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    HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Serial ATA International Organization: Serial ATA Revision 3.0 June 2, 2009 Gold Revision SATA-IO Board Members: Dell Computer Corporation Hewlett Packard Corporation Hitachi Global Storage Technologies, Inc. Intel Corporation Maxim Integrated Products Seagate Technology Western Digital Corporation Serial ATA Revision 3.0 - Gold Revision Serial ATA International Organization: Serial ATA Revision 3.0 specification ("Final Specification") is available for download at www.sata-io.org. SPECIFICATION DISCLAIMER THIS SPECIFICATION IS PROVIDED TO YOU “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE. THE AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO USE OR IMPLEMNETATION OF INFORMATION IN THIS SPECIFICATION. THE AUTHORS DO NOT WARRANT OR REPRESENT THAT SUCH USE WILL NOT INFRINGE SUCH RIGHTS. THE PROVISION OF THIS SPECIFICATION TO YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS. Copyright 2002-2009, Serial ATA International Organization. All rights reserved. For more information about Serial ATA, refer to the Serial ATA International Organization website at www.sata-io.org. All product names are trademarks, registered trademarks, or servicemarks of their respective owners. Serial ATA International Organization contact information: SATA-IO 3855 SW 153rd Drive Beaverton, Oregon 97006 USA Tel: +1 503-619-0572 Fax: +1 503-644-6708 E-mail: admin@sata-io.org Serial ATA Revision 3.0 Gold Revision page 2 of 663 TABLE OF CONTENTS 1 Revision History....................................................................................................................23 1.1 Revision 2.5 (Ratification Date October 27, 2005) ........................................................ 23 1.2 Revision 2.6 (Ratification Date February 15, 2007) ...................................................... 23 1.3 Revision 3.0 (Ratification Date: June 2, 2009) ............................................................. 23 2 Scope....................................................................................................................................25 3 Normative references ...........................................................................................................27 3.1 Approved references ..................................................................................................... 27 3.2 References under development .................................................................................... 29 3.3 Other references............................................................................................................ 29 4 Definitions, abbreviations, and conventions .........................................................................31 4.1 Definitions and abbreviations ........................................................................................ 31 4.1.1 Active Port ............................................................................................................. 31 4.1.2 ATA (AT Attachment)............................................................................................. 31 4.1.3 ATAPI (AT Attachment Packet Interface) device .................................................. 31 4.1.4 BER (bit error rate) ................................................................................................ 31 4.1.5 bitrate ..................................................................................................................... 31 4.1.6 bit synchronization ................................................................................................. 31 4.1.7 burst ....................................................................................................................... 31 4.1.8 byte ........................................................................................................................ 31 4.1.9 character ................................................................................................................ 31 4.1.10 character alignment ............................................................................................... 31 4.1.11 character slipping................................................................................................... 31 4.1.12 ClickConnect.......................................................................................................... 32 4.1.13 CLTF (Closed Loop Transfer Function)................................................................. 32 4.1.14 code violation......................................................................................................... 32 4.1.15 comma character ................................................................................................... 32 4.1.16 comma sequence .................................................................................................. 32 4.1.17 command aborted.................................................................................................. 32 4.1.18 command completion............................................................................................. 32 4.1.19 command packet ................................................................................................... 32 4.1.20 concentrator ........................................................................................................... 33 4.1.21 Control Block registers........................................................................................... 33 4.1.22 control character .................................................................................................... 33 4.1.23 control port ............................................................................................................. 33 4.1.24 control variable ...................................................................................................... 33 4.1.25 CRC (Cyclic Redundancy Check) ......................................................................... 33 4.1.26 data character ........................................................................................................ 33 4.1.27 data signal source.................................................................................................. 33 4.1.28 device..................................................................................................................... 33 4.1.29 device port ............................................................................................................. 33 4.1.30 DCB (DC block) ..................................................................................................... 33 4.1.31 differential signal.................................................................................................... 34 4.1.32 DJ (deterministic jitter – peak to peak) .................................................................. 34 4.1.33 DMA (direct memory access) ................................................................................ 34 4.1.34 Dword..................................................................................................................... 34 4.1.35 Dword synchronization .......................................................................................... 34 4.1.36 EMI (Electromagnetic Interference)....................................................................... 34 4.1.37 encoded character ................................................................................................. 34 4.1.38 endpoint device...................................................................................................... 34 4.1.39 elasticity buffer....................................................................................................... 34 4.1.40 eSATA.................................................................................................................... 34 4.1.41 Fbaud..................................................................................................................... 35 4.1.42 FER (frame error rate) ........................................................................................... 35 Serial ATA Revision 3.0 Gold Revision page 3 of 663 4.1.43 4.1.44 4.1.45 4.1.46 4.1.47 4.1.48 4.1.49 4.1.50 4.1.51 4.1.52 4.1.53 4.1.54 4.1.55 4.1.56 4.1.57 4.1.58 4.1.59 4.1.60 4.1.61 4.1.62 4.1.63 4.1.64 4.1.65 4.1.66 4.1.67 4.1.68 4.1.69 4.1.70 4.1.71 4.1.72 4.1.73 4.1.74 4.1.75 4.1.76 4.1.77 4.1.78 4.1.79 4.1.80 4.1.81 4.1.82 4.1.83 4.1.84 4.1.85 4.1.86 4.1.87 4.1.88 4.1.89 4.1.90 4.1.91 4.1.92 4.1.93 4.1.94 4.1.95 4.1.96 4.1.97 4.1.98 First-party DMA Data Phase.................................................................................. 35 First-party DMA access ......................................................................................... 35 FIS (Frame Information Structure)......................................................................... 35 frame...................................................................................................................... 35 Gen1 ...................................................................................................................... 35 Gen1i ..................................................................................................................... 35 Gen1m ................................................................................................................... 35 Gen1x .................................................................................................................... 35 Gen2 ...................................................................................................................... 35 Gen2i ..................................................................................................................... 35 Gen2m ................................................................................................................... 35 Gen2x .................................................................................................................... 36 Gen3 ...................................................................................................................... 36 Gen3i ..................................................................................................................... 36 HBA (Host Bus Adapter)........................................................................................ 36 HBWS (High Bandwidth Scope) ............................................................................ 36 HFTP (High Frequency Test Pattern).................................................................... 36 hot plug .................................................................................................................. 36 host port ................................................................................................................. 36 inactive port ........................................................................................................... 36 interrupt pending.................................................................................................... 36 immediate NCQ command .................................................................................... 37 ISI (inter-symbol interference) ............................................................................... 37 JMD (jitter measuring device) ................................................................................ 37 JTF (Jitter Transfer Function) ................................................................................ 37 junk ........................................................................................................................ 37 LBA (Logical Block Address) ................................................................................. 37 LBP (Lone Bit Pattern)........................................................................................... 37 LED (Light Emitting Diode) .................................................................................... 37 legacy mode .......................................................................................................... 38 legal character ....................................................................................................... 38 LFSR (Linear Feedback Shift Register)................................................................. 38 LFTP (low frequency test pattern) ......................................................................... 38 LL (laboratory load)................................................................................................ 38 LSS (laboratory sourced signal or lab-sourced signal).......................................... 38 MFTP (mid frequency test pattern)........................................................................ 38 NCQ streaming command ..................................................................................... 38 NCQ Non-streaming command ............................................................................. 38 OOB (Out-of-Band signaling) ................................................................................ 38 OS-aware hot plug................................................................................................. 39 OS-aware hot removal........................................................................................... 39 Phy offline .............................................................................................................. 39 PIO (programmed input/output) ............................................................................. 39 port address ........................................................................................................... 39 PRD (Physical Region Descriptor) ........................................................................ 39 primitive.................................................................................................................. 39 protocol-based port selection ................................................................................ 39 quiescent power condition ..................................................................................... 39 RJ (random jitter) ................................................................................................... 39 sector ..................................................................................................................... 39 SEMB (Serial ATA Enclosure Management Bridge) ............................................. 40 SEP (Storage Enclosure Processor) ..................................................................... 40 Shadow Register Block registers........................................................................... 40 side-band port selection......................................................................................... 40 SMART .................................................................................................................. 40 SSC (spread spectrum clocking) ........................................................................... 40 Serial ATA Revision 3.0 Gold Revision page 4 of 663 4.1.99 surprise hot plug .................................................................................................... 40 4.1.100 surprise hot removal .............................................................................................. 40 4.1.101 SYNC Escape........................................................................................................ 40 4.1.102 TDR (time domain reflectometer) .......................................................................... 40 4.1.103 TIA (timing interval analyzer) ................................................................................. 41 4.1.104 TJ (total jitter) ......................................................................................................... 41 4.1.105 UI (unit interval) ..................................................................................................... 41 4.1.106 unrecoverable error ............................................................................................... 41 4.1.107 UUT (unit under test) ............................................................................................. 41 4.1.108 VNA (vector network analyzer) .............................................................................. 41 4.1.109 warm plug .............................................................................................................. 41 4.1.110 word ....................................................................................................................... 41 4.1.111 xSATA.................................................................................................................... 41 4.1.112 zero crossing ......................................................................................................... 41 4.2 Conventions................................................................................................................... 41 4.2.1 Precedence............................................................................................................ 42 4.2.2 Keywords ............................................................................................................... 42 4.2.3 Numbering ............................................................................................................. 43 4.2.4 Dimensions ............................................................................................................ 43 4.2.5 Signal conventions................................................................................................. 43 4.2.6 State machine conventions ................................................................................... 44 4.2.7 Byte, word and Dword Relationships..................................................................... 44 5 General overview..................................................................................................................47 5.1 Architecture.................................................................................................................... 48 5.2 Usage Models................................................................................................................ 49 5.2.1 Internal 1 meter Cabled Host to Device................................................................. 52 5.2.2 Short Backplane to Device .................................................................................... 53 5.2.3 Long Backplane to Device ..................................................................................... 54 5.2.4 Internal 4-lane Cabled Disk Arrays ........................................................................ 55 5.2.5 System-to-System Interconnects – Data Center Applications (xSATA) ................ 57 5.2.6 System-to-System Interconnects – External Desktop Applications (eSATA)........ 59 5.2.7 Proprietary Serial ATA Disk Arrays ....................................................................... 60 5.2.8 Serial ATA and SAS .............................................................................................. 60 5.2.9 Potential External SATA Incompatibility Issues..................................................... 61 5.2.10 Mobile Applications................................................................................................ 61 5.2.11 Port Multiplier Example Applications ..................................................................... 62 6 Cables and Connectors ........................................................................................................67 6.1 Internal cables and connectors...................................................................................... 67 6.1.1 Internal Single Lane Description............................................................................ 67 6.1.2 Connector locations ............................................................................................... 70 6.1.3 Mating interfaces ................................................................................................... 79 6.1.4 Signal cable receptacle connector......................................................................... 83 6.1.5 Signal host plug connector .................................................................................... 85 6.1.6 Backplane connector ............................................................................................. 88 6.1.7 Power cable receptacle connector ........................................................................ 91 6.1.8 Internal single lane cable ....................................................................................... 93 6.1.9 Connector labeling................................................................................................. 94 6.1.10 Connector and cable assembly requirements and test procedures ...................... 94 6.1.11 Internal Multilane cables ........................................................................................ 98 6.1.12 Mini SATA Internal Multilane ............................................................................... 104 6.2 Internal Micro SATA Connector for 1.8” HDD ............................................................. 111 6.2.1 Usage model........................................................................................................ 111 6.2.2 General description.............................................................................................. 111 6.2.3 Connector location............................................................................................... 111 6.2.4 Mating interfaces ................................................................................................. 114 6.3 Internal Slimline cables and connectors ...................................................................... 120 Serial ATA Revision 3.0 Gold Revision page 5 of 663 6.3.1 Usage Models ...................................................................................................... 120 6.3.2 General description.............................................................................................. 121 6.3.3 Connector location and keep out zones .............................................................. 121 6.3.4 Mating interfaces ................................................................................................. 125 6.3.5 Backplane connector configuration and blind-mating tolerance.......................... 136 6.3.6 Connector labeling............................................................................................... 137 6.3.7 Connector and cable assembly requirements and test procedures .................... 137 6.4 Internal LIF-SATA Connector for 1.8” HDD ................................................................. 138 6.4.1 General description.............................................................................................. 138 6.4.2 Connector Locations............................................................................................ 139 6.4.3 Mating interfaces ................................................................................................. 141 Figure 87 defines the interface dimensions for the internal LIF-SATA embedded type connector with both signal and power segments. ............................................................... 141 Figure 88 defines the interface dimensions for the internal LIF-SATA device surface mounting type connector. .................................................................................................... 143 6.4.4 Internal LIF-SATA pin signal definition and contact mating sequence............... 145 6.4.5 Housing and contact electrical requirement ........................................................ 146 6.5 External cables and connectors .................................................................................. 147 6.5.1 External Single Lane............................................................................................ 147 6.5.2 External Multilane ................................................................................................ 157 6.5.3 Mini SATA External Multilane .............................................................................. 161 6.6 Cable and Connector Electrical Specifications............................................................ 165 6.6.1 Serial ATA Cable ................................................................................................. 165 6.6.2 Cable/Connector Test Methodology .................................................................... 166 6.7 Power Segment Pin P11 Definition (Optional) ............................................................ 174 6.7.1 Device Activity Signal .......................................................................................... 175 6.7.2 Staggered Spin-up Disable Control ..................................................................... 177 6.8 Precharge and Device Presence Detection ................................................................ 179 6.8.1 Device Requirements .......................................................................................... 179 6.8.2 Receptacle Precharge (Informative).................................................................... 179 6.8.3 Presence Detection (Informative) ........................................................................ 180 7 Phy Layer............................................................................................................................183 7.1 Descriptions of Phy Electrical Specifications............................................................... 183 7.1.1 List of Services .................................................................................................... 183 7.1.2 Low Level Electronics Block Diagrams (Informative) .......................................... 184 7.1.3 Compliance Testing ............................................................................................. 191 7.1.4 Link Performance................................................................................................. 192 7.2 Electrical Specifications ............................................................................................... 192 7.2.1 Physical Layer Requirements Tables .................................................................. 193 7.2.2 Phy Layer Requirements Details ......................................................................... 211 7.2.3 Loopback ............................................................................................................. 227 7.2.4 Test Pattern Requirements.................................................................................. 230 7.2.5 Hot Plug Considerations ...................................................................................... 247 7.2.6 Mated Connector Pair Definition.......................................................................... 250 7.2.7 Compliance Interconnect Channels (Gen1x, Gen2x, Gen3i) .............................. 251 7.2.8 Impedance Calibration (Optional)........................................................................ 254 7.3 Jitter ............................................................................................................................. 255 7.3.1 Jitter Definition ..................................................................................................... 256 7.3.2 Reference Clock Definition .................................................................................. 256 7.3.3 Spread Spectrum Clocking .................................................................................. 258 7.3.4 Jitter Budget......................................................................................................... 260 7.4 Measurements ............................................................................................................. 260 7.4.1 Frame Error Rate Testing .................................................................................... 261 7.4.2 Measurement of Differential Voltage Amplitudes (Gen1, Gen2) ......................... 264 7.4.3 Measurement of Differential Voltage Amplitudes (Gen3i) ................................... 275 7.4.4 Rise and Fall Times ............................................................................................. 276 Serial ATA Revision 3.0 Gold Revision page 6 of 663 7.4.5 Transmitter Amplitude.......................................................................................... 278 7.4.6 Receive Amplitude............................................................................................... 279 7.4.7 Long Term Frequency Accuracy ......................................................................... 283 7.4.8 Jitter Measurements ............................................................................................ 284 7.4.9 Transmit Jitter (Gen1i, Gen2i, Gen1m, Gen2m, Gen1x, and Gen2x) ................. 287 7.4.10 Transmit Jitter (Gen3i) ......................................................................................... 289 7.4.11 Receiver Tolerance (Gen1i, Gen2i, Gen1m, Gen2m, Gen1x, and Gen2x)......... 290 7.4.12 Receiver Tolerance (Gen3i) ................................................................................ 292 7.4.13 Return Loss and Impedance Balance ................................................................. 294 7.4.14 SSC Profile .......................................................................................................... 298 7.4.15 Intra-Pair Skew .................................................................................................... 298 7.4.16 Sequencing Transient Voltage ............................................................................ 300 7.4.17 AC Coupling Capacitor ........................................................................................ 301 7.4.18 TX Amplitude Imbalance...................................................................................... 301 7.4.19 TX Rise/Fall Imbalance........................................................................................ 301 7.4.20 TX AC Common Mode Voltage (Gen2i, Gen2m) ................................................ 302 7.4.21 Tx AC Common Mode Voltage (Gen3i)............................................................... 302 7.4.22 OOB Common Mode Delta.................................................................................. 302 7.4.23 OOB Differential Delta ......................................................................................... 303 7.4.24 Squelch Detector Tests ....................................................................................... 303 7.4.25 OOB Signaling Tests ........................................................................................... 304 7.4.26 TDR Differential Impedance (Gen1i / Gen1m) .................................................... 305 7.4.27 TDR Single-Ended Impedance (Gen1i / Gen1m)................................................ 306 7.4.28 DC Coupled Common Mode Voltage (Gen1i / Gen1m) ...................................... 307 7.4.29 AC Coupled Common Mode Voltage (Gen1i / Gen1m) ...................................... 308 7.4.30 Sequencing Transient Voltage - Laboratory Load (Gen3i).................................. 309 7.5 Interface States............................................................................................................ 309 7.5.1 Out Of Band Signaling ......................................................................................... 309 7.5.2 Idle Bus Condition................................................................................................ 317 7.6 Elasticity Buffer Management...................................................................................... 317 8 OOB and Phy Power States ...............................................................................................319 8.1 Interface Power States ................................................................................................ 319 8.2 Asynchronous Signal Recovery (Optional).................................................................. 319 8.2.1 Unsolicited COMINIT Usage (Informative) .......................................................... 319 8.3 OOB and Signature FIS return (Informative) ............................................................... 320 8.4 Power-On Sequence State Machine ........................................................................... 320 8.4.1 Host Phy Initialization State Machine .................................................................. 320 8.4.2 Device Phy Initialization State Machine............................................................... 325 8.4.3 Speed Negotiation ............................................................................................... 329 9 Link Layer ...........................................................................................................................335 9.1 Overview...................................................................................................................... 335 9.1.1 Frame Transmission ............................................................................................ 335 9.1.2 Frame Reception ................................................................................................. 335 9.2 Encoding Method......................................................................................................... 335 9.2.1 Notation and Conventions ................................................................................... 336 9.2.2 Character Code ................................................................................................... 337 9.2.3 Transmission Summary ....................................................................................... 345 9.2.4 Reception Summary ............................................................................................ 346 9.3 Transmission Overview ............................................................................................... 348 9.4 Primitives ..................................................................................................................... 348 9.4.1 Overview .............................................................................................................. 348 9.4.2 Primitive Descriptions .......................................................................................... 349 9.4.3 Primitive Encoding ............................................................................................... 350 9.4.4 9.4.5 9.4.6 DMATP Primitive .................................................................................................. 351 CONTP Primitive .................................................................................................. 351 ALIGNP Primitive.................................................................................................. 354 Serial ATA Revision 3.0 Gold Revision page 7 of 663 9.4.7 Flow Control Signaling Latency ........................................................................... 354 9.4.8 Examples of Primitive Usage (Informative) ......................................................... 356 9.5 CRC and Scrambling ................................................................................................... 358 9.5.1 Relationship Between Scrambling of FIS Data and Repeated Primitives ........... 358 9.5.2 Relationship Between Scrambling and CRC ....................................................... 358 9.5.3 Scrambling Disable (Informative) ........................................................................ 359 9.6 Link Layer State Machine ............................................................................................ 359 9.6.1 Terms Used in Link Layer Transition Tables ....................................................... 359 9.6.2 Link Idle State Diagram ....................................................................................... 360 9.6.3 Link Transmit State Diagram ............................................................................... 363 9.6.4 Link Receive State Diagram ................................................................................ 370 9.6.5 Link Power Mode State Diagram......................................................................... 376 10 Transport Layer ..................................................................................................................381 10.1 Overview...................................................................................................................... 381 10.1.1 FIS construction................................................................................................... 381 10.1.2 FIS decomposition ............................................................................................... 381 10.2 Frame Information Structure (FIS)............................................................................... 381 10.2.1 Overview .............................................................................................................. 381 10.2.2 Payload content ................................................................................................... 382 10.3 FIS Types .................................................................................................................... 382 10.3.1 FIS Type values ................................................................................................... 382 10.3.2 CRC Errors on Data FISes .................................................................................. 383 10.3.3 All FIS types......................................................................................................... 383 10.3.4 Register - Host to Device..................................................................................... 384 10.3.5 Register - Device to Host..................................................................................... 386 10.3.6 Set Device Bits - Device to Host.......................................................................... 387 10.3.7 DMA Activate - Device to Host ............................................................................ 388 10.3.8 DMA Setup – Device to Host or Host to Device (Bidirectional) ........................... 389 10.3.9 BIST Activate - Bidirectional ................................................................................ 392 10.3.10 PIO Setup – Device to Host................................................................................. 395 10.3.11 Data - Host to Device or Device to Host (Bidirectional)....................................... 397 10.4 Host transport states.................................................................................................... 399 10.4.1 Host transport idle state diagram......................................................................... 399 10.4.2 Host Transport transmit command FIS diagram ................................................. 402 10.4.3 Host Transport transmit control FIS diagram....................................................... 403 10.4.4 Host Transport transmit DMA Setup – Device to Host or Host to Device FIS state diagram 404 10.4.5 Host Transport transmit BIST Activate FIS.......................................................... 405 10.4.6 Host Transport decomposes Register FIS diagram ............................................ 406 10.4.7 Host Transport decomposes a Set Device Bits FIS state diagram ..................... 407 10.4.8 Host Transport decomposes a DMA Activate FIS diagram................................. 408 10.4.9 Host Transport decomposes a PIO Setup FIS state diagram ............................. 411 10.4.10 Host Transport decomposes a DMA Setup FIS state diagram ........................... 414 10.4.11 Host transport decomposes a BIST Activate FIS state diagram ......................... 415 10.5 Device transport states ................................................................................................ 416 10.5.1 Device transport idle state diagram ..................................................................... 416 10.5.2 Device Transport sends Register – Device to Host state diagram...................... 417 10.5.3 Device Transport sends Set Device Bits FIS state diagram................................ 418 10.5.4 Device Transport transmit PIO Setup – Device to Host FIS state diagram......... 419 10.5.5 Device Transport transmit DMA Activate FIS state diagram ............................... 420 10.5.6 Device Transport transmit DMA Setup – Device to Host FIS state diagram....... 421 10.5.7 Device Transport transmit Data – Device to Host FIS diagram........................... 422 10.5.8 Device Transport transmit BIST Activate FIS diagram....................................... 423 10.5.9 Device Transport decomposes Register – Host to Device state diagram........... 425 10.5.10 Device Transport decomposes Data (Host to Device) FIS state diagram........... 426 10.5.11 Device Transport decomposes DMA Setup – Host to Device state diagram...... 427 Serial ATA Revision 3.0 Gold Revision page 8 of 663 10.5.12 Device Transport decomposes a BIST Activate FIS state diagram .................... 428 11 Device Command Layer protocol .......................................................................................429 11.1 Power-on and COMRESET protocol ........................................................................... 429 11.2 Device Idle protocol ..................................................................................................... 432 11.3 Software reset protocol................................................................................................ 437 11.4 EXECUTE DEVICE DIAGNOSTIC command protocol ............................................... 440 11.5 DEVICE RESET command protocol............................................................................ 442 11.6 Non-data command protocol ....................................................................................... 442 11.7 PIO data-in command protocol.................................................................................... 443 11.8 PIO data-out command protocol.................................................................................. 445 11.9 DMA data in command protocol .................................................................................. 446 11.10 DMA data out command protocol ............................................................................ 447 11.11 PACKET protocol..................................................................................................... 448 11.12 READ DMA QUEUED command protocol............................................................... 454 11.13 WRITE DMA QUEUED command protocol ............................................................. 456 11.14 FPDMA QUEUED command protocol ..................................................................... 458 12 Host Command Layer protocol ...........................................................................................465 12.1 FPDMA QUEUED command protocol ......................................................................... 465 13 Application Layer ................................................................................................................471 13.1 Parallel ATA Emulation................................................................................................ 471 13.1.1 Software Reset .................................................................................................... 471 13.1.2 Master-only emulation ......................................................................................... 472 13.1.3 Master/Slave emulation (optional) ....................................................................... 473 13.2 IDENTIFY (PACKET) DEVICE .................................................................................... 479 13.2.1 IDENTIFY DEVICE .............................................................................................. 479 13.2.2 IDENTIFY PACKET DEVICE .............................................................................. 487 13.2.3 Determining Support for Serial ATA Features ..................................................... 491 13.3 SET FEATURES.......................................................................................................... 492 13.3.1 Enable/Disable Non-Zero Offsets in DMA Setup ................................................ 492 13.3.2 Enable/Disable DMA Setup FIS Auto-Activate Optimization............................... 492 13.3.3 Enable/Disable Device-Initiated Interface Power State Transitions .................... 493 13.3.4 Enable/Disable Guaranteed in-Order Data Delivery ........................................... 493 13.3.5 Enable/Disable Asynchronous Notification.......................................................... 493 13.3.6 Enable/Disable Software Settings Preservation .................................................. 493 13.3.7 Enable/Disable Device Automatic Partial to Slumber Transitions ....................... 493 13.4 Device Configuration Overlay...................................................................................... 494 13.4.1 Device Configuration Overlay Identify ................................................................. 494 13.4.2 Device Configuration Overlay Set ....................................................................... 495 13.5 Software Settings Preservation (Optional) .................................................................. 497 13.5.1 Warm Reboot Considerations (Informative) ........................................................ 498 13.6 Native Command Queuing (Optional) ......................................................................... 498 13.6.1 Definition .............................................................................................................. 499 13.6.2 Intermixing Non-Native Queued Commands and Native Queued Commands ... 503 13.6.3 Command Definitions .......................................................................................... 504 13.6.4 First-party DMA HBA Support (Informative) ........................................................ 522 13.7 SATA Logs................................................................................................................... 523 13.7.1 Log Address Definitions....................................................................................... 523 13.7.2 General Purpose Log Directory (00h).................................................................. 523 13.7.3 Queued Error Log (10h)....................................................................................... 524 13.7.4 Phy Event Counters Log (11h) ............................................................................ 526 13.7.5 NCQ Queue Management Log (12h) ................................................................. 526 13.8 Asynchronous Notification (Optional) .......................................................................... 527 13.8.1 Set Device Bits FIS Notification bit ...................................................................... 527 13.8.2 Notification Mechanism........................................................................................ 527 13.8.3 State Diagram for Asynchronous Notification...................................................... 527 13.8.4 ATAPI Notification................................................................................................ 528 Serial ATA Revision 3.0 Gold Revision page 9 of 663 13.9 Phy Event Counters (Optional) .................................................................................... 528 13.9.1 Counter Reset Mechanisms ................................................................................ 529 13.9.2 Counter Identifiers ............................................................................................... 529 13.9.3 Phy Event Counters Log (11h) ............................................................................ 532 13.10 Staggered Spin-up (Optional) .................................................................................. 533 13.11 Non-512 Byte Sector Size (Informative) .................................................................. 533 13.12 Defect Management (Informative) ........................................................................... 534 13.12.1 Overview (Informative)......................................................................................... 534 13.12.2 Typical Serial ATA Reliability Metrics (Informative)............................................. 534 13.12.3 An Overview of Serial ATA Defect Management (Informative) ........................... 534 13.12.4 Continuous Background Defect Scanning (Informative) ..................................... 535 13.12.5 Self-Monitoring, Analysis and Reporting Technology (Informative) .................... 535 13.13 Enclosure Services/Management (Optional) ........................................................... 536 13.13.1 Overview .............................................................................................................. 536 13.13.2 Topology .............................................................................................................. 536 13.13.3 Limitations............................................................................................................ 538 13.13.4 Definition .............................................................................................................. 538 13.13.5 SES and SAF-TE Extensions .............................................................................. 544 13.13.6 Enclosure Services Hardware Interface .............................................................. 550 13.14 HDD Activity Indication (Optional) ........................................................................... 551 13.14.1 HDD Activity Emulation of Desktop Behavior ...................................................... 551 13.14.2 Activity/Status Indication Reference (Informative)............................................... 552 13.15 Port Multiplier Discovery and Enumeration ............................................................. 555 13.15.1 Power-up ............................................................................................................. 555 13.15.2 Resets.................................................................................................................. 556 13.15.3 Software Initialization Sequences (Informative) .................................................. 557 13.15.4 Port Multiplier Discovery and Device Enumeration (Informative) ........................ 557 13.16 Automatic Partial to Slumber Transitions ................................................................ 559 14 Host adapter register interface ...........................................................................................560 14.1 Status and Control Registers....................................................................................... 560 14.1.1 SStatus register ................................................................................................... 561 14.1.2 SError register ..................................................................................................... 561 14.1.3 SControl register.................................................................................................. 563 14.1.4 SActive register.................................................................................................... 564 14.1.5 SNotification register (Optional)........................................................................... 565 15 Error handling .....................................................................................................................567 15.1 Architecture.................................................................................................................. 567 15.2 Phy error handling overview ........................................................................................ 568 15.2.1 Error detection ..................................................................................................... 568 15.2.2 Error control actions............................................................................................. 569 15.2.3 Error reporting...................................................................................................... 570 15.3 Link layer error handling overview............................................................................... 570 15.3.1 Error detection ..................................................................................................... 570 15.3.2 Error control actions............................................................................................. 570 15.3.3 Error reporting...................................................................................................... 571 15.4 Transport layer error handling overview ...................................................................... 571 15.4.1 Error detection ..................................................................................................... 572 15.4.2 Error control actions............................................................................................. 572 15.4.3 Error reporting...................................................................................................... 573 15.5 Application layer error handling overview.................................................................... 574 15.5.1 Error detection ..................................................................................................... 574 15.5.2 Error control actions............................................................................................. 574 16 Port Multiplier ......................................................................................................................577 16.1 Introduction .................................................................................................................. 577 16.2 Overview...................................................................................................................... 577 16.3 Definition ...................................................................................................................... 578 Serial ATA Revision 3.0 Gold Revision page 10 of 663 16.3.1 Addressing Mechanism ....................................................................................... 578 16.3.2 Device Port Requirements................................................................................... 578 16.3.3 Policies................................................................................................................. 580 16.4 Port Multiplier Registers .............................................................................................. 590 16.4.1 General Status and Control Registers................................................................. 590 16.4.2 Port Status and Control Registers ....................................................................... 599 16.5 Port Multiplier Command Definitions ........................................................................... 600 16.5.1 READ PORT MULTIPLIER.................................................................................. 600 16.5.2 WRITE PORT MULTIPLIER ................................................................................ 602 16.5.3 Interrupts.............................................................................................................. 604 16.6 Controlling PM Port Value and Interface Power Management.................................... 604 16.7 Switching Types (Informative) ..................................................................................... 604 16.7.1 Command-Based Switching ................................................................................ 605 16.7.2 FIS-Based Switching ........................................................................................... 605 17 Port Selector .......................................................................................................................607 17.1 Example Applications .................................................................................................. 607 17.2 Overview...................................................................................................................... 608 17.3 Active Port Selection.................................................................................................... 609 17.3.1 Protocol-based Port Selection ............................................................................. 609 17.3.2 Side-band Port Selection ..................................................................................... 612 17.3.3 Behavior during a change of active port .............................................................. 612 17.4 Behavior and Policies .................................................................................................. 613 17.4.1 Control State Machine ......................................................................................... 613 17.4.2 BIST support ........................................................................................................ 617 17.4.3 Flow control signaling latency.............................................................................. 617 17.4.4 Power Management............................................................................................. 617 17.4.5 OOB Phy signals ................................................................................................. 618 17.4.6 Hot Plug ............................................................................................................... 618 17.4.7 Speed Negotiation ............................................................................................... 618 17.4.8 Spread spectrum clocking ................................................................................... 619 17.5 Power-up and Resets .................................................................................................. 619 17.5.1 Power-up ............................................................................................................. 619 17.5.2 Resets.................................................................................................................. 619 17.6 Host Implementation (Informative) .............................................................................. 619 17.6.1 Software Method for Protocol-based Selection (Informative).............................. 619 Appendix A. Sample Code for CRC and Scrambling (Informative) ..........................................623 A.1 CRC calculation ........................................................................................................... 623 A.1.1 Overview .............................................................................................................. 623 A.1.2 Maximum frame size............................................................................................ 623 A.1.3 Example code for CRC algorithm ........................................................................ 623 A.1.4 Example code for CRC algorithm ........................................................................ 623 A.1.5 Example CRC implementation output ................................................................. 625 A.2 Scrambling calculation................................................................................................. 626 A.2.1 Overview .............................................................................................................. 626 A.2.2 Example code for scrambling algorithm .............................................................. 626 A.2.3 Example scrambler implementation .................................................................... 626 A.2.4 Example scrambler implementation output ......................................................... 629 A.3 Example frame............................................................................................................. 630 Appendix B. Command processing overview (Informative) ......................................................631 B.1 Non-data commands ................................................................................................... 631 B.2 DMA read by host from device .................................................................................... 631 B.3 DMA write by host to device ........................................................................................ 631 B.4 PIO data read from the device..................................................................................... 632 B.5 PIO data write to the device ........................................................................................ 632 B.6 ATA Tagged Command Queuing DMA read from device ........................................... 633 B.7 ATA Tagged Command Queuing DMA write to device ............................................... 634 Serial ATA Revision 3.0 Gold Revision page 11 of 663 B.8 ATAPI Packet commands with PIO data in ................................................................. 634 B.9 ATAPI Packet commands with PIO data out ............................................................... 635 B.10 ATAPI Packet commands with DMA data in ............................................................... 636 B.11 ATAPI Packet commands with DMA data out ............................................................. 637 B.12 Odd word count considerations ................................................................................... 638 B.12.1 DMA read from target for odd word count ........................................................... 638 B.12.2 DMA write by host to target for odd word count .................................................. 638 B.13 PIO data read from the device..................................................................................... 639 B.14 PIO data write to the device ........................................................................................ 639 B.15 Native Command Queuing Examples (Informative) .................................................... 639 B.15.1 Queued Commands with Out of Order Completion............................................. 640 B.15.2 Interrupt Aggregation ........................................................................................... 641 Appendix C. Device Emulation of nIEN with Interrupt Pending (Informative) .......................643 Appendix D. I/O Controller Module (Informative) ..................................................................644 D.1 Supported Configurations ............................................................................................ 645 D.1.1 Single I/O Controller Signals ............................................................................... 645 D.1.2 Dual I/O Controller Signals .................................................................................. 646 D.1.3 Further optional features...................................................................................... 646 D.2 Optional High Speed Channel configurations ............................................................. 647 D.3 Optional Low Speed Channel configurations .............................................................. 649 D.4 I/O Controller Module Connectors ............................................................................... 650 D.4.1 I/O Controller Module Connector ......................................................................... 650 D.5 I/O Controller Module Connector Locations ................................................................ 653 D.5.1 Purpose................................................................................................................ 653 D.6 Pinout Listing ............................................................................................................... 656 D.7 Signal Descriptions ...................................................................................................... 657 Appendix E. Jitter Formulas without SSC (Informative)............................................................662 E.1 Clock to Data ............................................................................................................... 662 E.2 Data to Data (shown for historical reasons) ................................................................ 662 Serial ATA Revision 3.0 Gold Revision page 12 of 663 LIST OF FIGURES Figure 1 – Byte, word and Dword relationships............................................................................. 45 Figure 2 – Parallel ATA device connectivity .................................................................................. 47 Figure 3 – Serial ATA connectivity ................................................................................................ 48 Figure 4 – Communication layers.................................................................................................. 49 Figure 5 – Internal 1 meter Cabled Host to Device Application .................................................... 52 Figure 6 – Short Backplane to Device Application ........................................................................ 54 Figure 7 – Long Backplane to Device Application......................................................................... 55 Figure 8 – Internal 4-lane Cabled Disk Array ................................................................................ 56 Figure 9 – System-to-System Data Center Interconnects............................................................. 58 Figure 10 – External Desktop Application ..................................................................................... 59 Figure 11 – SATA Disk Arrays....................................................................................................... 60 Figure 12 - Embedded LIF-SATA Application ............................................................................... 62 Figure 13 – Enclosure example using Port Multipliers with Serial ATA as the connection within the rack ........................................................................................................................................ 63 Figure 14 – Enclosure example using Port Multipliers with a different connection within the rack 64 Figure 15 – Mobile docking station example using a Port Multiplier ............................................. 65 Figure 16 – Serial ATA connector examples................................................................................. 68 Figure 17 – SATA Cable / Connector Connection Diagram .......................................................... 69 Figure 18 – SATA Host / Device Connection Diagram.................................................................. 70 Figure 19 – Optical Device Plug Connector Location on 5.25" form factor................................... 71 Figure 20 – Non-Optical Alternate Device Plug Connector Location on 5.25" form factor ........... 72 Figure 21 – Device Plug Connector Location on 3.5” Side Mounted Device ................................ 73 Figure 22 – Device Plug Connector Location on 3.5" Bottom Mounted Device............................ 74 Figure 23 – Device Plug Connector Location on 2.5” Side Mounted Device ................................ 75 Figure 24 – Device Plug Connector Location on 2.5" Bottom Mounted Device............................ 76 Figure 25 – Device Plug Connector Location on 1.8" Side Mounted Device ................................ 77 Figure 26 – Device Plug Connector Location on 1.8" Bottom Mounted Device............................ 78 Figure 27 – Device Plug Connector Keep Out Zones ................................................................... 79 Figure 28 – Device Plug Connector............................................................................................... 80 Figure 29 – Device Plug Connector (additional views).................................................................. 81 Figure 30 – Connector Pin and Feature Locations........................................................................ 83 Figure 31 – Cable receptacle connector interface dimensions ..................................................... 84 Figure 32 – Latching signal cable receptacle (ClickConnect) ....................................................... 85 Figure 33 – Host signal plug connector interface dimensions....................................................... 86 Figure 34 – Non-Latching Connector Stack Spacing and Orientation .......................................... 87 Figure 35 – Latching Connector Stack Spacing and Orientation .................................................. 87 Figure 36 – Backplane connector interface dimensions................................................................ 89 Figure 37 – Connector pair blind-mate misalignment tolerance.................................................... 90 Figure 38 – Device-backplane mating configuration ..................................................................... 91 Figure 39 – Power receptacle connector interface dimensions .................................................... 92 Figure 40 – Latching power cable receptacle................................................................................ 93 Figure 41 – Detailed cross-section of an example internal single lane cable ............................... 94 Figure 42 – Isometric drawings of the internal 2 Lane cable and connector............................... 100 Figure 43 – Isometric drawings of the internal 4 Lane cable and connector............................... 100 Figure 44 – 4 Lane Pin Assignments........................................................................................... 101 Figure 45 – 4 Lane to 4 x 1 Lanes, Fanout Implementation........................................................ 102 Figure 46 – 4 Lane Fanout Pin Assignments .............................................................................. 103 Figure 47 – 2 Lane Fanout Pin Assignments .............................................................................. 104 Figure 48 Isometric Drawings for Mini SATA Internal Multilane................................................. 105 Figure 49 Mini SATA Internal Multilane Connector Pin Assignments ........................................ 107 Figure 50 Mini SATA Internal Multilane System, Symmetric Cable Implementation ................. 108 Figure 51 Mini SATA Internal Multilane System, Controller based fanout cable implementation ............................................................................................................................................. 109 Serial ATA Revision 3.0 Gold Revision page 13 of 663 Figure 52 Mini SATA Internal Multilane System, Backplane based fanout cable implementation ............................................................................................................................................. 110 Figure 53 Device internal micro SATA connector location for 1.8” HDD.................................... 112 Figure 54 Device internal micro SATA connector location for 1.8” HDD.................................... 113 Figure 55 Device internal micro SATA plug connector............................................................... 116 Figure 56 Internal micro SATA backplane connector................................................................. 116 Figure 57 Internal micro SATA power receptable connector ..................................................... 117 Figure 58 Internal micro SATA connector pair blind-mate misalignment capability................... 118 Figure 59 - 7.0 mm Slimline Drive Connector Locations ............................................................. 122 Figure 60 - 9.5 mm/12.7 mm Slimline Drive Connector Locations.............................................. 123 Figure 61 - 7.0 mm Slimline Drive Connector Location (Section A-A) ........................................ 124 Figure 62 - 9.5 mm Slimline Drive Connector Location (Section A-A) ........................................ 124 Figure 63 - 12.7 mm Slimline Drive Connector Location (Section A-A) ...................................... 125 Figure 64 – 7 mm slimline device plug connector interface dimensions ..................................... 126 Figure 65 - 7.0 mm Slimline device plug connector interface dimensions Section A-A .............. 127 Figure 66 - 7.0 mm Slimline device plug connector interface dimensions Section B-B .............. 127 Figure 67 - 7.0 mm Slimline device plug connector interface dimensions detail D..................... 127 Figure 68 - 7.0 mm Slimline device plug connector interface dimensions optional hold down mounting .............................................................................................................................. 127 Figure 69 – Slimline Device plug connector interface dimensions.............................................. 129 Figure 70 - Slimline Device plug connector interface dimensions (Section A-A) ........................ 130 Figure 71 - Slimline Device plug connector interface dimensions (Section B-B) ........................ 130 Figure 72 - Slimline Device plug connector interface dimensions (Section C-C)........................ 130 Figure 73 - Slimline Device plug connector interface dimensions (Detail F)............................... 130 Figure 74 - Slimline Device plug connector interface dimensions (Section ................................ 130 Figure 75 – Slimline Device Plug Connector Optional Hold Down Mounting.............................. 130 Figure 76 – Slimline Connector Pin and Feature Locations ........................................................ 132 Figure 77 – Slimline Power receptacle connector interface dimensions..................................... 133 Figure 78 – Slimline Power receptacle connector Option with Latch .......................................... 134 Figure 79 – Slimline Power receptacle connector Option with Bump ......................................... 134 Figure 80 – Slimline Host receptacle connector interface dimensions........................................ 135 Figure 81 – Slimline Host receptacle connector interface dimensions Section C-C ................... 136 Figure 82 – Slimline Host receptacle connector interface dimensions Section X-X ................... 136 Figure 83 – Slimline Host receptacle connector interface dimensions Section Y-Y ................... 136 Figure 84 – Slimline Connector pair blind-mate misalignment tolerance .................................... 137 Figure 85 - Internal LIF-SATA connector location for 1.8” HDD.................................................. 139 Figure 86 - Internal LIF-SATA connector location for 1.8” SSD bulk of single-sided mount type 140 Figure 87 - Device internal LIF SATA embedded type connector............................................... 142 Figure 88 - Device internal LIF-SATA surface mounting type connector .................................... 143 Figure 89 - FPC for Internal LIF SATA ........................................................................................ 144 Figure 90 – Usage Model for HBA with external cable and single device enclosure.................. 148 Figure 91 – Usage Model for on-Board Serial ATA Connector with extension cable to external cable to disk......................................................................................................................... 149 Figure 92 – Renderings of External Serial ATA cable receptacle and right angle plug .............. 150 Figure 93 – Mechanical dimensions of External Serial ATA cable receptacle assembly............ 151 Figure 94 – Mechanical dimensions of External Serial ATA RA SMT plug................................. 152 Figure 95 – Mechanical dimensions of External SATA RA SMT plug – Reversed Pin Out ........ 153 Figure 96 – Mechanical dimensions of External Serial ATA RA Through-hole........................... 154 Figure 97 – Mechanical dimensions of External Serial ATA Vertical SMT plug.......................... 155 Figure 98 – Mechanical dimensions of External Serial ATA Vertical Through-hole plug............ 156 Figure 99 –External Multilane cable and connector .................................................................... 158 Figure 100 – Multilane Cable Connector Blocking Key Locations .............................................. 159 Figure 101 – Plug/Receptacle Keying ......................................................................................... 160 Figure 102 Mini SATA External Multilane System, Key Features .............................................. 162 Figure 103 Mini SATA External Multilane System, Key Slots 1 and 4 for “x level” Signals ....... 163 Figure 104 Mini SATA External Multilane System, Key Slots 7 for “m level” Signals ................ 163 Serial ATA Revision 3.0 Gold Revision page 14 of 663 Figure 105 Mini SATA External Multilane Connector Pin Assignments ..................................... 164 Figure 106 – Example activity signal electrical block diagram .................................................... 175 Figure 107 – Example host LED driver circuits ........................................................................... 177 Figure 108 – Example host circuit for signaling staggered spin-up disable ................................ 178 Figure 109 – Typical precharge configuration ............................................................................. 179 Figure 110 – Example presence detection implementation ........................................................ 181 Figure 111 – Physical Plant Overall Block Diagram (Informative) .............................................. 185 Figure 112 – Analog Front End (AFE) Block Diagram ................................................................ 188 Figure 113 – Analog Front End (AFE) Cabling............................................................................ 190 Figure 114 – The Simplex Link.................................................................................................... 191 Figure 115 – Common Mode Biasing Examples for Gen1i (Informative).................................... 212 Figure 116 – Common Mode Biasing for Gen1x, Gen2i, Gen2x, and Gen3i .............................. 213 Figure 117 – Differential Return Loss Limits ............................................................................... 215 Figure 118 – Common Mode Return Loss Limits........................................................................ 216 Figure 119 – Impedance Balance Limits ..................................................................................... 216 Figure 120 – Differential Return Loss Limits,Gen3i, TX and RX ................................................. 217 Figure 121 – Signal Rise and Fall Times .................................................................................... 218 Figure 122 – TX Intra-Pair Skew ................................................................................................. 219 Figure 123 – OOB Differential Delta (at Compliance Point with AC Coupling) ........................... 220 Figure 124 – LL Laboratory Load ................................................................................................ 222 Figure 125 – LSS Lab-Sourced Signal ........................................................................................ 223 Figure 126 – RX Differential Input Voltage Conditions................................................................ 224 Figure 127 – RX Intra-Pair Skew................................................................................................. 225 Figure 128 – Far-End Retimed Loopback ................................................................................... 228 Figure 129 – Far-End Analog Loopback ..................................................................................... 229 Figure 130 – Near-End Analog Loopback ................................................................................... 230 Figure 131 – Compliant Test Patterns......................................................................................... 231 Figure 132 – Example Circuit for Common Mode Transients ..................................................... 248 Figure 133 – Mated Connector Pair ............................................................................................ 250 Figure 134 – Mated Connector Pair, Pin Tail Detail .................................................................... 250 Figure 135 – Compliance Channel Loss for Gen3i ..................................................................... 252 Figure 136 – Compliance Channel Loss for Gen2x .................................................................... 253 Figure 137 – Compliance Channel Loss for Gen1x .................................................................... 254 Figure 138 – SSC Profile Example: Triangular ........................................................................... 259 Figure 139 – Spectral Fundamental Frequency Comparison ..................................................... 260 Figure 140 – Differential Voltage Amplitude Measurement......................................................... 264 Figure 141 – Differential Voltage Amplitude Measurement Pattern Example ............................. 265 Figure 142 – LFTP Pattern on High BW Scope (HBWS) ............................................................ 273 Figure 143 – Single Ended Rise and Fall Time........................................................................... 277 Figure 144 – Transmit Amplitude Test with Laboratory Load ..................................................... 278 Figure 145 – Transmit Amplitude Test with Compliance Interconnect Channel ......................... 279 Figure 146 – Receiver Amplitude Test--Setting Levels ............................................................... 280 Figure 147 – Receiver Amplitude Test ........................................................................................ 280 Figure 148 - Voltage at Receiver Input........................................................................................ 281 Figure 149 – TX Long Term Frequency Measurement ............................................................... 283 Figure 150- Receiver Model for Jitter .......................................................................................... 284 Figure 151 – Jitter at Receiver .................................................................................................... 285 Figure 152 – Jitter at Receiver, High Pass Function ................................................................... 285 Figure 153 – JTF and CLTF Definition ........................................................................................ 286 Figure 154 – Transmitter Jitter Test (Gen1i, Gen2i).................................................................... 288 Figure 155 – Transmit Jitter Test with Compliance Interconnect Channel (Gen1x, Gen2x)....... 288 Figure 156 – Transmitter Random Jitter Test (Gen3i)................................................................. 289 Figure 157 – Transmitter Total Jitter Test (Gen3i) ...................................................................... 290 Figure 158 – Receiver Jitter and CM Tolerance Test—Setting Levels ....................................... 291 Figure 159 – Receiver Jitter and CM Tolerance Test.................................................................. 292 Figure 160 – Receiver Jitter and CM Tolerance Test – Setting RJ Level (Gen3i) ...................... 293 Serial ATA Revision 3.0 Gold Revision page 15 of 663 Figure 161 – Receiver Jitter and CM Tolerance Test – Setting TJ and CM Levels (Gen3i) ....... 294 Figure 162 – Receiver Jitter and CM Tolerance Test (Gen3i) .................................................... 294 Figure 163 – Return Loss Test-Calibration ................................................................................. 295 Figure 164 – Return Loss Test .................................................................................................... 297 Figure 165 – Intra-Pair Skew Test for a Transmitter ................................................................... 299 Figure 166 – Receiver Intra-Pair Skew Test—Setting Levels ..................................................... 299 Figure 167 – Receiver Intra-Pair Skew Test ............................................................................... 299 Figure 168 – Example Intra-Pair Skew test for Transmitter (10.8 pS) ........................................ 300 Figure 169 – TX/RX Sequencing Transient Voltage Measurement ............................................ 300 Figure 170 – AC Coupled Capacitance Measurement................................................................ 301 Figure 171 – Squelch Detector Threshold Test—Setting Levels ................................................ 303 Figure 172 – Squelch Detector Threshold Test........................................................................... 304 Figure 173 – TDR Differential Impedance Test—Setting Risetime............................................. 306 Figure 174 – TDR Impedance Test ............................................................................................. 306 Figure 175 – TDR Single-Ended Impedance Test—Setting Risetime ........................................ 307 Figure 176 – DC Coupled Common Mode Voltage Measurement.............................................. 307 Figure 177 – AC Coupled Common Mode Voltage Measurement.............................................. 308 Figure 178 – TDR Impedance Test ............................................................................................. 308 Figure 179 - Sequencing Transient Voltage Laboratory Load .................................................... 309 Figure 180 – OOB Signals........................................................................................................... 310 Figure 181 – Transmitter Examples ............................................................................................ 311 Figure 182 – Transmitter Examples (Concluded)........................................................................ 312 Figure 183 – COMRESET Sequence.......................................................................................... 313 Figure 184 – COMINIT Sequence ............................................................................................... 314 Figure 185 – OOB Signal Detector.............................................................................................. 316 Figure 186 – Squelch Detector.................................................................................................... 317 Figure 187 – Power-On Sequence .............................................................................................. 330 Figure 188 – PHYRDY to Partial—Host Initiated ........................................................................ 332 Figure 189 – PHYRDY to Partial—Device Initiated..................................................................... 333 Figure 190 – Nomenclature Reference ....................................................................................... 336 Figure 191 – Bit Ordering and Significance................................................................................. 346 Figure 192 – Transmission Structures ........................................................................................ 348 Figure 193 – FIS type value assignments ................................................................................... 383 Figure 194 – Register - Host to Device FIS layout ...................................................................... 384 Figure 195 – Register - Device to Host FIS layout ...................................................................... 386 Figure 196 – Set Device Bits - Device to Host FIS layout ........................................................... 387 Figure 197 – DMA Activate - Device to Host FIS layout.............................................................. 388 Figure 198 – DMA Setup – Device to Host or Host to Device FIS layout ................................... 389 Figure 199 – BIST Activate - Bidirectional................................................................................... 392 Figure 200 – PIO Setup - Device to Host FIS layout................................................................... 395 Figure 201 – Data – Host to Device or Device to Host FIS layout .............................................. 397 Figure 202 –DEVICE CONFIGURATION IDENTIFY data structure ........................................... 494 Figure 203 - DEVICE CONFIGURATION SET data structure .................................................... 495 Figure 204 – DMA Setup FIS definition for memory buffer selection .......................................... 501 Figure 205 – READ FPDMA QUEUED command definition ....................................................... 504 Figure 206 – READ FPDMA QUEUED error on command receipt............................................. 506 Figure 207 - Set Device Bits FIS with error notification, and command completions ................. 507 Figure 208 - Set Device Bits FIS aborting all outstanding command.......................................... 508 Figure 209 – WRITE FPDMA QUEUED command definition ..................................................... 509 Figure 210 - Set Device Bits FIS for successful WRITE FPDMA QUEUED command completion ............................................................................................................................................. 510 Figure 211 – WRITE FPDMA QUEUED error on command receipt ........................................... 511 Figure 212 - Set Device Bits FIS with error notification, and command completions ................. 512 Figure 213 - NCQ QUEUE MANAGEMENT - Command definition ........................................... 513 Figure 214 – NCQ QUEUE MANAGEMENT, Abort NCQ Queue - Successful completion........ 515 Figure 215 – NCQ QUEUE MANAGEMENT, Abort NCQ Queue - error on command receipt .. 516 Serial ATA Revision 3.0 Gold Revision page 16 of 663 Figure 216 - NCQ QUEUE MANAGEMENT, Abort NCQ Queue – error during execution......... 517 Figure 217 – NCQ QUEUE MANAGEMENT, Deadline Handling - Successful completion........ 520 Figure 218 – NCQ QUEUE MANAGEMENT, Deadline Handling - error on command receipt .. 520 Figure 219 - NCQ QUEUE MANAGEMENT, Deadline Handling – error during execution......... 521 Figure 220 – Example DMA engine indirection for First-party DMA support .............................. 522 Figure 221 – Queued Error Log data structure definition ............................................................ 525 Figure 222 – NCQ Queue Management Log (12h) data structure definition .............................. 527 Figure 223 – Phy Event Counter Identifiers ................................................................................ 530 Figure 224 – Phy Event Counters Log data structure definition.................................................. 532 Figure 225 – Generic enclosure services topology ..................................................................... 537 Figure 226 – Simplified view of generic topology ........................................................................ 537 Figure 227 – Enclosure services definition configuration............................................................ 538 Figure 228 – Register Signature Indicating Presence of Enclosure Services Device................. 539 Figure 229 – Register Signature for Absent Enclosure Processor.............................................. 539 Figure 230 – Command Block Register Fields Used in Enclosure Processor Communications 540 Figure 231 – I2C Frame for Conveying an Enclosure Services Command ................................. 541 Figure 232 – WRITE SEP Command Block Registers................................................................ 542 Figure 233 – I2C Transactions Corresponding to a WRITE SEP Command .............................. 543 Figure 234 – READ SEP Command Block Registers ................................................................. 544 Figure 235 – I2C Transactions Corresponding to READ SEP Command ................................... 544 Figure 236 – IDENTIFY SEP data structure definition ................................................................ 545 Figure 237 – SAF-TE Write Device Slot Status data structure ................................................... 547 Figure 238 – SES Device Element data structure....................................................................... 548 Figure 239 – Example Subsystem............................................................................................... 549 Figure 240 – SAF-TE Device ID field convention........................................................................ 549 Figure 241 – SES Slot Address field convention......................................................................... 550 Figure 242 – Activity LED definition for desktop behavior emulation .......................................... 552 Figure 243 – Device Activity LEDs with Separate Wires............................................................. 553 Figure 244 – Device Activity LEDs with Ribbon Cable................................................................ 554 Figure 245 – Device Activity LEDs in a Storage Subsystem....................................................... 555 Figure 246 – Software reset to control port result values............................................................ 556 Figure 247 – Port Multiplier Signature ......................................................................................... 558 Figure 248 – SActive register definition....................................................................................... 565 Figure 249 – SNotification register definition............................................................................... 565 Figure 250 – Error handling architecture..................................................................................... 567 Figure 251 – Port Multiplier Overview ......................................................................................... 577 Figure 252 – Port Selector Overview........................................................................................... 607 Figure 253 – Example Failover Application with Two Hosts ....................................................... 608 Figure 254 – Port selection signal based on assertion of COMRESET to assertion of following COMRESET ........................................................................................................................ 610 Figure 255 – Complete port selection signal consisting of two sequences with requisite inter-reset spacings............................................................................................................................... 611 Figure 256 – Control State Machine............................................................................................ 613 Figure 257 – Phy Block Diagram................................................................................................. 614 Figure 258 – Concept summary interconnect structure .............................................................. 644 Figure 259 – An example of signal connections with one I/O Controller..................................... 645 Figure 260 – Example of signal connections with two I/O Modules ............................................ 647 Figure 261 – High Speed Channels – Configuration 0................................................................ 648 Figure 262 – High-Speed Channels – Configuration 1 ............................................................... 648 Figure 263 – Low Speed Channels ............................................................................................. 649 Figure 264 – Interconnect Channels ........................................................................................... 649 Figure 265 – I/O Controller Module Connector Rendering.......................................................... 650 Figure 266 – Connector Pin Layout and Pin Lengths.................................................................. 651 Figure 267 – I/O Controller Module Connector Receptacle Engineering Drawing...................... 652 Figure 268 – Side View of Connector.......................................................................................... 652 Figure 269 – I/O Controller Module Connector Locations on 1xWide I/O module ...................... 654 Serial ATA Revision 3.0 Gold Revision page 17 of 663 Figure 270 – I/O Controller Module Connector Locations on 2xWide I/O Module ...................... 655 Figure 271 – Jitter Deviations...................................................................................................... 662 Figure 272 – Edge to Edge Timing.............................................................................................. 663 Serial ATA Revision 3.0 Gold Revision page 18 of 663 LIST OF TABLES Table 1 – State Table Cell Description .......................................................................................... 44 Table 2 – Usage Model Descriptions............................................................................................. 50 Table 3 – Signal and Power SATA Plug and Nominal Mate Sequence ........................................ 82 Table 4 – Allowed values for dimension A and B for device-to-backplane mating ....................... 91 Table 5 – Housing and contact electrical parameters, test procedures, and requirements .......... 95 Table 6 – Mechanical test procedures and requirements ............................................................. 96 Table 7 – Environmental parameters, test procedures, and requirements ................................... 97 Table 8 – Additional requirement................................................................................................... 97 Table 9 – Connector test sequences............................................................................................. 98 Table 10 – Signal and Power Internal Micro SATA Plug and Nominal Mate Sequence ............. 119 Table 11 – Unique Connector Mechanical Testing Procedures and Requirements ................... 119 Table 12 – Slimline Connector Location References .................................................................. 122 Table 13 – Slimline Device plug connector pin definition ............................................................ 131 Table 14 – Slimline Connector Mechanical Test Procedures And Requirements ...................... 138 Table 15 - Signal and Power Internal LIF-SATA Plug ................................................................. 145 Table 16 - Unique Connector Mechanical Testing Procedures and Requirements .................... 146 Table 17 – Multilane Pin Assignments ........................................................................................ 161 Table 18 – Internal Cable / Connector Measurement Parameter and Requirements................. 165 Table 19 – External Single Lane Cable / Connector Measurement Parameter and Requirements ............................................................................................................................................. 165 Table 20 – Limited External Multilane Cable / Connector Measurement Parameter and Requirements ...................................................................................................................... 166 Table 21 – Extended External Multilane Cable / Connector Measurement Parameter and Requirements ...................................................................................................................... 166 Table 22 – Common Interconnect Measurement Procedure Methodologies.............................. 169 Table 23 – Interconnect Test Methodologies / Procedures......................................................... 170 Table 24 – Power segment pin P11 activity signal electrical parameters ................................... 176 Table 25 – Host activity signal electrical parameters .................................................................. 176 Table 26 – Activity signal functional states.................................................................................. 177 Table 27 – Host staggered spin-up control electrical requirements ............................................ 178 Table 28 – Comparator voltages for alternate example presence detection circuit .................... 181 Table 29 – General Specifications............................................................................................... 193 Table 30 – Transmitter Specifications ......................................................................................... 195 Table 31 – Transmitted Signal Requirements ............................................................................. 198 Table 32 – Receiver Specifications ............................................................................................. 202 Table 33 – Lab-Sourced Signal (for Receiver Tolerance Testing) .............................................. 206 Table 34 – OOB Specifications ................................................................................................... 209 Table 35 – Low Transition Density Pattern (LTDP) Starting with RD- ........................................ 233 Table 36 – Low Transition Density Pattern (LTDP) starting with RD+ ........................................ 234 Table 37 – High Transition Density Pattern (HTDP) Starting with RD– ...................................... 235 Table 38 – High Transition Density Pattern (HTDP) Starting with RD+ ...................................... 236 Table 39 – Low Frequency Spectral Content Pattern (LFSCP) Starting with RD– ..................... 237 Table 40 – Low Frequency Spectral Content Pattern (LFSCP) Starting with RD+ ..................... 238 Table 41 – Simultaneous Switching Outputs Pattern (SSOP) Starting with RD– ....................... 239 Table 42 – Simultaneous Switching Outputs Pattern (SSOP) Starting with RD+ ....................... 239 Table 43 – Lone-Bit Pattern (LBP) Starting with RD– ................................................................. 240 Table 44 – Lone-Bit Pattern (LBP) Starting with RD+ ................................................................. 240 Table 45 – Composite-Bit Pattern (COMP) Starting with RD– .................................................... 241 Table 46 – Composite-Bit Pattern (COMP) Starting with RD+.................................................... 244 Table 47 – Frame Error Rate Confidence Levels Versus Sample Size ...................................... 262 Table 48 – Bit Error Rate Confidence Levels Versus Sample Size ............................................ 264 Table 49 – OOB Signal Times..................................................................................................... 310 Table 50 – Interface Power States .............................................................................................. 319 Serial ATA Revision 3.0 Gold Revision page 19 of 663 Table 51 – State Diagram Host Phy Initialization State Machine................................................ 321 Table 52 – State Diagram Device Phy Initialization State Machine ............................................ 325 Table 53 – Bit Designations......................................................................................................... 336 Table 54 – Conversion Examples................................................................................................ 337 Table 55 – 5B/6B Coding ............................................................................................................ 339 Table 56 – 3B/4B Coding ............................................................................................................ 339 Table 57 – Encoding Examples................................................................................................... 340 Table 58 – Valid Data Characters ............................................................................................... 341 Table 59 – Valid Control Characters ........................................................................................... 345 Table 60 – Single Bit Error with Two Character Delay ................................................................ 347 Table 61 – Single Bit Error with One Character Delay ................................................................ 347 Table 62 – Description of Primitives ............................................................................................ 349 Table 63 – Primitive Encoding..................................................................................................... 350 Table 64 – CONTP Usage Example ............................................................................................ 352 Table 65 – Example of Components of a Round Trip Delay....................................................... 355 Table 66 – SRST Write from Host to Device Transmission Breaking Through a Device to Host Data FIS............................................................................................................................... 356 Table 67 – Command Shadow Register Block Register Transmission Example ....................... 356 Table 68 – Data from Host to Device Transmission Example..................................................... 357 Table 69 – State Diagram Link Idle ............................................................................................. 360 Table 70 – State Diagram Link Transmit..................................................................................... 363 Table 71 – State Diagram Link Receive ...................................................................................... 370 Table 72 – State Diagram Link Power Mode............................................................................... 376 Table 73 – Simplified Shadow Register Block register numbering ............................................. 382 Table 74 – BIST Activate FIS Modes and Bit Settings ................................................................ 393 Table 75 – IDENTIFY DEVICE information ................................................................................. 479 Table 76 - Coded Values for Negotiated Serial ATA Signaling Speed ....................................... 484 Table 77 – IDENTIFY PACKET DEVICE information ................................................................. 487 Table 78 - Features enable/disable values ................................................................................. 492 Table 79 - Feature identification values ...................................................................................... 492 Table 80 - Subcommand Field .................................................................................................... 513 Table 81 - Abort Type .................................................................................................................. 515 Table 82- Log Addresses for Serial ATA ..................................................................................... 523 Table 83 - General Purpose Log directory values for Serial ATA ............................................... 524 Table 84 – SCR definition............................................................................................................ 560 Table 85 – SCR Definition ........................................................................................................... 560 Table 86 – State Diagram Collisions ........................................................................................... 581 Table 87 – State Diagram Hot Plug State Machine for Host Port ............................................... 583 Table 88 – State Diagram Hot Plug State Machine for Device Port............................................ 585 Table 89 – Register Values for an Unsupported Command ....................................................... 588 Table 90 – Static Information Registers ...................................................................................... 590 Table 91 – Status Information and Control Registers ................................................................. 592 Table 92 – Features Supported Registers .................................................................................. 596 Table 93 – Features Enabled Registers ...................................................................................... 597 Table 94 – Vendor Unique Registers .......................................................................................... 598 Table 95 – Phy Event Counter Registers .................................................................................... 599 Table 96 – Reserved Registers ................................................................................................... 599 Table 97 – PSCR Definition......................................................................................................... 600 Table 98 – READ PORT MULTIPLIER Command Definition ..................................................... 600 Table 99 – READ PORT MULTIPLIER Success Status Result Values ...................................... 601 Table 100 – READ PORT MULTIPLIER Error Status Result Values.......................................... 602 Table 101 – WRITE PORT MULTIPLIER Command Definition.................................................. 602 Table 102 – WRITE PORT MULTIPLIER Success Status Result Values .................................. 603 Table 103 – WRITE PORT MULTIPLIER Error Status Result Values ........................................ 604 Table 104 – Port selection signal inter-reset timing requirements .............................................. 610 Table 105 – CRC and scrambler calculation example - PIO Write Command ........................... 630 Serial ATA Revision 3.0 Gold Revision page 20 of 663 Table 106 – J1, J2, J3 Pin Assignments ..................................................................................... 656 Table 107 – J4, J5, J6 Pin Assignments ..................................................................................... 656 Serial ATA Revision 3.0 Gold Revision page 21 of 663 1 Revision History 1.1 Revision 2.5 (Ratification Date October 27, 2005) Release that integrates and consolidates the following previously published specifications including all erratum against those specifications: • Serial ATA revision 1.0a • Serial ATA II: Extensions to Serial ATA 1.0a revision 1.2 • Serial ATA II: Electrical Specification revision 1.0 • Serial ATA II: Cable and Connectors Volume 1 revision 1.0 • Serial ATA II: Cable and Connectors Volume 2 revision 1.0 • Serial ATA II: Port Multiplier revision 1.2 • Serial ATA II: Port Selector revision 1.0 1.2 Revision 2.6 (Ratification Date February 15, 2007) Release that incorporates errata against Revision 2.5 and the following new features and enhancements: • Internal Slimline cable and connector • Internal Micro SATA connector for 1.8” HDD • Mini SATA Internal Multilane cable and connector • Mini SATA External Multilane cable and connector • NCQ Priority • NCQ Unload • Enhancements to the BIST Activate FIS • Enhancements for robust reception of the Signature FIS 1.3 Revision 3.0 (Ratification Date: June 2, 2009) Release that incorporates errata against Revision 2.6: • ECN001 - Slimline Bump Correction • ECN002 - Bump Correction • ECN003 - State Name Corrections • ECN004 - ATA Log & Subcode reservations • ECN006 - fbaud/10 Jitter Parameter Removal • ECN008 - fbaud/500 Jitter Parameter Clarification • ECN009 - Correcting LBP references in the COMP data pattern and other locations • ECN010 - Power State Resume Speed • ECN011 - Data validity clarifications • ECN012 - Cable & Connector Retention • ECN013 - Section 13 Corrections • ECN014 - PACKET State Names • ECN016 - Long Term Frequency Accuracy and SSC Profile Tests for Transmitters • ECN017 - OOB Burst/Gap Duration Clarification • ECN018 - Figure 69 Pin Location Correction • ECN019 - Cable ISI Test Source Risetime • ECN021 - External plug height • ECN022 - Editorial cleanup – 8KB, IDENTIFY DEVICE • ECN023 - L-Key Opening Correction (Slimline Host Receptacle Connector) • ECN024 - Contact Current Rating procedure • ECN025 - Rise Time Measurements Serial ATA Revision 3.0 Gold Revision page 23 of 663 • ECN026 - Gen 3i TX TJ Measurement Location • ECN027 - Gen3i Rx Differential Return Loss Text Description and Figure Change - Clarification Only • ECN028 - Clarification of Test Patterns for Measurement Defined in 7.2 Electrical Specification • ECN029 - Addition of Pattern to the TX AC Common Mode Voltage (Gen3i) Measurement • ECN031 - Correction to ECN 004 • ECN032 - Correction to TX AC Common Mode Voltage Table Value 'Units' • ECN033 - Definition of Terms • ECN034 - Corrections to Technical Proposal 005 • ECN035 - Clarification of Words 76 to 79 • ECN036 - LIF-SATA Clarifications • ECN037 - Changes made by Technical Integration Work Group • ECN038 - Key clarification and the following new features and enhancements • TP002 - Gen3 register assignments • TP004 - NCQ Clarifications • TP005 - SATA Speed Indicator in ID String • TP007 - Automatic Partial to Slumber Transitions • TP009 - LIF Connector for 1.8” HDD for SATA Revision 2.6 • TP010 - Serial ATA NCQ Streaming Command • TP011 - Serial ATA NCQ QUEUE MANAGEMENT Command • TP012 - Gen 1 Clock to Data Jitter Definition • TP013 - Connector for 7 mm slimline drives • TP014 - Allow READ LOG DMA EXT to Clear NCQ Error • TP015 - Remove Device Register from Signature • TP016 - Add Write-Read-Verify to SSP support • TP017 - Align SATA 2.6 with ATA8-ACS • TP018 - Specification Revisions For Gen3i Serial ATA Revision 3.0 Gold Revision page 24 of 663 2 Scope This specification defines a high-speed serialized ATA data link interface (specifying Phy, Link, Transport, and Application layers). The serialized interface uses the command set from the ATA8-ACS standard, augmented with Native Command Queuing commands optimized for the serialized interface. The serialized ATA interface is defined in a register-compatible manner with parallel ATA to enable backward compatibility with parallel ATA drivers. The physical interface is defined to ease integration (low pin count, low voltages) and enable scalable performance (with currently defined data rates of 1.5 Gbps, 3.0 Gbps and 6.0 Gbps). Complementary components are also specified including interconnect solutions for various applications, port expansion devices, and failover devices. Normative information is provided to allow interoperability of components designed to this specification. Informative information, when provided, may illustrate possible design implementation. Serial ATA Revision 3.0 Gold Revision page 25 of 663 3 Normative references The following standards contain provisions that, through reference in the text, constitute provisions of this standard. At the time of publication, the editions indicated were valid. All standards are subject to revision, and parties to agreements based on this standard are encouraged to investigate the possibility of applying the most recent editions of the standards listed below. Copies of the following documents may be obtained from ANSI: Approved ANSI standards, approved and draft international and regional standards (ISO, IEC, CEN/CENELEC, ITUT), and approved and draft foreign standards (including BSI, JIS, and DIN). For further information, contact ANSI Customer Service Department at 212-642-4900 (phone), 212-302-1286 (fax) or via the World Wide Web at http://www.ansi.org. Additional availability contact information is provided below as needed. 3.1 Approved references The following approved ANSI standards, approved international and regional standards (ISO, IEC, CEN/CENELEC, ITUT), may be obtained from the international and regional organizations who control them. AT Attachment with Packet Interface – 5 (ATA/ATAPI-5) [ANSI INCITS 340-2000] AT Attachment with Packet Interface – 6 (ATA/ATAPI-6) [ANSI INCITS 361-2002] ATA/ATAPI-8 Command Set (ATA8-ACS) [ANSI INCITS 452-2008] Serial Attached SCSI – 1.1 (SAS-1.1) [ANSI INCITS 417-2006] SCSI-3 Enclosure Services (SES) Command Set [ANSI INCITS 305-1998] SCSI-3 Enclosure Services (SES) Amendment 1 [ANSI INCITS 305-1998/AM1-2000] SCSI Enclosure Services - 2 (SES-2) [ANSI INCITS T10/1559-D] ATA/ATAPI Host Adapters Standard [ANSI INCITS 370-2004] ASME Y14.5M Dimensioning and Tolerancing To obtain copies of these documents, contact Global Engineering or INCITS. Global Engineering Documents, an IHS Company 15 Inverness Way East Englewood, CO 80112-5704 USA Web site: http://global.ihs.com Telephone: (303) 397-7956 or (303) 792-2181 or (800) 854-7179 Document Distribution INCITS Online Store managed by Techstreet 1327 Jones Drive Ann Arbor, MI 48105 USA Serial ATA Revision 3.0 Gold Revision page 27 of 663 Web site: http://www.techstreet.com/incits.html Telephone: (734) 302-7801 or (800) 699-9277 Additional material and draft versions available from http://www.T10.org and http://www.T13.org. SAF-TE – SCSI Accessed Fault-Tolerant Enclosure version 1.00 [revision R041497, April 14, 1997]. Available for download at http://www.intel.com/design/servers/ipmi/pdf/sr041497.pdf. I2C-Bus Specification version 2.1. Available from Philips Semiconductors at http://www.semiconductor.philips.com/buses/i2c. IPMB - Intelligent Platform Management Bus Communications Protocol Specification version 1.0. Available for download at http://www.intel.com/design/servers/ipmi/spec.htm. IPMI - Intelligent Platform Management Interface Specification version 1.5. Available for download at http://www.intel.com/design/servers/ipmi/spec.htm. JEDEC Standards (Located on http://www.jedec.com). • JESD22-A114-B, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) • JESD22-C101-A, Field-Induced Charged-Device Model Test Method for ElectrostaticDischarge-Withstand Thresholds of Microelectronic Components” The following standards published by the SFF Committee are referenced. These standards are available for download through http://www.sffcommittee.org. • SFF-8086, Compact Multilane Series: Common Elements • SFF-8087, Compact Multilane Series: Unshielded • SFF-8088, Compact Multilane Series: Shielded • SFF-8111, 1.8” drive form factor (60x70 mm) • SFF-8144, 54 mm x 71 mm Form Factor w/micro SATA Connector • SFF-8201, Form Factor of 2.5” Disk Drives • SFF-8301, Form Factor of 3.5” Disk Drives • SFF-8470, Shielded High Speed Serial Multilane Copper Connector • SFF-8484, Multilane Internal Serial Attachment Connector • SFF-8553, Form Factor of 5 1/4" 7 mm Height Optical Drives with SATA Interface The following EIA-364-xx standards published by EIA are referenced. To obtain copies of these documents, contact Global Engineering. • EIA-364-09, Durability Test Procedure for Electrical Connectors and Contacts • EIA-364-13, Mating and Unmating Forces Test Procedure for Electrical Connectors • EIA-364-17, Temperature Life with or without Electrical Load Test Procedure for Electrical Connectors and Sockets • EIA-364-18, Visual and Dimensional Inspection for Electrical Connector • EIA-364-20, Withstanding Voltage Test Procedure for Electrical Connectors, Sockets and Coaxial Contacts • EIA-364-21, Insulation Resistance Test Procedure for Electrical Connectors, Sockets, and Coaxial Contacts • EIA-364-23, Low Level Contact Resistance Test Procedure for Electrical Connectors and Sockets • EIA-364-27, Mechanical Shock (Specified Pulse) Test Procedure for Electrical Connectors • EIA-364-28, Vibration Test Procedure for Electrical Connectors and Sockets • EIA-364-31, Humidity Test Procedure for Electrical Connectors and Sockets • EIA-364-32, Thermal Shock (Temperature Cycling) Test Procedure for Electrical Connectors and Sockets Serial ATA Revision 3.0 Gold Revision page 28 of 663 • EIA-364-38, Cable Pull-Out Test Procedure for Electrical Connectors • EIA-364-41, Cable Flexing Test Procedure for Electrical Connectors • EIA-364-65, Mixed Flowing Gas Many of the EIA-364-xx specifications are available for download from: http://www.ecaus.org/engineering/Downloads/eia364.htm The following form factor standards published by EIA are referenced. These standards may be obtained from Global Engineering. • EIA-740, specification for small form factor 3.5” disk drives • EIA-720, specification for small form factor 2.5” disk drives 3.2 References under development The following ANSI standards under development are referenced. Draft versions of these standards are available from http://www.T10.org or http://www.T13.org. ATA/ATAPI-8 Serial Transport (ATA8-AST) [ANSI INCITS T13/1697-D] ATA/ATAPI-8 Parallel Transport (ATA8-APT) [ANSI INCITS T13/1698-D] ATA Host Adapter Standards - 2 (HBA-2) [ANSI INCITS T13/2014D] 3.3 Other references The 8b/10b code used in Serial ATA is based on the following published references: [1] A.X. Widmer and P.A. Franaszek, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code.” IBM Journal of Research and Development, 27, no. 5: 440-451 (September, 1983) [2] U.S. Patent 4,486,739. Peter A. Franaszek and Albert X. Widmer. Byte Oriented DC Balanced (0,4) 8B/10B Partitioned Block Transmission Code. (Dec. 4, 1984) Serial ATA Revision 3.0 Gold Revision page 29 of 663 4 Definitions, abbreviations, and conventions 4.1 Definitions and abbreviations 4.1.1 Active Port The active port is the currently selected host port on a Port Selector. 4.1.2 ATA (AT Attachment) ATA defines the physical, electrical, transport, and command protocols for the attachment of storage devices. 4.1.3 ATAPI (AT Attachment Packet Interface) device A device implementing the Packet Command feature set. 4.1.4 BER (bit error rate) 4.1.5 bitrate Reciprocal of the unit interval. Bitrate = 1 / UI. 4.1.6 bit synchronization The state in which a receiver has synchronized the internal receiver clock to the external transmitter and is delivering retimed serial data. 4.1.7 burst A short pulse of data starting from and ending with the idle condition on the interface. These are used for OOB signaling. 4.1.8 byte A byte is an ordered set of eight (8) bits. The least significant bit is bit 0 and the most significant bit is bit 7. 4.1.9 character A character is a representation of a byte in the Zxx.y notation (see 9.2.1). 4.1.10 character alignment Character alignment is a receiver action that resets the character boundary to that of the comma sequence found in the K28.5 control character of ALIGNP, and establishes Dword synchronization of the incoming serial data stream. 4.1.11 character slipping Character slipping is the receiver action that realigns the receiver’s clock to the received bit stream by adding or removing bit times within the characters of ALIGNP. Serial ATA Revision 3.0 Gold Revision page 31 of 663 4.1.12 ClickConnect An optional positive latch solution for internal single lane interconnects (see section 6.1.4). 4.1.13 CLTF (Closed Loop Transfer Function) For a feedback system, the CLTF is the ratio of the magnitude and phase of the output variable to the magnitude and phase of the input variable, as a function of frequency for sinusoidal excitation. This term is used in the Reference Clock sections of this specification. 4.1.14 code violation A code violation is an error that occurs in the reception process as a result of (1) a running disparity violation or (2) an encoded character that does not translate to a valid data or control character or (3) an encoded character that translates to a control character other than K28.5 or K28.3 in byte 0 of a Dword or (4) an encoded character that translates to any control character (valid or invalid) in bytes 1-3 of a Dword. 4.1.15 comma character A comma character is a control character, that when encoded, contains the comma sequence. In Serial ATA the only comma character used is K28.5, and only ALIGNP contains the comma character. The comma sequence is the first seven bits of the encoded character. 4.1.16 comma sequence The comma sequence is a seven-bit sequence of 0011111 or 1100000 in an encoded stream. The comma sequence is unique in that it appears only in a single encoded character, and furthermore, may not appear in any subset of bits in adjacent encoded characters. This unique property allows the comma sequence to be used for determining alignment of the received data stream. 4.1.17 command aborted Command aborted is command completion with ABRT bit set to one in the Error register, and ERR bit set to one in the Status register. 4.1.18 command completion Command completion describes the completion of an action requested by command, applicable to the device. Command completion also applies to the case where the command has terminated with an error, and the following actions occurred: a) the appropriate bits of the Status Register have been updated b) BSY & DRQ bits have been cleared to zero c) assertion of INTRQ (if nIEN is active-low), assuming that the command protocol specifies INTRQ to be asserted In Serial ATA, the register contents are transferred to the host using a Register - Device-to-Host FIS. 4.1.19 command packet A data structure transmitted to the device during the execution of a PACKET command that includes the command and command parameters. Serial ATA Revision 3.0 Gold Revision page 32 of 663 4.1.20 concentrator 集中器 A concentrator is a generic term used to describe a logical block that has multiple Serial ATA ports to connect to Serial ATA devices plus some small number of ports to connect to a host. In the simplest case a concentrator may be a host bus adapter (HBA) that is plugged into the host that connects to some number of Serial ATA devices (like a PCI Serial ATA controller card). A concentrator may also be an internal or external RAID controller such as a fibre-channel to Serial ATA RAID controller, or may be some element that expands the number of ports through a fanout scheme, like a Port Multiplier. 4.1.21 Control Block registers Control Block registers are interface registers used for device control and to post alternate status. 4.1.22 control character A control character is a character in which Z is equal to K (See 9.2.1). 4.1.23 control port The Port Multiplier has one port address reserved for control and status communication with the Port Multiplier itself. The control port has port address Fh. 4.1.24 control variable The control variable, Z, is a flag that determines the code set to be used to interpret a data byte. The control variable has the value D (for data characters) or K (for control characters). 4.1.25 CRC (Cyclic Redundancy Check) An error checking mechanism that checks data integrity by computing a polynomial algorithm based checksum. In Serial ATA a 32-bit CRC is calculated over the contents of a Frame Information Structure. The Serial ATA CRC is the Dword in a frame that immediately precedes EOFP. 4.1.26 data character A data character is a character in which Z is equal to D (See 9.2.1). 4.1.27 data signal source An instrument which provides a Serial ATA data signal. 4.1.28 device Device is a storage peripheral. Traditionally, a device on the interface has been a hard disk drive, but any form of storage device may be placed on the interface provided the device adheres to this specification and to an ATA standard. 4.1.29 device port The device port is a port on a Port Multiplier or a Port Selector that is connected to the device. Port Multipliers may have up to 15 device ports. Port Selectors have one device port. 4.1.30 DCB (DC block) The DC block is defined as a device that passes frequencies from 10 MHz to at least 12 GHz with minimal effect on the amplitude or phase of the signal. Serial ATA Revision 3.0 Gold Revision page 33 of 663 4.1.31 differential signal The differential signal is the voltage on the positive conductor minus the voltage on the negative conductor (i.e. TX+ – TX-). 4.1.32 DJ (deterministic jitter – peak to peak) All jitter sources that have bounded probability distribution functions (i.e. values outside the bounds have probability zero). Four kinds of deterministic jitter are identified: duty cycle distortion, data dependent (ISI), sinusoidal, and uncorrelated (to the data) bounded. DJ is characterized by its bounded, peak-to-peak value. 4.1.33 DMA (direct memory access) DMA is a means of data transfer between device and host memory without host processor intervention. 干预 4.1.34 Dword A Dword is an ordered set of thirty-two (32) bits. The least significant bit is bit 0 and the most significant bit is bit 31. 4.1.35 Dword synchronization The state in which a receiver has recognized the comma sequence and is producing an aligned data stream of Dwords (four contiguous bytes) from the zero-reference of the comma character. 4.1.36 EMI (Electromagnetic Interference) 4.1.37 encoded character An encoded character is the output of the 8b/10b encoder – the result of encoding a character. An encoded character consists of 10 bits, where bit 0 is the most significant bit and bit 9 is the least significant. The bits in an encoded character are symbolically referred to as “abcdeifghj” where “a” corresponds to bit 0 and “j” corresponds to bit 9. Case is significant. Note the out-oforder representation. See section 9.2 for a description of the relationship between bytes, characters and encoded characters. 4.1.38 endpoint device An endpoint device is an ATA or ATAPI device, as reported by the device signature after poweron or reset. This may include hard disk drives, optical disk drives, and tape drives. 4.1.39 elasticity buffer The elasticity buffer is a portion of the receiver where character slipping and/or character alignment is performed. 4.1.40 eSATA The System to System Interconnects - External Desktop Applications usage model (see section 5.2.6). Serial ATA Revision 3.0 Gold Revision page 34 of 663 4.1.41 Fbaud The nominal rate of data through the channel, measured in GHz. 4.1.42 FER (frame error rate) Refer to section 7.2.2.1.2. 4.1.43 First-party DMA Data Phase The First-party DMA Data Phase is the period from the reception of a DMA Setup FIS until either the exhaustion of the associated data transfer count or the assertion of the ERR bit in the shadow Status register. 4.1.44 First-party DMA access First-party DMA access is a method by which a device accesses host memory. 4.1.45 FIS (Frame Information Structure) The user payload of a frame, does not include the SOFP, CRC, and EOFP delimiters. 4.1.46 frame A frame is an indivisible unit of information exchanged between a host and device. A frame consists of SOFP, a Frame Information Structure, a CRC calculated over the contents of the FIS, and EOFP. 4.1.47 Gen1 Refers to first generation signaling characterized by a speed of 1.5 Gbps. Refer to section 7.1. 4.1.48 Gen1i The internal electrical specifications at 1.5 Gbps with cable lengths up to 1 meter. 4.1.49 Gen1m The electrical specifications used in Short Backplane Applications, External Desktop Applications, and Data Center Applications with cable lengths up to two meters, defined at 1.5 Gbps. 4.1.50 Gen1x The electrical specifications used in Long Backplane Applications and Data Center Applications supporting cable lengths up to and greater than two meters, defined at 1.5 Gbps. 4.1.51 Gen2 Refers to second generation signaling characterized by a speed of 3.0 Gbps. Refer to section 7.1. 4.1.52 Gen2i The internal electrical specifications at 3.0 Gbps with cable lengths up to 1 meter. 4.1.53 Gen2m The electrical specifications used in Short Backplane Applications, External Desktop Applications, and Data Center Applications with cable lengths up to two meters, defined at 3.0 Gbps. Serial ATA Revision 3.0 Gold Revision page 35 of 663 4.1.54 Gen2x The electrical specifications used in Long Backplane Applications and Data Center Applications supporting cable lengths up to and greater than two meters, defined at 3.0 Gbps. 4.1.55 Gen3 Refers to third generation signaling characterized by a speed of 6.0 Gbps. 4.1.56 Gen3i The internal electrical specifications at 6.0 Gbps with cable lengths up to 1 meter. 4.1.57 HBA (Host Bus Adapter) HBA is a component that connects to the host system’s expansion bus to provide connectivity for devices. HBAs are also often referred to as controller cards or merely controllers. 4.1.58 HBWS (High Bandwidth Scope) An oscilloscope with an analog bandwidth of 10 GHz or greater in the measurement path. 4.1.58.1 Gen1/Gen2 Requirement For Gen1/Gen2 measurements, an oscilloscope with an analog bandwidth of 10 GHz or greater shall be used in the measurement path. 4.1.58.2 Gen3 Requirement For Gen3 measurements, an oscilloscope with an analog bandwidth of 12 GHz or greater shall be used in the measurement path. 4.1.59 HFTP (High Frequency Test Pattern) This pattern provides the maximum frequency allowed within the Serial ATA encoding rules. Pattern: 1010101010 1010101010b = encoded D10.2. The pattern is repetitive. 4.1.60 hot plug The connection of a SATA device to a host system that is already powered. The SATA device is already powered or powered upon insertion/connection. See section 7.2.5.1 for details on hot plug scenarios. 4.1.61 host port The host port is the port that is used to connect the Port Multiplier or Port Selector to a host. Port Multipliers have one host port. Port Selectors have two host ports. 4.1.62 inactive port The inactive port is the host port that is not currently selected on the Port Selector. 4.1.63 interrupt pending Interrupt pending is an internal state of the device that exists when the device protocol requires the device to notify the host of an event by asserting INTRQ, given the condition where nIEN is asserted active-low to zero. Serial ATA Revision 3.0 Gold Revision page 36 of 663 4.1.64 immediate NCQ command An immediate NCQ command is a NCQ command that shall be processed: a) After any command previously accepted by the device for which the device has transmitted a DMA Setup FIS and has not reached command completion; and b) Before any NCQ command previously accepted by the device for which the device has not transmitted a DMA Setup FIS. 4.1.65 ISI (inter-symbol interference) Data-dependent deterministic jitter caused by the time differences required for the signal to arrive at the receiver threshold when starting from different places in bit sequences (symbols). For example media attenuates the peak amplitude of the bit sequence [ 0,1,0,1... ], more than it attenuates the peak amplitude of the bit sequence [ 0,0,0,0,1,1,1,1... ], thus the time required to reach the receiver threshold with the [ 0,1,0,1... ] sequence is less than required from the [ 0,0,0,0,1,1,1,1... ] sequence. The run length of 4 produces a higher amplitude which takes more time to overcome when changing bit values and therefore produces a time difference compared to the run length of 1 bit sequence. When different run lengths are mixed in the same transmission the different bit sequences (symbols) therefore interfere with each other. ISI is expected whenever any bit sequence has frequency components that are propagated at different rates by the transmission media. This translates into a high level of high-frequency, datadependent, jitter. 4.1.66 JMD (jitter measuring device) A device used to measure jitter. Examples are a bit error rate tester (BERT), a timing interval analyzer (TIA), a single shot capture oscilloscope and processing software, or a HBWS. 4.1.67 JTF (Jitter Transfer Function) In general terms, the JTF of a system is the ratio of the jitter magnitude and phase of the output variable to the jitter magnitude and phase of the input variable, as a function of frequency for sinusoidal jitter excitation. In the case of a jitter definition, this defines the magnitude of the jitter, as a function of frequency allowed to be generated by the transmitter or tolerated by the receiver. In the case of a JMD, this defines the ratio of the reported jitter to the applied jitter, as a function of frequency for sinusoidal excitation. 4.1.68 junk An 8b/10b encoded data Dword sent between CONTP and another primitive transmitted on the link. All junk Dwords shall be ignored by the receiver. 4.1.69 LBA (Logical Block Address) As defined in the ATA8-ACS standard. 4.1.70 LBP (Lone Bit Pattern) This pattern is defined in section 7.2.4.3.5. The pattern is repetitive. 4.1.71 LED (Light Emitting Diode) Serial ATA Revision 3.0 Gold Revision page 37 of 663 4.1.72 legacy mode Legacy mode is the mode of operation which provides software-transparent communication of commands and status between a host and device using the ATA Command Block and Control Block registers. 4.1.73 legal character A legal character is one for which there exists a valid decoding, either into the data character or control character fields. Due to running disparity constraints not all 10-bit combinations result in a legal character. Additional usage restrictions in Serial ATA result in a further reduction in the SATA defined control character space. 4.1.74 LFSR (Linear Feedback Shift Register) Refer to section 9.4.5 for details on using a LFSR in scrambling. 4.1.75 LFTP (low frequency test pattern) This pattern provides a low frequency, which is allowed within the Serial ATA encoding rules. Pattern: 0111100011 1000011100b = encoded D30.3. The pattern is repetitive. 4.1.76 LL (laboratory load) An electrical test system connected to the unit under test. The LL receives a signal from the UUT at the defined impedance level of 100 Ohms differential and 25 Ohms common mode. 4.1.77 LSS (laboratory sourced signal or lab-sourced signal) An instrument and electrical test system connected to the unit under test. The LSS provides a signal to the UUT at the defined impedance level of 100 Ohms differential and 25 Ohms common mode. 4.1.78 MFTP (mid frequency test pattern) This pattern provides a middle frequency which is allowed within the Serial ATA encoding rules. Pattern: 1100110011 0011001100b = encoded D24.3. The pattern is repetitive. 4.1.79 NCQ streaming command An NCQ Streaming command is a command using the FPDMA QUEUED protocol for which the ICC field is non-zero. 4.1.80 NCQ Non-streaming command An NCQ Non-Streaming command is a command using the FPDMA QUEUED protocol which the ICC field is zero. 4.1.81 OOB (Out-of-Band signaling) OOB signaling is a pattern of ALIGNP primitives or Dwords composed of D24.3 characters and idle time and is used to initialize the Serial ATA interface. OOB signaling is also used to recover from low power states and to signal specific actions during test modes. Refer to section 8. Serial ATA Revision 3.0 Gold Revision page 38 of 663 4.1.82 OS-aware hot plug The insertion of a SATA device into a backplane that has power shutdown. The backplane is later powered, and both the device and the host power up, and the host-initiated OOB sequence determines the time that SATA operations begin. 4.1.83 OS-aware hot removal The removal of a SATA device from a powered backplane, that has been first placed in a quiescent state. 4.1.84 Phy offline In this mode the host Phy is forced off and the host Phy does not recognize nor respond to COMINIT or COMWAKE. This mode is entered by setting the DET field of the SControl register to 0100b. This is a mechanism for the host to turn off its Phy. 4.1.85 PIO (programmed input/output) PIO is a means of accessing device registers. PIO is also used to describe one form of data transfers. PIO data transfers are performed by the host processor utilizing PIO register accesses to the Data register. 4.1.86 port address The control port and each device port present on a Port Multiplier have a port address. The port address is used to route FISes between the host and a specific device or the control port. 4.1.87 PRD (Physical Region Descriptor) A PRD table is a data structure used by DMA engines that comply with the ATA/ATAPI Host Adapters standard. The PRD describes memory regions to be used as the source or destination of data during DMA transfers. A PRD table is often referred to as a scatter/gather list. 4.1.88 primitive A primitive is a special Dword used by the Link layer for the transport control. Byte 0 of each primitive is a control character. 4.1.89 protocol-based port selection Protocol-based port selection is a method that may be used by a host to select the host port that is active on a Port Selector. Protocol-based port selection uses a sequence of Serial ATA OOB Phy signals to select the active host port. 4.1.90 quiescent power condition Entering a quiescent power condition for a particular Phy is defined as the Phy entering the idle bus condition as defined in section 7.5.2. 4.1.91 RJ (random jitter) Random jitter is Gaussian. Random jitter is equal to the peak to peak value of 14 times the 1 standard deviation value given the 10-12 BER requirement. 4.1.92 sector A set of data bytes accessed and referenced as a unit. Serial ATA Revision 3.0 Gold Revision page 39 of 663 4.1.93 SEMB (Serial ATA Enclosure Management Bridge) A SEMB is a logical block that translates Serial ATA transactions into I2C transactions to communicate enclosure services commands to a Storage Enclosure Processor. 4.1.94 SEP (Storage Enclosure Processor) A SEP is a logical block that interfaces with the various enclosure sensors and actuators in an enclosure and is controlled through an I2C interface to the Serial ATA Enclosure Management Bridge. 4.1.95 Shadow Register Block registers Shadow Register Block registers are interface registers used for delivering commands to the device or posting status from the device. 4.1.96 side-band port selection Side-band port selection is a method that may be used by a host to select the host port that is active on a Port Selector. Side-band port selection uses a mechanism that is outside of the Serial ATA protocol for determining which host port is active. The port selection mechanism used in implementations that support side-band port selection is outside the scope of this specification. 4.1.97 SMART Self-Monitoring, Analysis, and Reporting Technology for prediction of device degradation and/or faults. 4.1.98 SSC (spread spectrum clocking) The technique of modulating the operating frequency of a signal slightly to spread its radiated emissions over a range of frequencies. This reduction in the maximum emission for a given frequency helps meet radiated emission requirements. 4.1.99 surprise hot plug The insertion of a SATA device into a backplane that has power present. The device powers up and initiates an OOB sequence. 4.1.100 surprise hot removal The removal of a SATA device from a powered backplane, without first being placed in a quiescent state. 4.1.101 SYNC Escape The condition when SYNCP is used to escape from the present FIS transmission on the interface and resynchronize the link back to an IDLE state. The most common use of the SYNC Escape mechanism is to bring the link to an IDLE condition in order to send a Control Register FIS with a software reset to the device, but may be used at other times to recover link communication from erroneous conditions. A SYNC Escape is requested by the Transport layer to the Link layer. 4.1.102 TDR (time domain reflectometer) An instrument used to test the impedance of the unit under test. Serial ATA Revision 3.0 Gold Revision page 40 of 663 4.1.103 TIA (timing interval analyzer) Timing interval analyzer with Duty Cycle Distortion and ISI noise floor performance of better than 5% of a UI for K28.5 with less than 67 ps rise and fall times. 4.1.104 TJ (total jitter) Peak to peak value of (14 * RJ ) + DJ. 4.1.105 UI (unit interval) Equal to the time required to transmit one bit (e.g. 666.667 ps for Gen1). 4.1.106 unrecoverable error An unrecoverable error is defined as having occurred at any point when the device sets either the ERR bit or the DF bit to one in the Status register at command completion. 4.1.107 UUT (unit under test) The product under test and the other half of the “mated“ connector (which is physically on the laboratory load but considered part of the UUT). 4.1.108 VNA (vector network analyzer) An instrument used to test the impedance of the unit under test. 4.1.109 warm plug Device connection with host controller powered and power at connector pins off (un-powered). This mechanism is used in Slimline applications, refer to section 6.3. 4.1.110 word A word is an ordered set of sixteen (16) bits. The least significant bit is bit 0 and the most significant bit is bit 15. 4.1.111 xSATA The System to System Interconnects - Data Center Applications usage model (see section 5.2.5). 4.1.112 zero crossing To locate the zero crossing of a Data Eye, turn on the horizontal histogram function to horizontally enclose all waveforms associated with the “edge” and vertically limit to +/-5% of the waveform voltage. The “zero crossing” is the location of the mean of the waveforms. 4.2 Conventions Lowercase is used for words having the normal English meaning. Certain words and terms used in this document have a specific meaning beyond the normal English meaning. These words and terms are defined either in section 4.1 or in the text where they first appear. The names of abbreviations, commands, fields, and acronyms used as signal names are in all uppercase (e.g., IDENTIFY DEVICE). Fields containing only one bit are usually referred to as the "name" bit instead of the "name" field. Serial ATA Revision 3.0 Gold Revision page 41 of 663 Names of device registers begin with a capital letter (e.g., Command). Primitive names are followed by a ‘P’ subscript (e.g., R_OK ). P 4.2.1 Precedence If there is a conflict between text, figures, and tables, the precedence shall be tables, figures, and then text. 4.2.2 Keywords Several keywords are used to differentiate between different levels of requirements and optionality. 4.2.2.1 expected A keyword used to describe the behavior of the hardware or software in the design models assumed by this standard. Other hardware and software design models may also be implemented. 4.2.2.2 mandatory A keyword indicating items to be implemented as defined by this standard. 4.2.2.3 may A keyword that indicates flexibility of choice with no implied preference. 4.2.2.4 na A keyword that indicates that a field or value is not applicable and has no defined value and should not be checked by the recipient. 4.2.2.5 obsolete A keyword used to describe bits, bytes, fields, and code values that no longer have consistent meaning or functionality from one implementation to another. However, some degree of functionality may be required for items designated as “obsolete” to provide for backward compatibility. An obsolete bit, byte, field, or command shall never be reclaimed for any other use in any future standard. Bits, bytes, fields, and code values that had been designated as “obsolete” in previous standards may have been reclassified as “retired” in this standard based on the definitions herein for “obsolete” and “retired”. 4.2.2.6 optional A keyword that describes features that are not required by this standard. However, if any optional feature defined by the standard is implemented, the feature shall be implemented in the way defined by the standard. 4.2.2.7 retired A keyword indicating that the designated bits, bytes, fields, and code values that had been defined in previous standards are not defined in this standard and may be reclaimed for other uses in future standards. If retired bits, bytes, fields, or code values are utilized before they are reclaimed, they shall have the meaning or functionality as described in previous standards. Serial ATA Revision 3.0 Gold Revision page 42 of 663 4.2.2.8 reserved A keyword indicating reserved bits, bytes, words, fields, and code values that are set-aside for future standardization. Their use and interpretation may be specified by future extensions to this or other standards. A reserved bit, byte, word, or field shall be cleared to zero, or in accordance with a future extension to this standard. The recipient shall not check reserved bits, bytes, words, or fields. Receipt of reserved code values in defined fields shall be treated as a command parameter error and reported by returning command aborted. 4.2.2.9 shall A keyword indicating a mandatory requirement. Designers are required to implement all such mandatory requirements to ensure interoperability with other standard conformant products. 4.2.2.10 should A keyword indicating flexibility of choice with a strongly preferred alternative. Equivalent to the phrase “it is recommended”. 4.2.3 Numbering Numbers that are not immediately followed by a lowercase "b" or "h" are decimal values. Numbers that are immediately followed by a lowercase "b" (e.g., 01b) are binary values. Numbers that are immediately followed by a lowercase "h" (e.g., 3Ah) are hexadecimal values. 4.2.4 Dimensions All dimensions are shown in millimeters unless otherwise noted. 4.2.5 Signal conventions Signal names are shown in all uppercase letters. Serial ATA Revision 3.0 Gold Revision page 43 of 663 4.2.6 State machine conventions For each function to be completed a state machine approach is used to describe the sequence requirements. Each function is composed of several states to accomplish a set goal. Each state of the set is described by an individual state table. Table 1 below shows the general layout for each of the state tables that comprise the set of states for the function. Table 1 – State Table Cell Description State Designator: State name Transition condition 0 Transition condition 1 Action list[P | W] Next state 0 Next state 1 Each state is identified by a state designator and a state name. The state designator is unique among all states in all state diagrams in this document. The state designator consists of a set of letters that are capitalized followed by a unique number. The state name is a brief description of the primary action taken during the state, and the same state name may appear in other state diagrams. If the same primary function occurs in other states in the same state diagram, they are designated with a unique letter at the end of the name. Additional actions may be taken while in a state and these actions are described in the state description text. Each transition is identified by a transition label and a transition condition. The transition label consists of the state designator of the state from which the transition is being made followed by the state designator of the state to which the transition is being made. The transition condition is a brief description of the event or condition that causes the transition to occur and may include a transition action that is taken when the transition occurs. This action is described fully in the transition description text. Upon entry to a state, all actions to be executed in that state are executed. If a state is re-entered from itself, all actions to be executed in the state are executed again. It is assumed that all actions are executed within a state and that transitions from state to state are instantaneous. 4.2.7 Byte, word and Dword Relationships The most significant bit in a byte (i.e., bit 7) is shown on the left (see Figure 1). A word may be represented as an ordered set of two (2) bytes. The least significant byte (lower byte) is byte 0 and the most significant byte (upper byte) is byte 1. The most significant byte is shown on the left (see Figure 1). A Dword may be represented as an ordered set of two (2) words. The least significant word (lower word) is word 0 and the most significant word (upper word) is word 1. The most significant word is shown on the left (see Figure 1). A Dword may be represented as an ordered set of four (4) bytes. The least significant byte is byte 0 and the most significant byte is byte 3. The most significant byte is shown on the left (see Figure 1). Serial ATA Revision 3.0 Gold Revision page 44 of 663 76543210 Byte 111111 5432109876543210 Word Byte 1 Byte 0 332 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 109 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Dword Word 1 Word 0 Byte 3 Byte 2 Byte 1 Figure 1 – Byte, word and Dword relationships Byte 0 Serial ATA Revision 3.0 Gold Revision page 45 of 663 5 General overview Serial ATA is a high-speed serial link replacement for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential layer that utilizes Gigabit technology and 8b/10b encoding. Figure 2 illustrates how two devices are connected to a parallel ATA host adapter. This method allows up to two devices to be connected to a parallel ATA bus using a Master/Slave communication technique. Each device is connected via a ribbon cable that “daisy chains” the devices. Operating system Application 1 Application 2 Parallel ATA adapter Driver Application 3 Disk drive Disk drive Figure 2 – Parallel ATA device connectivity Serial ATA Revision 3.0 Gold Revision page 47 of 663 Figure 3 shows an example of how the same two devices are connected using a Serial ATA HBA. In this figure the dark grey portion is functionally identical to the dark grey portion of Figure 2. Host software that is only parallel ATA aware accesses the Serial ATA subsystem in exactly the same manner and functions correctly. In this case, however, the software views the two devices as if they were “masters” on two separate ports. The right hand portion of the HBA is of a new design that converts the normal operations of the software into a serial data/control stream. The Serial ATA structure connects each of the two devices with their own respective cables in a pointto-point fashion. Operating System Application 1 Application 2 Serial ATA HBA Driver Application 3 Disk Drive Disk Drive Figure 3 – Serial ATA connectivity 5.1 Architecture There are four layers in the Serial ATA architecture: Application, Transport, Link, and Phy. The Application layer is responsible for overall ATA command execution, including controlling Command Block Register accesses. The Transport layer is responsible for placing control information and data to be transferred between the host and device in a packet/frame, known as a Frame Information Structure (FIS). The Link layer is responsible for taking data from the constructed frames, encoding or decoding each byte using 8b/10b, and inserting control characters such that the 10-bit stream of data may be decoded correctly. The Physical layer is responsible for transmitting and receiving the encoded information as a serial data stream on the wire. Serial ATA Revision 3.0 Gold Revision page 48 of 663 Commands and applications (Section 12 and 13) Serial digital transport control (Section 10) Serial digital link control (Section 9) Serial physical interface plant (Section 7 and 8) Host located layers Application layer 4 Transport layer 3 Link layer 2 Physical layer 1 Commands and applications (Section 11 and 13) Serial digital transport control (Section 10) Serial digital link control (Section 9) Serial physical interface plant (Section 7 and 8) Device located layers Figure 4 – Communication layers The host may interact with the Application layer through a register interface that is equivalent to that presented by a traditional parallel ATA host adapter. When using parallel ATA emulation, the host software follows existing ATA/ATAPI-6 standards and conventions when accessing the register interface and follows standard command protocol conventions. 5.2 Usage Models This section describes some of the potential applications of Serial ATA, including usage models that take advantage of features such as Native Command Queuing, enclosure management, Port Multipliers, and Port Selectors. Table 2 outlines the different usage models described throughout the section as well as highlights the relative requirements applicable to those usage models. Table 2 shows which characteristics in the first column are necessary to support the usage models in the top row. Feature specific (FS) is intended to indicate that Gen1 is required but higher data rates are optional. NOTE: The exact position of compliance points associated with the transmitter and the receiver are defined in sections 7.2.2.4 and 7.2.2.5. Serial ATA Revision 3.0 Gold Revision page 49 of 663 Characteristic Use model section number Cable and/or backplane type Cable length Cable Electrical Attenuation at 4.5GHz Host-side connector Device-side connector Gen1i 1.5 Gbps Gen1m 1.5 Gbps Internal 1 meter Cabled Host to Device 5.2.1 Int SL <= 1 m Table 18 -6dB 6.1.5 6.1.3.1 R NS Short Backplane to Device 5.2.2 BP P P P 6.1.3.1 D (host to provide received signal) H Long Back plane to Device 5.2.3 BP P -16dB P 6.1.3.1 (inside canister) D NS Table 2 – Usage Model Descriptions Internal 4-lane Cabled Disk Arrays System to System Inter connects – Data Center Applications xSATA System to System Inter connects – Data Center Applications xSATA 5.2.4 5.2.5 5.2.5 Int ML Ext ML Ext ML <= 1 m Table 18 -6dB 6.1.11 or 6.1.12 6.1.3.1 R <= 2 m Table 20 -8dB 6.5.3 (key 7) 6.5.3 (key 7) NS *subject to electrical requirements Table 21 -16dB 6.5.2 or 6.5.3 (key 1) 6.5.2 or 6.5.3 (key 1 or 4) NS NS R (key 7) NS System to System Inter connects – External Desktop Applications eSATA 5.2.6 Ext SL <= 2 m Table 19 -8dB 6.5.1 6.5.1 NS R Proprietary Serial ATA Disk Arrays 5.2.7 BP and cable Table 18 -6dB 6.1.5 or P 6.1.3.1 R NS Serial ATA and SAS 5.2.8 BP P P SAS 6.1.3.1 D NS LIFSATA 5.2.10 P P Table 18 -6dB 6.4.3 6.4.2 R NS Serial ATA Revision 3.0 Gold Revision page 50 of 663 Characteristic Internal Short Long Internal System to System to System to Proprietary Serial 1 meter Backplane Back 4-lane System Inter System Inter System Inter Serial ATA ATA Cabled to Device plane to Cabled connects – connects – connects – Disk and Host to Device Disk Data Center Data Center External Arrays SAS Device Arrays Applications Applications Desktop xSATA xSATA Applications eSATA Gen2i FS D (host to D FS NS NS NS FS D 3.0 Gbps provide received signal) Gen2m NS H NS NS FS (key 7) NS FS NS NS 3.0 Gbps Gen1x NS NS H, D NS NS R NS NS NS 1.5 Gbps Gen2x NS NS H, D NS NS FS NS NS NS 3.0 Gbps Gen3i FS NS NS FS NS NS NS FS D 6.0 Gbps Hot plug NS R R NS R R R R R support Key: R – Required : configuration requires appropriate capabilities FS – Feature specific : configuration is supported by specification but may be tied to an optional capability NOTE: Feature specific is intended to indicate that Gen1 is required but higher data rates are optional. NS – Not supported : configuration is not supported by definition in specification P – Proprietary : implementation is vendor specific and not defined in specification H – Host D – Device SL – single lane ML – multi-lane Int – Internal Ext – External BP – Backplane NOTE : Many of the references in the table are section numbers or notations of clarification which do not require Key values LIFSATA FS NS NS NS FS NS Serial ATA Revision 3.0 Gold Revision page 51 of 663 5.2.1 Internal 1 meter Cabled Host to Device In this application, Gen1i, Gen2i or Gen3i electrical specifications compliant points are located at the Serial ATA mated connectors on both the host controller and device. The cable, specified in section 6, operates at 1.5 Gbps, 3.0 Gbps and 6.0 Gbps. The application may comply with the electrical hot plug specification described in section 7.2.5. Gen1i / Gen2i / Gen3i Compliance Points Host Controller Device Device Gen1i / Gen2i / Gen3i Compliance Points Figure 5 – Internal 1 meter Cabled Host to Device Application Serial ATA Revision 3.0 Gold Revision page 52 of 663 5.2.2 Short Backplane to Device In this application, Gen1i/2i disk devices within a small disk array are installed into drive canisters which are plugged into a “short” backplane. The host controller connecting to the Backplane shall contain a Host component which exceeds Gen1i/2i transmitter and receiver Differential Swings specifications so that the signals at the host controller connector complies with or exceeds the Gen1m/2m electrical specifications. All other electrical specifications at this compliance point shall meet Gen1i/2i specifications. Compliance points are located at the Serial ATA mated connectors on both the device (Gen1i/2i) and the host controller (Gen1m/2m). The signaling at the host controller connector may exceed the Gen1m/Gen2m transmit maximum providing the Gen1i/Gen2i receiver maximum is not exceeded at the device connector. The application does not contain a cable but routes Serial ATA signals on printed circuit board at 1.5 Gbps and 3.0 Gbps where it is anticipated that the backplanes attenuate signals more than the compliant copper cable described in section 6. The burden falls on the host controller to increase transmit signal swing and accommodate smaller receive swings at the host controller connector. The Gen1i/2i devices are not required to comply with the electrical hot plug specification described in section 7.2.5. However, there are practical application benefits from complying with the hot plug electrical specifications. NOTE: At Gen2 speeds the designer faces significant challenges regarding signal integrity issues. Validation/feasibility data at Gen2 speeds has not been provided. Making this work is up to the system designer. Using a laboratory load to measured the host controller amplitude or jitter at the device connector and comparing with Serial ATA Revision 3.0 Gold Revision page 53 of 663 Table 33 is not appropriate. Additional margin is required due to the non-ideal impedance match of transmitter and receiver. The receiver is tested to work at these amplitudes and jitter levels when the signal is applied from a lab-sourced signal. Gen1m Compliance Points (4 Plcs) Backplane Device Host Controller Gen1i Compliance Points (4 Plcs) Drive Canister Figure 6 – Short Backplane to Device Application 5.2.3 Long Backplane to Device In this 1.5 Gbps or 3.0 Gbps application, the length of the backplane is longer than in the previous example so attenuation of signals reduce their amplitude beyond usable levels. Therefore an IC may be placed between the device and the canister’s connector to the backplane to convert the disk’s Gen1i/Gen2i levels to Gen1x/Gen2x levels. A typical circuit might be a Serial ATA Port Selector. Likewise, the host controller complies with Gen1x/Gen2x levels at the backplane connector to the host controller. This allows reliable transmission of Serial ATA data over backplanes longer than in the Short Backplane Application described above. The burden of determining whether a Backplane Application is Short or Long falls upon the system designer based on the system’s attenuation. Compliance points are located at the Serial ATA mated connectors on both the canister (Gen1x/Gen2x) and the host controller (Gen1x/Gen2x). The Gen1x/Gen2x Electrical Specifications require Hot Plug capability so that the disk/canister may be plugged and unplugged without damage. Serial ATA Revision 3.0 Gold Revision page 54 of 663 Gen1x / Gen2x Compliance Points Host Controller Backplane IC IC IC IC … Device IC IC IC IC Gen1x/Gen2x Compliance Points Drive Canister Gen1i/Gen2i Compliance Points Figure 7 – Long Backplane to Device Application 5.2.4 Internal 4-lane Cabled Disk Arrays In this application, Gen1i, Gen2i and Gen3i Serial ATA devices are connected to the host controller via the internal 4-lane cable solution. Gen1i, Gen2i and Gen3i specifications shall be met at each end of the 4-lane cable mated interface. The internal 4-lane cable shall connect to the device by one of the following two approaches. • The host end of the internal 4-lane solution shall mate directly to the host controller board. The device end shall consist of four individual single lane Serial ATA cables for direct mate with up to four individual Serial ATA devices. • The host end of the internal 4-lane solution shall mate directly to the host controller board. The device end of the internal 4-lane cable shall consist of a single internal 4-lane connector mated to a backplane which provides individual connection points to up to four Serial ATA devices. The backplane design is proprietary. Serial ATA Revision 3.0 Gold Revision page 55 of 663 In the second solution, attenuation of the backplane reduces signal amplitude below specification limits at the compliance points. An IC, such as a Port Selector, shall be placed between the device and the internal 4-lane cable mated interface. Gen1i, Gen2i and Gen3i specifications shall be met at each end of the 4-lane cable mated interface and the device mated connector interface. Gen1i / Gen2i / Gen3i Compliance Points (8 Plcs) Proprietary Backplane Device Serial ATA Host Internal 4-lane Cable IC to ensure Gen1i / Gen2 / Gen3i Compliance (8 Plcs) Gen1i Compliance Points (4 Plcs) Drive Canister Figure 8 – Internal 4-lane Cabled Disk Array NOTE: For Gen2i and Gen3i devices the link from the host to the drive (through the IC on the backplane) does not have an electrical specification for the “delivered signal” to the drive. Consider the compliance point for the backplane-drive connector (through the mated pair). If the signal at the compliance point, into a lab load meets all the requirements of Table 29 and Serial ATA Revision 3.0 Gold Revision page 56 of 663 Table 31, and the backplane meets all the requirements of Table 30, then interoperability is confirmed. However, it is anticipated that the additional trace length on the backplane between the IC and the backplane-device connector makes compliance to these specifications difficult. The burden for ensuring interoperability with all Gen1i/Gen2i devices falls upon the implementer of the system. Essentially the implementer would use simulations and empirical results to confirm that the compliance point at the backplane-device connector is equivalent to or better than a compliant host and cable combination. 5.2.5 System-to-System Interconnects – Data Center Applications (xSATA) This application is defined as external storage applications that require more than one serial link between systems. This application uses the external Multilane cables defined in sections 6.5.2 and 6.5.3, and may be referred to as xSATA. For system-to-system interconnects that require cables of approximately two meters or less (i.e. pedestal to pedestal, blade to blade, or intrarack connections) either Gen1m/Gen2m or Gen1x/Gen2x Electrical Specifications are used. For system-to-system interconnects that require distances greater than two meters (i.e. rack to rack,) Gen1x/Gen2x Electrical Specifications are used. All external Serial ATA cables function at both 1.5 Gbps and 3.0 Gbps. Use of a cable that operates at 1.5 Gbps but not at 3.0 Gbps is allowed but this cable assembly shall not be interchangeable with standard Serial ATA cables. For example, if this 1.5 Gbps cable uses Serial ATA specified connectors, the cable shall be keyed to insure that it cannot plug into standard Serial ATA connections. Hot pluggability is a requirement in this application. Compliance points are located at the mated bulkhead connectors of each system as shown in the example implementation in Figure 9. If a SATA endpoint device is included in the system, it shall not be connected directly to the external connectors. Instead, a bridge shall be used between the external connectors and the endpoint device. Some examples of bridges include repeaters/retimers, Port Multipliers, and RAID controllers. NOTE: Interconnects between Gen1m/Gen2m and Gen1x/Gen2x systems are not allowed. NOTE: Gen3 is not defined for xSATA. Serial ATA Revision 3.0 Gold Revision page 57 of 663 Limited Length External Multilane Interconnect Gen1m / Gen2m Compliance Points Gen1i / Gen2i / Gen3i Compliance Points SSeySSsreyitaesrlitmaeAlmTAATA Host Controller |_____ < two meters _____| SerSiaylsAteTSmAerial ATA h Bridge h h h Extended Length External Multilane Interconnect Gen1x / Gen2x Compliance Points Gen1i / Gen2i / Gen3i Compliance Points SSeySSsreyitaesrlitmaeAlmTAATA Host Controller Serial ATA System h Bridge h h h Figure 9 – System-to-System Data Center Interconnects Serial ATA Revision 3.0 Gold Revision page 58 of 663 5.2.6 System-to-System Interconnects – External Desktop Applications (eSATA) This application is aimed at external storage applications that require a single lane with approximately two meters or less of cable length. This application uses the external single lane connector system defined in section 6.5.1, and may be referred to as eSATA. NOTE: Gen3i is not defined for eSATA. In the example shown below, a device enclosure contains a Gen1i / Gen2i device and an interposer card which contains an integrated circuit unless the device is specifically designed for external connection. Regardless of the implementation, the outside of the device enclosure shall meet Gen1m specifications when operating at Gen1 speeds and Gen2m specifications when operating at Gen2 speeds. A cable/connector has been defined for this application which operates at both Gen1 and Gen2. The host system has an external connector which meets Gen1m specifications when operating at Gen1 speeds and Gen2m specifications when operating at Gen2 speeds. The entire system shall meet the following requirements: • The cable/connector shall operate at Gen1 and Gen2 speeds. Systems shall not deploy any cable which cannot operate at Gen2 speeds when the host system and device enclosure both comply with Gen2m electrical specifications. • The host system and device enclosure shall comply with Gen1m specifications when operating at Gen1 speeds. • The host system and device enclosure may operate at Gen2 speeds. However, if they operate at Gen2 speeds the host system and device enclosure shall comply with Gen2m specifications when operating at Gen2 speeds and shall also be able to operate at Gen1 speeds using Gen1m electrical specifications. • The host system and the device enclosure shall comply with the Hot Plug Specifications in this document. • NOTE: AC Coupling on the transmitters and receivers of the host system and device enclosure is strongly recommended for Gen1m and required for Gen2m. Gen1m / Gen2m Compliance Point Gen1i / Gen2i / Gen3i Compliance Point Device Host System Gen1m / Gen2m Compliance Point IC Device Enclosure Figure 10 – External Desktop Application Serial ATA Revision 3.0 Gold Revision page 59 of 663 5.2.7 Proprietary Serial ATA Disk Arrays In this application, Serial ATA devices are connected to a backplane and the links are routed over a combination of internal backplanes or cables as well as an external cable to a Serial ATA system. There are not semiconductors between the devices and the system so the intermediate connectors are not compliance points. Although this application is allowed, the external connectors on the disk array shall not be standard Serial ATA connectors. This is to prevent users from connecting standard external cables between the system and the disk array since they may not function reliably. NOTE: The designer faces significant challenges regarding signal integrity issues because of complexity of the interface, which may require additional margin. Validation/feasibility data has not been provided. Making this work is up to the system designer. Using a laboratory load to measured the host controller amplitude or jitter at the device connector and comparing with Table 33 is not appropriate. The receiver is tested to work at these amplitudes and jitter levels when the signal is applied from a lab-sourced signal. Proprietary Cable Backplane Device Serial ATA System Gen1i /Gen2i / Gen3i Compliance Points (4 Plcs) Proprietary Cable or PCB Non-Compliance Points (8 Plcs) Gen1i /Gen2i / Gen3i Compliance Points (4 Plcs) Drive Canister Figure 11 – SATA Disk Arrays 5.2.8 Serial ATA and SAS The SAS reference is a standard that specifies a SCSI transport protocol over a serial link. The SAS standard borrows heavily from the SATA Phy, Link, and Transport layers. A SAS domain may support attachment to and control of unmodified SATA devices connected directly into the SAS domain using the Serial ATA Tunneled Protocol (STP). Serial ATA Revision 3.0 Gold Revision page 60 of 663 5.2.9 Potential External SATA Incompatibility Issues WARNING: The functionality of External Desktop and External Data Center cabled applications is not defined by this specification. Consequently, two systems could be connected which may not interoperate even though all the components comply with the electrical specifications defined in this document. External applications are not required to support Port Multipliers or Port Selectors. As a result, a host with an External Data Center connector could be connected to a disk array containing a Port Multiplier and the resulting system may not operate correctly. 5.2.10 Mobile Applications Applications and compliance points for Serial ATA devices within or connected to mobile computers are not defined in this document, except for embedded applications. If any proprietary cables/connectors or electrical specifications are developed for this application, the system shall be designed so as to prevent connection with standard SATA components. If standard cables/connectors/electrical interfaces are used within the mobile computer, within the docking bay or to external storage components, these shall comply with the applicable requirements in this specification and interoperate properly with Serial ATA components. Internal Applications: It is expected that all internal interfaces comply with the Gen1i, Gen2i, and/or Gen3i specifications. Any mobile computer designer modifying electrical specifications of hosts and devices within the mobile computer is free to do so, however, all proprietary interfaces shall be designed so as to prevent connection with standard SATA components. Docking Bay Applications: Proprietary docking bay interfaces shall be designed so as to prevent connection with standard SATA components. External Applications: Applications for external Serial ATA interfaces on mobile computers may use either the External Desktop cable/connector (Gen1m/Gen2m) or the System-to-System Data Center cable/connector (Gen1m/Gen2m or Gen1x/Gen2x). Proprietary solutions shall be designed so as to prevent connection with standard SATA components. Serial ATA Revision 3.0 Gold Revision page 61 of 663 Embedded Applications Gen1i / Gen2i / Gen3i Compliance point Host FPC Gen1i / Gen2i / Gen3i Compliance point Device LIF-SATA Connector LIF-SATA Connector Figure 12 - Embedded LIF-SATA Application In this application, the device is connected to a host controller via a flexible printed circuit cable (FPC). The FPC interfaces shall comply with Gen1i electrical requirements listed in Table 18. The compliance points are shown in Figure 12. Gen2i or Gen3i compliance is feature specific, but if implemented, shall also comply with the electrical requirements listed in Table 18. 5.2.11 Port Multiplier Example Applications One possible application of the Port Multiplier is to increase the number of Serial ATA connections in an enclosure that does not have a sufficient number of Serial ATA connections for all of the devices in the enclosure. An example is shown in Figure 13. A Multilane cable with two Serial ATA connections is delivered to the enclosure. The enclosure contains eight Serial ATA devices. To create the appropriate number of Serial ATA connections, two 1-to-4 Port Multipliers are used to create eight Serial ATA connections. Serial ATA Revision 3.0 Gold Revision page 62 of 663 Drive Enclosure Multi Lane Serial ATA cable Port Multipliers Figure 13 – Enclosure example using Port Multipliers with Serial ATA as the connection within the rack Another example is shown in Figure 14. Fibre Channel, Infiniband, or Gigabit Ethernet is used as the connection within the rack to the enclosure. Inside the enclosure, a host controller creates two Serial ATA connections from the connection delivered. The enclosure contains eight Serial ATA devices. To create the appropriate number of Serial ATA connections, two 1-to-4 Port Multipliers are used to create eight Serial ATA connections. Serial ATA Revision 3.0 Gold Revision page 63 of 663 Drive Enclosure Fibre Channel, InfiniBand, or Gigabit Ethernet Port Multipliers Figure 14 – Enclosure example using Port Multipliers with a different connection within the rack The Port Multiplier allows host controllers with a modest number of connections to be used in these enclosures and then the connectivity is increased as product requirements dictate. Another example application is using a Port Multiplier to increase the number of Serial ATA connections in a mobile docking station. The example shown in Figure 15 has a proprietary interface between the laptop and the docking station. The proprietary interface may route a Serial ATA connection from the laptop to the docking station or the docking station may create a Serial ATA connection itself. The docking station routes the Serial ATA connection to a Port Multiplier to create an appropriate number of Serial ATA connections for the number of devices to be attached. Serial ATA Revision 3.0 Gold Revision page 64 of 663 Laptop or Mobile Device “Wedge” or Docking Station CD External HDD Other Serial ATA-based peripherals Figure 15 – Mobile docking station example using a Port Multiplier These are a few examples of possible applications of the Port Multiplier and are not meant to be all encompassing. Serial ATA Revision 3.0 Gold Revision page 65 of 663 6 Cables and Connectors This section defines the connectors and cable assemblies for Serial ATA. It specifies: • The mating interfaces between the connectors • The connector location on the Serial ATA device • The electrical, mechanical and reliability requirements of the connectors and cable assemblies The mating interfaces of Serial ATA connectors are defined in terms of their front end (i.e. separable) characteristics only. All SATA internal and external connector contact mating areas shall have a gold or gold-compatible finish. Unless otherwise specified, connector back end characteristics including finish, PCB mounting features, and cable termination features are not defined. 6.1 Internal cables and connectors 6.1.1 Internal Single Lane Description A Serial ATA device may be either directly connected to a host or connected to a host through a cable. For direct connection, the device plug connector, shown as (a) and (b) in Figure 16, is inserted directly into a backplane connector, illustrated as (g) in Figure 16. The device plug connector and the backplane connector incorporate features that enable the direct connection to be hot pluggable and blind mateable. For connection via cable, the device signal plug connector, shown as (a) in Figure 16, mates with the signal cable receptacle connector on one end of the cable, illustrated as (c) in Figure 16. The signal cable receptacle connector on the other end of the cable is inserted into a host signal plug connector, shown as (f) in Figure 16. The signal cable wire consists of two twinax sections in a common outer sheath. Besides the signal cable, there is also a separate power cable for the cabled connection. A Serial ATA power cable includes a power cable receptacle connector, shown as (d) in Figure 16, on one end and may be directly connected to the host power supply on the other end or may include a power cable receptacle on the other end. The power cable receptacle connector on one end of the power cable mates with the device power plug connector, shown as (b) in Figure 16. The other end of the power cable is attached to the host as necessary. Serial ATA Revision 3.0 Gold Revision page 67 of 663 (a) (c) (b) (d) (e) (f) (g) Figure 16 – Serial ATA connector examples Illustrated above: (a) device signal plug segment or connector; (b) device power plug segment or connector; (c) signal cable receptacle connector, to be mated with (a); (d) power cable receptacle connector, to be mated with (b); (e) signal cable receptacle connector, to be mated with (f), the host signal plug connector; (g) backplane connector mating directly with device plug connector (a) & (b). Serial ATA Revision 3.0 Gold Revision page 68 of 663 6.1.1.1 Figure 17 shows a direct cable / connector connection and highlights the signal path of the differential TX and RX pairs. Host Tx+ Host Tx- Host RxHost Rx+ KEY GND A+ A- GND BB+ GND Host Plug KEY 1 2 3 4 5 6 7 Cable Receptacle Host Chip, PCB & Connector Cable & Connectors KEY 1 2 3 4 5 6 7 Cable Receptacle KEY GND A+ A- GND BB+ GND Device Plug Dev Rx+ Dev Rx- Dev TxDev Tx+ Device Chip, PCB & Connector Figure 17 – SATA Cable / Connector Connection Diagram The connector on the left represents the Host with TX/RX differential pairs connected to a cable. The connector on the right shows the Device with TX/RX differential pairs also connected to the cable. Notice also the ground path connecting the shielding of the cable to the Cable Receptacle. Figure 18 shows the connection between host and device as a direct connection. It is similar to the cable/connector connection with the exception of the cable. Serial ATA Revision 3.0 Gold Revision page 69 of 663 Host Tx+ Host Tx- Host RxHost Rx+ KEY GND A+ A- GND BB+ GND KEY GND A+ A- GND BB+ GND Direct Connect Dev Rx+ Dev Rx- Dev TxDev Tx+ Host Chip, PCB & Connector Device Chip, PCB & Connector Figure 18 – SATA Host / Device Connection Diagram In both cases the connection of the TX differential signal pair on the host side to the RX differential signal pair on the device side. A similar connection of the host RX pair to the device TX pair is also shown. 6.1.2 Connector locations The device connector location is defined to facilitate blind mating. Figure 19 and Figure 20 define the connector location on 5.25” devices. Optical devices shall locate the connector as indicated in the optical device connector location. Non-optical devices should locate the connector as indicated in the optical device connector location but may locate the connector as indicated in the non-optical device alternate connector location. The Serial ATA connector is nominally flush to the end of the device factor. Figure 21 defines the connector location on side mounted 3.5” devices. Figure 22 defines the connector location on bottom mounted 3.5” devices. Refer to EIA-740 and SFF-8301 for 3.5” device form factor specifications. The Serial ATA connector is nominally flush to the end of the device factor. Figure 23 defines the connector location on side mounted 2.5” devices. Figure 24 defines the connector location on bottom mounted 2.5” devices. Refer to EIA-720 and SFF-8201 for 2.5” device form factor specifications. The Serial ATA connector nominally protrudes 0.3 mm from the end of the device factor. Figure 25 defines the Serial ATA connector location on side mounted 1.8” devices. Figure 26 defines the Serial ATA connector location on bottom mounted 1.8” devices. Refer to SFF-8111 for 1.8” device form factor specifications. The Serial ATA connector nominally protrudes 0.3 mm from the end of the device factor. To ensure mating of devices to backplanes with proper mechanical and electrical interface and without physical conflict, Figure 38 illustrates the fully mated condition of the device to a nominally Serial ATA Revision 3.0 Gold Revision page 70 of 663 flush backplane receptacle and Figure 27 defines the keep out zones for devices of all form factors. The application shall ensure that these areas do not contain any materials or construction that prevents the fully mated condition. Figure 19 – Optical Device Plug Connector Location on 5.25" form factor Serial ATA Revision 3.0 Gold Revision page 71 of 663 Figure 20 – Non-Optical Alternate Device Plug Connector Location on 5.25" form factor Serial ATA Revision 3.0 Gold Revision page 72 of 663 Figure 21 – Device Plug Connector Location on 3.5” Side Mounted Device Serial ATA Revision 3.0 Gold Revision page 73 of 663 Figure 22 – Device Plug Connector Location on 3.5" Bottom Mounted Device Serial ATA Revision 3.0 Gold Revision page 74 of 663 Figure 23 – Device Plug Connector Location on 2.5” Side Mounted Device Serial ATA Revision 3.0 Gold Revision page 75 of 663 Figure 24 – Device Plug Connector Location on 2.5" Bottom Mounted Device Serial ATA Revision 3.0 Gold Revision page 76 of 663 Figure 25 – Device Plug Connector Location on 1.8" Side Mounted Device Serial ATA Revision 3.0 Gold Revision page 77 of 663 Figure 26 – Device Plug Connector Location on 1.8" Bottom Mounted Device Serial ATA Revision 3.0 Gold Revision page 78 of 663 Figure 27 – Device Plug Connector Keep Out Zones Notes: 1. The 1.50 keepout area above Datum A extends into the form factor to the connector Datum C in Figure 28. 2. The 1.00 keepout area shown in Detail 1 applies to both ends of the connector and extends from the connector housing outward to the outermost point of the form factor. 6.1.3 Mating interfaces 6.1.3.1 Device plug connector Figure 28 and Figure 29 show the interface dimensions for the device plug connector with both signal and power segments. The device plug includes optional features to allow use of latching cables, fillets, and additional material to improve connector robustness. Table 3 defines the pin definitions and contact mating sequence for hot plug. These optional features should be included in all plug designs. Serial ATA Revision 3.0 Gold Revision page 79 of 663 Figure 28 – Device Plug Connector Serial ATA Revision 3.0 Gold Revision page 80 of 663 Figure 29 – Device Plug Connector (additional views) Serial ATA Revision 3.0 Gold Revision page 81 of 663 6.1.3.2 Pin Signal Definition and Contact Mating Sequence Table 3 details the pin names, types, and contact order of the two SATA plug options. A brief description is also included for signal, ground and power pins. There are total of 7 pins in the signal segment and 15 pins in the power segment. Table 3 – Signal and Power SATA Plug and Nominal Mate Sequence Name Type Description Cable Usage2, 3 Backplane Usage3 Signal Segment Signal Segment Key S1 GND S2 S3 A+ A- Differential Signal Pair A S4 GND S5 S6 BB+ Differential Signal Pair B S7 GND 1st Mate 2nd Mate 2nd Mate 1st Mate 2nd Mate 2nd Mate 1st Mate 2nd Mate 3rd Mate 3rd Mate 2nd Mate 3rd Mate 3rd Mate 2nd Mate Signal Segment "L" Central Connector Gap4 Power Segment Power Segment "L" P1 V33 3.3 V Power P2 V33 3.3 V Power P3 V33 3.3 V Power, Pre-charge P4 GND P5 GND P6 GND P7 V5 5 V Power, Pre-charge P8 V5 5 V Power P9 V5 5 V Power P10 GND P11 DAS/DSS Device Activity Signal / Disable Staggered Spinup1 P12 GND P13 V12 12 V Power, Pre-charge P14 V12 12 V Power P15 V12 12 V Power Power Segment Key 2nd Mate 2nd Mate 1st Mate 1st Mate 1st Mate 1st Mate 1st Mate 2nd Mate 2nd Mate 1st Mate 2nd Mate 1st Mate 1st Mate 2nd Mate 2nd Mate 3rd Mate 3rd Mate 2nd Mate 1st Mate 2nd Mate 2nd Mate 2nd Mate 3rd Mate 3rd Mate 2nd Mate 3rd Mate 1st Mate 2nd Mate 3rd Mate 3rd Mate NOTE: 1. The corresponding pin to be mated with P11 in the power cable receptacle connector shall always be grounded. For specific optional usage of pin P11 see section 6.7. 2. Although the mate order is shown, hot plugging is not supported when using the cable connector receptacle. 3. All mate sequences assume zero angular offset between connectors. 4. The signal segment and power segment may be separate. Mating Configuration Notes • All pins are in a single row with 1.27 mm (.050”) pitch • All ground pins in the Serial ATA device plug power segment (connector pins P4, P5, P6, P10, and P12) shall be bussed together on the Serial ATA device. • The connection between the Serial ATA device signal ground and power ground is vendor specific. • The following sets of voltage pins in the Serial ATA device plug power segment shall be bussed together on the Serial ATA device: Serial ATA Revision 3.0 Gold Revision page 82 of 663 P1, P2, and P3 3.3 V power delivery and precharge P7, P8, and P9 5 V power delivery and precharge P13, P14, and P15 12 V power delivery and precharge • The use of power delivery schemes that do not deliver all the specified voltages should only be used in scenarios where there is sufficient configuration control to ensure that the attached device does not require a supply voltage that is not provided. Signal Segment Key Signal Segment Pin S1 Power Segment Pin P1 Power Segment Key Figure 30 – Connector Pin and Feature Locations 6.1.4 Signal cable receptacle connector Figure 31 shows the interface dimensions for the signal cable receptacle connector. There are two identical receptacles at the two ends of the Serial ATA cable assembly. The cable receptacle mates with either the signal segment of the device plug connector on the device, or the host plug connector on the host. Figure 32 defines an optional positive latch solution for internal cabled system applications. The latch requires the user to press and hold a release mechanism when disconnecting the cable. The latching feature option for device and host plug connectors are required in order to provide a latching surface. This latching feature option is called ClickConnect. Without a latching surface, there is no retention feature to hold a latching cable assembly in place. It is optional to implement the latch on cable receptacles. Serial ATA Revision 3.0 Gold Revision page 83 of 663 Figure 31 – Cable receptacle connector interface dimensions Serial ATA Revision 3.0 Gold Revision page 84 of 663 Figure 32 – Latching signal cable receptacle (ClickConnect) The pin out of the cable receptacle connector is the mirror image of the signal segment of the device plug connector. Notice that: • The two differential pin pairs are terminated with the corresponding differential cable pairs • The ground pins are terminated with the cable drain wires, if it applies • The choice of cable termination methods, such as crimping or soldering is up to each connector vendor 6.1.5 Signal host plug connector The signal host plug connector is to be mated with one end of the Serial ATA cable assembly. The pinout of the host plug connector is the mirror image of the signal cable receptacle. Figure 33 shows the host plug connector interface definition. The host plug includes optional features to allow use of latching cables, fillets, and additional material to improve connector robustness. Serial ATA Revision 3.0 Gold Revision page 85 of 663 Figure 33 – Host signal plug connector interface dimensions 6.1.5.1 Internal plug stacking The purpose of this recommended layout is to conserve motherboard, HBA and I/O controller printed circuit board space to support system density and size goals for such products. For applications where multiple Serial ATA ports or connectors are stacked together on the host, there is a clearance or spacing requirement to prevent the cable assemblies from interfering with Serial ATA Revision 3.0 Gold Revision page 86 of 663 each other. Figure 34 shows the recommended clearance or spacing. Figure 35 shows the recommended clearance and orientation to allow access for latching cables. Figure 34 – Non-Latching Connector Stack Spacing and Orientation Figure 35 – Latching Connector Stack Spacing and Orientation Serial ATA Revision 3.0 Gold Revision page 87 of 663 6.1.6 Backplane connector The backplane connector is to be blind-mated directly with the device plug connector. The interface dimensions for the backplane connector are shown in Figure 36. Note that dimension B allows two values: 8.15 mm and 14.15 mm. There are two levels of contacts in the backplane connector. The advancing ground contacts P4 and P12 mate first with the corresponding ground pins on the device plug connector, followed by the engaging of the pre-charged power pins. An appropriate external retention mechanism independent of the connector is required to keep the host PCB and the device in place. The backplane connector is not designed with any retention mechanism. Serial ATA Revision 3.0 Gold Revision page 88 of 663 Figure 36 – Backplane connector interface dimensions 6.1.6.1 Backplane connector configuration and blind-mating tolerance Serial ATA Revision 3.0 Gold Revision page 89 of 663 The maximum blind-mate misalignment tolerances are ±1.50 mm and ±1.00 mm, respectively, for two perpendicular axes illustrated in Figure 37. Any skew angle of the plug, with respect to the receptacle, reduces the blind-mate tolerances. Figure 37 – Connector pair blind-mate misalignment tolerance The device-to-backplane mating configuration is shown in Figure 38. The allowed values for dimension A and dimension B are shown in Table 4. Serial ATA Revision 3.0 Gold Revision page 90 of 663 Table 4 – Allowed values for dimension A and B for device-to-backplane mating Description Device mated height (A) Component clearance (B) Standard 8.45 mm 3.55 mm Extended 14.45 mm 9.55 mm Figure 38 – Device-backplane mating configuration 6.1.7 Power cable receptacle connector The power cable receptacle connector mates with the power segment of the device plug, bringing power to the device. Figure 39 shows the interface dimensions of the power receptacle connector. The pinout of the connector is the mirror image of the power segment of the device plug shown in Table 3. Figure 40 defines an optional positive latch solution for internal cabled system applications. The latch requires the user to press and hold a release mechanism when disconnecting the cable. The latching feature option for device plug connectors is required in order to provide a latching surface. Without a latching surface, there is no retention feature to hold a latching cable assembly in place. It is optional to implement the latch on cable receptacles. Serial ATA Revision 3.0 Gold Revision page 91 of 663 Figure 39 – Power receptacle connector interface dimensions Serial ATA Revision 3.0 Gold Revision page 92 of 663 Figure 40 – Latching power cable receptacle The power receptacle connector is terminated onto 18 AWG wires that are connected to the system power supply or other power sources. Five 18 AWG wires may be used, with three wires terminated to the nine power pins for the three voltages, while the remaining two wires to the six ground pins. 6.1.8 Internal single lane cable The internal single lane cable consists of four conductors in two differential pairs. If necessary, the cable may also include drain wires to be terminated to the ground pins in the Serial ATA cable receptacle connectors. The conductor size may be 30 to 26 AWG. The cable maximum length is one meter. This specification does not specify a standard internal single lane cable. Any cable that meets the electrical requirements in section 6.3 is considered an acceptable internal single lane cable. The connector and cable vendors have the flexibility to choose cable constructions and termination methods based on performance and cost considerations. An example cable construction is given in Figure 41 for an informational purpose only. Although construction methodologies are not specified, there are a few essential elements of the Serial ATA cable that should be considered. Physical characteristics of the Serial ATA cable may include the following items. See Figure 41 for details. • Shielded Pairs (2) • Solid Tinned Copper (26 AWG) • White Foam Polyolefin (43.5 mil Diameter) • Parallel Drain Pairs (2 pr., 28 AWG – Solid Tinned Copper) • Aluminized Polyester Foil (1 mil thick w/35mil overlap) • Foil may be the blue longitudinal wrap that is sealed with heat • Jacket (20 mil PVC wall) Serial ATA Revision 3.0 Gold Revision page 93 of 663 115 mil 305 mil Void is Optional 46.5 mil 86.5 mil Jacket Parallel Drain Pairs 150 mil White Foam Polyolefin Solid Tinned Copper (26 AWG) Aluminized Polyester Foil Figure 41 – Detailed cross-section of an example internal single lane cable 6.1.9 Connector labeling Labeling on a connector with the connector manufacturer identifier or Serial ATA icon is optional. 6.1.10 Connector and cable assembly requirements and test procedures Unless otherwise specified, all measurements shall be performed within the following lab conditions: • Mated • Temperature: 15° to 35° C • Relative Humidity: 20% to 80% • Atmospheric Pressure: 650 mm to 800 mm of Hg If an EIA (Electronic Industry Association) test is specified without a letter suffix in the test procedures, the latest approved version of that test shall be used. 6.1.10.1 Housing and contact electrical requirements Table 5 is the connector housing and contact electrical requirements. Serial ATA Revision 3.0 Gold Revision page 94 of 663 Table 5 – Housing and contact electrical parameters, test procedures, and requirements Parameter Insulation resistance Dielectric withstanding voltage Low level contact resistance (LLCR) Contact current rating (Power segment) Procedure EIA 364-21 After 500 VDC for 1 minute, measure the insulation resistance between the adjacent contacts of mated and unmated connector assemblies. EIA 364-20 Method B Test between adjacent contacts of mated and unmated connector assemblies. EIA 364-23 Subject mated contacts assembled in housing to 20mV maximum open circuit at 100mA maximum • Mount connector to a test PCB • Wire three adjacent pins in parallel for supply (or the minimum number required by the connector type) • Wire three adjacent pins in parallel for return (or the minimum number required by the connector type) • Apply a DC current of three times the current rating per contact to the supply pins, returning through the return pins. • Record temperature rise when thermal equilibrium is reached. Requirement 1000 M minimum The dielectric shall withstand 500 VAC for 1 minute at sea level. • Initially 30 m maximum. • Resistance increase 15 m maximum after stress 1.5 A per pin minimum. The temperature rise above ambient shall not exceed 30° C at any point in the connector when contact positions are powered. The ambient condition is still air at 25° C. 6.1.10.2 Mechanical and environmental requirements Table 6 lists the mechanical parameters and requirements, while Table 7 the environmental and reliability tests and requirements: Serial ATA Revision 3.0 Gold Revision page 95 of 663 Table 6 – Mechanical test procedures and requirements Visual and dimensional inspections Cable pull-out Cable flexing EIA-364-18 Viual, dimensional and functional per applicable quality inspection plan. EIA-364-38 Condition A Subject a Serial ATA cable assembly to a 40 N axial load for a min of one minute while clamping one end of the cable plug. For round cable: EIA-364-41 Condition I Dimension x=3.7 x cable diameter, 100 cycles in each of two planes. Meets product drawing requirements No physical damage. Cable shall meet all connector and cable mechanical requirements before and after the completion of the test. No physical damage. No discontinuity over 1 us during flexing. Insertion force Cabled signal connector Removal force Cabled signal connector (Non-latching) Insertion force Cabled power connector Removal force Cabled power connector (Non-latching) Insertion force Backplane connector Removal force Backplane connector Removal force Cabled Latching connector Includes power and signal connectors Durability For flat cable: EIA-364-41 Condition II 250 cycles using either method 1 or 2. EIA-364-13 Measure the force necessary to mate the connector assemblies at a max. rate of 12.5 mm per minute. EIA-364-13 Measure the force necessary to unmate the connector assemblies at a max. rate of 12.5 mm per minute. EIA-364-13 Measure the force necessary to mate the connector assemblies at a max. rate of 12.5 mm per minute. EIA-364-13 Measure the force necessary to unmate the connector assemblies at a max. rate of 12.5 mm per minute. EIA-364-13 Measure the force necessary to mate the connector assemblies at a max. rate of 12.5 mm per minute. EIA-364-13 Measure the force necessary to unmate the connector assemblies at a max. rate of 12.5 mm per minute. EIA-364-13 Apply a static 25 N unmating test load EIA-364-09 50 cycles for internal cabled application; 500 cycles for backplane/blindmate application. Test done at a maximum rate of 200 cycles per hour. 45 N Max. 10 N Min. through 50 cycles 45 N Max. 15 N Min. for cycles 1 through 5 10 N Min. through 50 cycles 20 N Max. 4 N Min. after 500 cycles No damage No physical damage. Meet requirements of additional tests as specified in the test sequence in Table 9. Serial ATA Revision 3.0 Gold Revision page 96 of 663 Table 7 – Environmental parameters, test procedures, and requirements Parameter Physical shock Random vibration Humidity Temperature life Thermal shock Mixed Flowing Gas Procedure EIA 364-27 Condition H Subject mated connectors to 30 g’s halfsine shock pulses of 11 ms duration. Three shocks in each direction applied along three mutually perpendicular planes for a total of 18 shocks. See NOTE 2. EIA 364-28 Condition V Test letter A Subject mated connectors to 5.35 g’s RMS. 30 minutes in each of three mutually perpendicular planes. See NOTE 2. EIA 364-31 Method II Test Condition A. Subject mated connectors to 96 hours at 40° C with 90% to 95% RH. EIA 364-17 Test Condition III Method A. Subject mated connectors to temperature life at +85°C for 500 hours. EIA 364-32 Test Condition I. Subject mated connectors to 10 cycles between –55° C and +85° C. EIA 364-65, Class 2A Half of the samples are exposed unmated for seven days, then mated for remaining seven days. Other half of the samples are mated during entire testing. Requirement No discontinuities of 1 us or longer duration. No physical damage. No discontinuities of 1 us longer duration. See NOTE 1 See NOTE 1. See NOTE 1. See NOTE 1. NOTE: 1. Shall meet EIA 364-18 Visual Examination requirements, show no physical damage, and shall meet requirements of additional tests as specified in the test sequence in Table 9. 2. Shock and vibration test fixture is to be determined by each user with connector vendors. An additional requirement is listed in Table 8. Parameter Flammability Table 8 – Additional requirement Procedure UL 94V-0 Requirement Material certification or certificate of compliance required with each lot to satisfy the Underwriters Laboratories follow-up service requirements. It should be pointed out that this specification does not attempt to define the connector and cable assembly reliability requirements that are considered application-specific. It is up to users and their connector suppliers to determine if additional requirements shall be added to satisfy the application needs. For example, a user who requires a SMT connector may want to include additional requirements for SMT connector reliability. 6.1.10.3 Sample selection Serial ATA Revision 3.0 Gold Revision page 97 of 663 Samples shall be prepared in accordance with applicable manufacturers’ instructions and shall be selected at random from current production. Each test group shall provide 100 data points for a good statistical representation of the test result. For a connector with greater than 20 pins, a test group shall consist of a minimum of five connector pairs. From these connector pairs, a minimum of 20 contact pairs per mated connector shall be selected and identified. For connectors with less than 20 pins, choose the number of connectors sufficient to provide 100 data points. 6.1.10.4 Test sequence Table 9 shows the connector test sequences for five groups of tests. Table 9 – Connector test sequences Test or examination Test group A B C D E Examination of the connector(s) 1, 5 1, 9 1, 8 1, 8 1, 7 Low-Level Contact Resistance (LLCR) 2, 4 3, 7 2, 4, 6 4, 6 Insulation resistance 2, 6 Dielectric withstanding voltage 3, 7 Current rating 7 Insertion force 2 Removal force 8 Durability 3 4(1) 2(1) Physical shock 6 Vibration 5 Humidity 5 Temperature life 3 Reseating (manually unplug/plug three 5 5 times) Mixed Flowing Gas 3 Thermal shock 4 NOTE 1. Preconditioning, 20 cycles for the 50-durability cycle requirement, 50 cycles for the 500-durability cycle requirement. The insertion and removal cycle is at the maximum rate of 200 cycles per hour. For example, in Test Group A, one would perform the following tests: 1. Examination of the connector(s) 2. LLCR 3. Durability 4. LLCR 5. Examination of the connector(s) 6.1.11 Internal Multilane cables This section defines standard cable assemblies and headers for connecting multiple Serial ATA links from a RAID host bus adapter to a backplane within the same enclosure or server, or for connecting multiple Serial ATA links from a host bus adapter to individual devices. This cable/connector is based on the SFF-8484 specification. The SFF-8484 specification is also used by Serial Attached SCSI (SAS). Serial ATA Revision 3.0 Gold Revision page 98 of 663 6.1.11.1 Conformance Criteria • 2 or 4 lanes, Serial ATA signals. • Either point to point with a high density connector on both ends of the cable or fanout with a high density connector on one end of the cable assembly and individual single lane connectors on the other end of the cable assembly. • Additional pins/conductors for sideband signals. • Specifications for PCB footprint for SMT, thru hole and press fit. • RX, TX, RX, TX pin sequencing to minimize crosstalk. • Ground reference between each pair. • Flexible cable for routing and airflow. • Performance supporting 1.5 Gbps and 3.0 Gbps. • Compliance points are at the ends of a mated cable interface. If additional interconnect media between host and device exists, that portion of the design is proprietary and shall ensure the mated cable interface compliance points are met. 6.1.11.1.1 Electrical Requirements The Internal Multilane cable assembly shall meet the electrical characteristics defined in Table 18. The Internal Multilane cable assembly shall operate at Gen1i and Gen2i levels and meet the electrical characteristics defined in Table 18. Since this cable is a Multilane and therefore has multi-aggressors, the additional requirement is to have crosstalk measured using the CXT method. The measured crosstalk shall meet the requirements listed in Table 18. 6.1.11.1.2 Component Descriptions Three components are defined in this section for Multilane applications. Each component has a 2 Lane and a 4 Lane version. Pin assignments are provided at the end of this section. • Cable Receptacles and Backshells • Vertical Headers • Right Angle Headers 6.1.11.1.3 Cable Receptacles and Backshells Figure 42 and Figure 43 show isometric drawings of the internal Multilane cables and connectors. Refer to SFF-8484 for dimensions and mechanical details. Serial ATA Revision 3.0 Gold Revision page 99 of 663 Figure 42 – Isometric drawings of the internal 2 Lane cable and connector Figure 43 – Isometric drawings of the internal 4 Lane cable and connector 6.1.11.2 4 Lane Pin Assignments Serial ATA Revision 3.0 Gold Revision page 100 of 663 Note: Dashed line around Side Band lines 14 – 19 indicates shielding optional based on application and may be connected to the adjacent signal grounds. Figure 44 – 4 Lane Pin Assignments Serial ATA Revision 3.0 Gold Revision page 101 of 663 Figure 45 – 4 Lane to 4 x 1 Lanes, Fanout Implementation Serial ATA Revision 3.0 Gold Revision page 102 of 663 Note: Sideband signals not shown Figure 46 – 4 Lane Fanout Pin Assignments Serial ATA Revision 3.0 Gold Revision page 103 of 663 6.1.11.3 2 Lane Pin Assignments Figure 47 – 2 Lane Fanout Pin Assignments 6.1.12 Mini SATA Internal Multilane This section defines standard cable assemblies and headers for connecting multiple Serial ATA links from a RAID host bus adapter to a backplane within the same enclosure or server, or for connecting multiple Serial ATA links from a host bus adapter to individual devices. This cable/connector system is based on the SFF-8086 and SFF-8087 specifications. Both SFF8086 and SFF-8087 specifications are also used by Serial Attached SCSI (SAS). 6.1.12.1 Conformance Criteria Serial ATA Revision 3.0 Gold Revision page 104 of 663 • 4 lanes, Serial ATA signals. • Cable length is 1 meter maximum. • Either point to point with a high density connector on both ends of the cable or fanout with a high density connector on one end of the cable assembly and individual single lane connectors on the other end of the cable assembly. • RX, TX, RX, TX pin sequencing to minimize crosstalk. • Ground reference between each pair. • Performance supporting 1.5 Gbps, 3.0 Gbps and 6.0 Gbps. • Compliance points are at the ends of a mated cable interface. If additional interconnect media between host and device exists, that portion of the design is proprietary and shall ensure the mated cable interface compliance points are met. 6.1.12.1.1 Electrical Requirements The Mini SATA Internal Multilane cable assembly shall operate at Gen1i, Gen2i and Gen3i levels and meet the electrical characteristics defined in Table 18. Since this cable is a Multilane and therefore has multi-aggressors, the additional requirement is to have crosstalk measured using the CXT method. The measured crosstalk shall meet the requirements listed in Table 18. 6.1.12.1.2 Component Descriptions Detailed mechanical requirements are specified in SFF-8086 and SFF-8087. 6.1.12.1.3 Mechanical Requirements Figure 48 shows the isometric drawings of the Mini SATA Internal Multilane cables and connectors. Refer to SFF-8086 and SFF-8087 for dimensions and mechanical details. The Mini SATA Internal Multilane cables and connectors shall use the 36-circuit version plug and receptacle defined in SFF-8086 and SFF-8087. B18 B1 B1 B18 A1 A1 A18 A18 Figure 48 Isometric Drawings for Mini SATA Internal Multilane 6.1.12.2 Mini SATA Internal Multilane Pin Assignments The Mini SATA Internal Multilane connector pin assignments are shown in Figure 49. Serial ATA Revision 3.0 Gold Revision page 105 of 663 Pin assignments for sideband signals are based on the Internal Symmetrical Cable Assembly Implementation shown in Figure 50. For host-to-backplane applications, sideband signals on the host are attached to the corresponding sideband signals on the backplane (e.g., SB0 of the host is attached to SB0 of the backplane). For host-to-host applications, sideband signals on one host are not attached to their corresponding sideband signals on the other host (e.g., SB0 of one host is attached to SB6 of the other host). Figure 51 shows the Controller based fanout cable assembly. Figure 52 shows the Backplane based fanout cable assembly Serial ATA Revision 3.0 Gold Revision page 106 of 663 B18 B1 A1 A18 Signal SIGNAL GND RX 0+ RX 0SIGNAL GND RX 1+ RX 1SIGNAL GND SB7 (host)/SB0 (backplane) SB3 (host)/SB1 (backplane) SB4 (host)/SB2 (backplane) SB5 (host)/SB6 (backplane) SIGNAL GND RX 2+ RX 2SIGNAL GND RX 3+ RX 3SIGNAL GND SIGNAL GND TX 0+ TX 0SIGNAL GND TX 1+ TX 1SIGNAL GND SB0 (host)/SB7 (backplane) SB1 (host)/SB3 (backplane) SB2 (host)/SB4 (backplane) SB6 (host)/SB5 (backplane) SIGNAL GND TX 2+ TX 2SIGNAL GND TX 3+ TX 3SIGNAL GND Signal pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 Figure 49 Mini SATA Internal Multilane Connector Pin Assignments Serial ATA Revision 3.0 Gold Revision page 107 of 663 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 Mini SATA“ Internal Multilane cable plug connectors A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 Legend: High-Speed Serial Differential Pairs Signal Return Sideband Signal Figure 50 Mini SATA Internal Multilane System, Symmetric Cable Implementation Serial ATA Revision 3.0 Gold Revision page 108 of 663 Controller Ground B18 B18 Ground A18 A18 Host TX3 - B17 B17 Host TX3+ B16 B16 Ground B15 B15 Host RX3 - A17 A17 Host RX3+ A16 A16 Ground A15 A15 Host TX2 - B14 B14 Host TX2+ B13 B13 Ground B12 B12 Host RX2 - A14 A14 Host RX2+ A13 A13 Ground A12 A12 A11 A10 A9 A8 B11 B10 B9 B8 Ground B7 B7 Ground A7 A7 Host TX1 - B6 B6 Host TX1+ B5 B5 Ground B4 B4 Host RX1 - A6 A6 Host RX1+ A5 A5 Ground A4 A4 Host TX0 - B3 B3 Host TX0+ B2 B2 Ground B1 B1 Host RX0 - A3 A3 Host RX0+ A2 A2 Ground A1 A1 Sideband signal connection is vendor specific 1 1 Ground 2 2 Drive RX+ 3 3 Drive RX - 4 4 Ground 5 5 Drive TX - 6 6 Drive TX+ 7 7 Ground 1 1 Ground 2 2 Drive RX+ 3 3 Drive RX - 4 4 Ground 5 5 Drive TX - 6 6 Drive TX+ 7 7 Ground SATA -single lane signal cable receptacle connectors 1 1 Ground 2 2 Drive RX+ 3 3 Drive RX - 4 4 Ground 5 5 Drive TX - 6 6 Drive TX+ 7 7 Ground 1 1 Ground 2 2 Drive RX+ 3 3 Drive RX - 4 4 Ground 5 5 Drive TX - 6 6 Drive TX+ 7 7 Ground Note: The cable assembly shall connect each signal return on one end to at least one signal return on the other end. The cable assembly may connect one or more of the signal returns together. Figure 51 Mini SATA Internal Multilane System, Controller based fanout cable implementation Serial ATA Revision 3.0 Gold Revision page 109 of 663 Ground 7 7 Host RX+ 6 6 Host RX- 5 5 Ground 4 4 Host TX- 3 3 Host TX+ 2 2 Ground 1 1 Ground 7 7 Host RX+ 6 6 Host RX- 5 5 Ground 4 4 Host TX- 3 3 Host TX+ 2 2 Ground 1 1 SATA single lane signal cable receptacle connectors Ground 7 7 Host RX+ 6 6 Host RX- 5 5 Ground 4 4 Host TX- 3 3 Host TX+ 2 2 Ground 1 1 Ground 7 7 Host RX+ 6 6 Host RX- 5 5 Ground 4 4 Host TX- 3 3 Host TX+ 2 2 Ground 1 1 Sideband signal connection is vendor specific Backplane B18 B18 Ground A18 A18 Ground B17 B17 Backplane TX3- B16 B16 Backplane TX3+ B15 B15 Ground A17 A17 Backplane RX3- A16 A16 Backplane RX3+ A15 A15 Ground B14 B14 Backplane TX2- B13 B13 Backplane TX2+ B12 B12 Ground A14 A14 Backplane RX2- A13 A13 Backplane RX2+ A12 A12 Ground A11 A10 A9 A8 B11 B10 B9 B8 B7 B7 Ground A7 A7 Ground B6 B6 Backplane TX1- B5 B5 Backplane TX1+ B4 B4 Ground A6 A6 Backplane RX1- A5 A5 Backplane RX1+ A4 A4 Ground B3 B3 Backplane TX0- B2 B2 Backplane TX0+ B1 B1 Ground A3 A3 Backplane RX0- A2 A2 Backplane RX0+ A1 A1 Ground Note: The cable assembly shall connect each signal return on one end to at least one signal return on the other end. The cable assembly may connect one or more of the signal returns together. Figure 52 Mini SATA Internal Multilane System, Backplane based fanout cable implementation Serial ATA Revision 3.0 Gold Revision page 110 of 663 6.2 Internal Micro SATA Connector for 1.8” HDD This section provides capabilities required to enable a smaller Serial ATA 1.8” HDD (hard disk drive). The definition supports the following capabilities: • Supports Gen1 (1.5 Gbps) and Gen2 (3.0 Gbps) transfer rates • Support for backplane (direct connect) and cable attachment usage models • Support for hot plug in backplane (non-cabled) applications • Support for 8.0 and 5.0 mm slim 1.8” form factor HDDs • Support of 3.3 V with 5 V to meet future product requirements • Support optional pins, P8 and P9 for vendor specific use 6.2.1 Usage model The internal micro SATA connector may be used for the mobile usage model defined in section 5.2.10 The definition only supports internal 8.0 mm and 5.0 mm slim 1.8” form factor HDDs. 6.2.2 General description The internal micro SATA connector is designed to enable connection of a slim 1.8” form factor HDD to the Serial ATA interface. The internal micro Serial ATA connector uses the 1.27 mm pitch configuration for both the signal and power segments. The signal segment has the same configuration as the internal standard Serial ATA connector. The power segment provides the present voltage requirement support of 3.3 V, and includes a provision for a future voltage requirement of 5 V. In addition, there is a reserved pin, P7. Finally, there are two optional pins, P8 and P9, for vendor specific use. The internal micro SATA connector is designed with staggered pins, for hot plug backplane (noncabled) applications. A special power segment key is located between pins P7 and P8. This feature prevents insertion of other Serial ATA cables. Care should be taken in the application of this device so that excessive stress is not exerted on the device or connector. Backplane configurations should pay particular attention so that the device and connector are not damaged due to excessive misalignment. 6.2.3 Connector location The internal micro SATA connector location on the HDD is shown in Figure 53 and Figure 54 for reference purposes. See SFF-8144 for form factor definition and connector location. Serial ATA Revision 3.0 Gold Revision page 111 of 663 Figure 53 Device internal micro SATA connector location for 1.8” HDD Serial ATA Revision 3.0 Gold Revision page 112 of 663 Figure 54 Device internal micro SATA connector location for 1.8” HDD Serial ATA Revision 3.0 Gold Revision page 113 of 663 6.2.4 Mating interfaces 6.2.4.1 Device internal micro SATA plug connector Figure 55 defines the interface dimensions for the internal micro SATA device plug connector with both signal and power segments. Serial ATA Revision 3.0 Gold Revision page 114 of 663 Serial ATA Revision 3.0 Gold Revision page 115 of 663 Figure 55 Device internal micro SATA plug connector 6.2.4.2 Internal micro SATA backplane connector Figure 56 defines the interface dimensions for the internal micro SATA backplane connector. Figure 56 Internal micro SATA backplane connector Serial ATA Revision 3.0 Gold Revision page 116 of 663 6.2.4.3 Internal micro SATA power receptacle connector Figure 57 defines the interface dimensions for the internal micro SATA power receptacle connector. Figure 57 Internal micro SATA power receptable connector 6.2.4.4 Internal micro SATA connector pair blind-mate misalignment capability Serial ATA Revision 3.0 Gold Revision page 117 of 663 The maximum blind-mate misalignment capabilities are ±1.50 mm and ±1.00 mm, respectively, for two perpendicular axes illustrated in Figure 58. Any skew angle of the plug, with respect to the receptacle, reduces the blind-mate capabilities. Figure 58 Internal micro SATA connector pair blind-mate misalignment capability 6.2.4.5 Internal micro SATA pin signal definition and contact mating sequence Serial ATA Revision 3.0 Gold Revision page 118 of 663 Signal Segment Table 10 details the pin names, types and contact order of the two internal micro SATA Plug options. A brief description is also included for signal, ground and power pins. There are total of 7 pins in the signal segment and 9 pins in the power segment. Table 10 – Signal and Power Internal Micro SATA Plug and Nominal Mate Sequence Name Type Description Cable Usage1,2 Backplane Usage2 Refer to Table 3. Spacing separate signal and power segments3 Power Segment P1 V33 3.3 V Power P2 V33 3.3 V Power, Pre-charge P3 GND P4 GND P5 V5 5 V Power, Pre-charge4 P6 V5 5 V Power4 P7 R Reserved5 2nd Mate 1st Mate 1st Mate 1st Mate 1st Mate 2nd Mate 2nd Mate 3rd Mate 2nd Mate 1st Mate 1st Mate 2nd Mate 3rd Mate 3rd Mate Key Key Key P8 Optional Vendor specific6 NC 2nd Mate NC 3rd Mate P9 Optional Vendor specific6 2nd Mate 3rd Mate NOTE: 1. Although the mate order is shown, hot plugging is not supported when using the cable connector receptacle. 2. All mate sequences assume zero angular offset between connectors. 3. The signal segment and power segment may be separate. 4. The 5 V supply voltage pins are included to meet future product requirements and may optionally be provided on the power segment receptacle. Future revisions of this specification may require 5 V supply voltage be provided. 5. The corresponding pin to be mated with pin P7 in the power Internal Micro receptacle connector shall always be grounded. 6. No connect on the host side. 6.2.4.6 Internal micro SATA connector and cable assembly requirements and test procedures The internal micro SATA connector and cable shall meet the requirements as defined for standard internal SATA cables and connectors in section 6.1.10, with the exceptions listed in Table 11. Table 11 – Unique Connector Mechanical Testing Procedures and Requirements Removal force EIA-364-13 2.5 N Min. after 500 cycles Serial ATA Revision 3.0 Gold Revision page 119 of 663 Backplane connector Insertion force Cabled power connector (non-latching) Removal force Cabled power connector (non-latching) Measure the force necessary to unmate the connector assemblies at a max. rate of 12.5 mm per minute. EIA-364-13 Measure the force necessary to mate the connector assemblies at a max. rate of 12.5 mm per minute. EIA-364-13 Measure the force necessary to unmate the connector assemblies at a max. rate of 12.5 mm per minute. 45 N Max. 10 N Min. for cycles 1 through 5 8 N Min. through 50 cycles 6.3 Internal Slimline cables and connectors This section provides capabilities required to enable Serial ATA in “Slimline” optical disk drives. The definition supports the following capabilities: • Supports Gen1 (1.5 Gbps) and Gen2 (3.0 Gbps) transfer rates • Support for backplane (direct connect) and cable attachment usage models • Support for warm plug • Support for 12.7 mm, 9.5 mm and 7.0 mm Slimline devices • 5 V only power delivery The definition has the following constraints: • No device activity signal support • Analog audio is not supported • External cable and connector are not supported • No hot plug support • Warm plug support is usage model dependent 6.3.1 Usage Models Support for three usage models. Internal fixed bay (direct attach), removable bay, and internal cable. The requirements for each usage model are specified in this section. Internal Fixed Bay requirements: • Support for 12.7, 9.5 and 7.0 mm slimline devices • Direct attach support for 1.8” HDD not required • Direct attach support for 2.5” HDD not required • Minimum footprint • Device presence detection not required Removable Bay requirements: • Support for 12.7 mm, 9.5 mm and 7.0 mm slimline devices • Direct attach support for 1.8” HDD not required • Direct attach support for 2.5” HDD not required. Attachment in carrier adapter shall conform to cabled usage model for Gen1i, Gen2i and Gen3i. • Warm plug and blind mate required • Un-powered device presence detection required • No floppy support required Serial ATA Revision 3.0 Gold Revision page 120 of 663 • No battery connector support required • Support 500 insertions and removals. Design is scaleable to higher cycle counts. Internal Cable requirements: • Support for 12.7 mm, 9.5 mm and 7.0 mm slimline devices • Direct attach support for 1.8” HDD not required • Direct attach support for 2.5” HDD not required • Blind mate not supported • Device presence detection not supported • Support passive and latching retention mechanisms • Support internal single lane cables and connectors, defined in section 6.1 • Support 50 insertions and removals 6.3.2 General description The Slimline connector is designed to enable connection of a “slimline” form factor drivedevice to the Serial ATA interface. The connector design accommodates a latching option for 9.5 mm and 12.7 mm slimline devices. A latching option may not be accommodated in 7 mm slimline devices. This internal Serial ATA connector uses the 5 mm (ref) connector height as low profile. The connector is designed to fit into the presently used PATA (Parallel ATA) connector slimline designs with almost no changes to the slimline device case, media tray, or internal mechanics. It is anticipated that a simple replacement of the PATA PC board with a SATA controller and connector in the present slimline device designs may be possible. The connector preserves the design of the signal portion of the present SATA connector and accommodates presently available SATA signal cables. The power portion of the connector was reduced to six pins. Both +12 V and +3.3V were removed from the connector leaving +5 V as the sole supply voltage. The standard +A, -A, +B, and –B signals are on the signal portion of the connector. In addition to +5 V and GND, the following signals were added to the power portion: • DP – Device Present – Active low signal indicating device connect to the host. The device shall connect the DP pin to ground with a resistance of 1K ohms and a maximum tolerance of ± 10% ohms. This signal is not supported in a cabled environment. If a cabled connection is used and the cable is held in a fixed position, the cable shall follow backplane requirements. Host connection to the DP pin is optional. If un-used, no connection is allowed. If the host requires the use of the DP function, the maximum current it shall source is 4mA and the minimum is 0 mA. • MD – Manufacturing Diagnostic – Signal pin used by device vendors during device testing. No host connection is allowed, device connection is optional. 6.3.3 Connector location and keep out zones This section describes the location of the connector in the slimline device referenced from the standard locations. Keep out zones are also defined to allow blind mate capability. 6.3.3.1 Location Table 12 shows the connector location references for the 7.0 mm, 9.5 mm and 12.7 mm slimline devices. Serial ATA Revision 3.0 Gold Revision page 121 of 663 Table 12 – Slimline Connector Location References Slimline Drive 7.0 mm Slimline 9.5 mm Slimline 12.7 mm Slimline Horizontal Drive left edge to connector CL Drive left edge to connector CL Drive left edge to connector CL Vertical Drive bottom edge to connector tongue top edge Drive bottom edge to connector tongue top edge Drive bottom edge to connector tongue top edge Depth Drive back edge to connector back wall Drive back edge to connector back wall Drive back edge to connector back wall 6.3.3.2 Keep out zones The minimum panel opening is the maximum connector size plus the positional tolerance of the connector location within the slimline device. The internal SATA connector location on the 7 mm slimline ODD is shown in Figure 59 for reference purposes only. Additional details may be found in SFF-8553. Figure 59 - 7.0 mm Slimline Drive Connector Locations Serial ATA Revision 3.0 Gold Revision page 122 of 663 -G- 128 REF B OF CONNECTOR DATUM -B- 0.6 X G 0.4 X A -C- A -X- 28.7 REF KEEP OUT ZONE B 5.4 REF 9.5 REF / 12.7 REF 20.4 REF 0.76 X -B- 21.25 -Z- 5.2 -X- SECTION B-B Figure 60 - 9.5 mm/12.7 mm Slimline Drive Connector Locations Serial ATA Revision 3.0 Gold Revision page 123 of 663 7.0 mm Slimline Devices Figure 61 - 7.0 mm Slimline Drive Connector Location (Section A-A) 6.3.3.2.1 9.5 mm Slimline Drives -Z- 0.4 Z -A- 6±0.38 0.3 REF 9.5 REF Figure 62 - 9.5 mm Slimline Drive Connector Location (Section A-A) 6.3.3.2.2 12.7 mm Slimline Drives Serial ATA Revision 3.0 Gold Revision page 124 of 663 -Z- 0.4 Z -A- 6.2±0.38 0.3 REF 12.7 REF Figure 63 - 12.7 mm Slimline Drive Connector Location (Section A-A) 6.3.4 Mating interfaces Serial ATA connectors are defined in terms of their mating interface or front end characteristics only. Connector back end characteristics including PCB mounting features and cable termination features are not defined. Certain informative dimensions may be defined to indicate specific assumptions made in the design to meet certain requirements of form, fit, and function. Serial ATA Revision 3.0 Gold Revision page 125 of 663 6.3.4.1 7 mm Slimline Device plug connector This is the connector used in the 7 mm slimline device. Figure 2 and Table 1 show the interface dimensions for the device plug connector with both signal and power segments. General tolerances on these drawings are +/-0.20 mm. Figure 64 – 7 mm slimline device plug connector interface dimensions Serial ATA Revision 3.0 Gold Revision page 126 of 663 Figure 65 - 7.0 mm Slimline device plug connector interface dimensions Section A-A Figure 66 - 7.0 mm Slimline device plug connector interface dimensions Section B-B Figure 67 - 7.0 mm Slimline device plug connector interface dimensions detail D Figure 68 - 7.0 mm Slimline device plug connector interface dimensions optional hold down mounting 6.3.4.1.1 Connector pin signal definition Refer to Table 13 for connector pin assignment and description. 6.3.4.1.2 Housing and contact electrical and mechanical requirement Serial ATA Revision 3.0 Gold Revision page 127 of 663 The internal SATA connector and cable shall meet the requirements as defined for standard internal SATA cables and connectors in 6.1.10.1. 6.3.4.1.3 Connector and cable assembly requirements and test procedure The connector and cable assembly requirements and test procedure shall confirm to those in 6.3.7. Serial ATA Revision 3.0 Gold Revision page 128 of 663 6.3.4.2 9.5 mm and 12.7 mm Slimline Device plug connector This is the connector used in the slimline device. Figure 69 and Table 13 show the interface dimensions for the device plug connector with both signal and power segments. General tolerances on these drawings is +/-0.20 mm. Figure 69 – Slimline Device plug connector interface dimensions Serial ATA Revision 3.0 Gold Revision page 129 of 663 0.35±0.05 -A- 1.58±0.08 45° 1.95±0.08 R0.25±0.08 TOTAL 10 PLC AROUND 1.23±0.05 3.1±0.08 BASE OF "L"-SHAPED TONGUES, EXCEPT ON SURFACE WITH CONTACTS Figure 70 - Slimline Device plug connector interface dimensions (Section A-A) 30° 2 PLC 1.25 MIN OF -B- 3.7 MAX 2 PLC 7.5 MIN 2 PLC Figure 71 - Slimline Device plug connector interface dimensions (Section B-B) 1.0mm MIN KEEP OUT ZONE 0.3±0.05 X 45° ALL AROUND 4.25±0.05 0.35 MIN 6.375 5.57 Figure 74 - Slimline Device plug connector interface dimensions (Section G-G) 32.7 REF HOLD DOWN (OPTIONAL) R0.35±0.08 Figure 72 - Slimline Device plug connector interface dimensions (Section C-C) 0.3±0.08 30° 30° Figure 75 – Slimline Device Plug Connector Optional Hold Down Mounting Figure 73 - Slimline Device plug connector interface dimensions (Detail F) Serial ATA Revision 3.0 Gold Revision page 130 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization There are total of 7 pins in the signal segment and 6 pins in the power segment. The pin definitions are shown in Table 13. Note that the pin is numbered from the pin furthest from the power segment. Table 13 – Slimline Device plug connector pin definition Name Type Description Cable Usage Backplane Usage Signal Segment Refer to Table 3. Signal Segment “L” Central Connector Gap Power Segment Power Segment “L” P1 DP Device Present P2 +5 V P3 +5 V P4 MD Manufacturing Diagnostic P5 Gnd P6 Gnd 3rd mate 2nd mate 2nd mate 2nd mate 1st mate 1st mate 3rd mate 2nd mate 2nd mate 2nd mate 1st mate 1st mate Power Segment Key NOTE: 1. All pins are in a single row with 1.00 mm (.039”) pitch on the power segment portion. 2. Ground pins in the Serial ATA slimline device plug power segment (connector pins P5 and P6) shall be bussed together on the Serial ATA slimline device. 3. The connection between the Serial ATA slimline device signal ground and power ground is vendor specific. 4. The DP and MD signals shall be referenced to the power portion ground pins, P5 and P6. 5. The 5 V power delivery pins in the Serial ATA slimline device plug power segment (connector pins P2 and P3) shall be bussed together in the Serial ATA slimline device. Serial ATA Revision 3.0 Gold Revision page 131 of 663 POWER SEGMENT KEY POWER SEGMENT PIN P1 SIGNAL SEGMENT KEY SIGNAL SEGMENT PIN S1 PCB MOUNTING SIDE Figure 76 – Slimline Connector Pin and Feature Locations 6.3.4.2.1 Slimline Signal cable receptacle connector The standard SATA signal cable receptacle is used. See section 6.1.4. 6.3.4.2.2 Slimline Power cable receptacle connector The slimline power cable receptacle connector mates with the power segment of the device plug, bringing power to the device. Figure 77 shows the interface dimensions of the power receptacle connector. The pin out of the connector is the mirror image of the power segment of the device plug shown in Table 13. The MD and DP connector pins are optionally present in a cabled environment. Serial ATA Revision 3.0 Gold Revision page 132 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Figure 77 – Slimline Power receptacle connector interface dimensions Serial ATA Revision 3.0 Gold Revision page 133 of 663 Figure 78 – Slimline Power receptacle connector Option with Latch Figure 79 – Slimline Power receptacle connector Option with Bump Serial ATA Revision 3.0 Gold Revision page 134 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 6.3.4.3 Slimline Host Receptacle Connector The slimline host receptacle connector is to be blind-mated directly with the device plug connector. The interface dimensions for the host receptacle connector are shown in Figure 80. An appropriate external retention mechanism independent of the connector is required to keep the host PCB and the device in place. The slimline host receptacle connector is not designed with any retention mechanism. Figure 80 – Slimline Host receptacle connector interface dimensions Serial ATA Revision 3.0 Gold Revision page 135 of 663 0.92±0.08 1.5±0.08 34.8° REF 39.6° REF 1.2±0.05 Figure 81 – Slimline Host receptacle connector interface dimensions Section C-C 5.2±0.15 0.3±0.05 X 45° 1.4±0.15 PINS S1 THRU S7 1.4±0.08 2.4±0.08 Figure 82 – Slimline Host receptacle connector interface dimensions Section X-X 1.9±0.15 PIN P1 ONLY 1.4±0.15 PINS P2 THRU P6 Figure 83 – Slimline Host receptacle connector interface dimensions Section Y-Y 6.3.5 Backplane connector configuration and blind-mating tolerance The maximum blind-mate misalignment tolerances are ±1.50 mm and ±1.20 mm, respectively, for two perpendicular axes illustrated in Figure 84. Any skew angle of the plug, with respect to the receptacle, reduces the blind-mate tolerances. Serial ATA Revision 3.0 Gold Revision page 136 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization OF RECEPTACLE OF RECEPTACLE 1.2 MAX G 1.5 MAX G OF PLUG SECTION G-G OF PLUG 1.63° MAX Figure 84 – Slimline Connector pair blind-mate misalignment tolerance 6.3.6 Connector labeling Refer to section 6.1.9. 6.3.7 Connector and cable assembly requirements and test procedures The connector and cable assembly requirements and test procedures shall conform to those in Table 6 with the following exceptions. Serial ATA Revision 3.0 Gold Revision page 137 of 663 Table 14 – Slimline Connector Mechanical Test Procedures And Requirements Removal force Backplane connector Insertion force Cabled power connector Without latch Removal force Cabled power connector Without latch Insertion force Cabled power connector With latch Removal force Cabled power connector With latch EIA-364-13 Measure the force necessary to unmate the connector assemblies at a max. rate of 12.5 mm per minute. EIA-364-13 Measure the force necessary to mate the connector assemblies at a max. rate of 12.5 mm per minute. EIA-364-13 Measure the force necessary to unmate the connector assemblies at a max. rate of 12.5 mm per minute. EIA-364-13 Measure the force necessary to mate the connector assemblies at a max. rate of 12.5 mm per minute. EIA-364-13 Apply a static 25 N unmating test load 2.5 N Min. after 500 cycles 45 N Max. 10 N Min. for cycles 1 through 5 8 N Min. through 50 cycles 45 N Max. No damage and no disconnect through 50 mating cycles 6.4 Internal LIF-SATA Connector for 1.8” HDD This section provides capabilities required to enable a new smaller Serial ATA 1.8” HDD (hard disk drive). The definition supports the following capabilities: • Supports Gen1 (1.5 Gbps) and Gen2 (3 Gbps) transfer rates • Support for FPC usage models • Support for 8.0 and 5.0 mm slim 1.8” Form Factor (FF) HDD’s • Support of 3.3 V with 5 V to meet future product requirements • Support vendor pins, P18,19,20 and 21 reserved for HDD customer usage • Support vendor pins, P22 and P23 for HDD manufacturing usage This LIF-SATA is only for internal 8.0 mm and 5.0 mm slim 1.8” form factor devices. NOTE: It is expected that the LIF-SATA interfaces comply with Gen1i and Gen2i specifications. The LIF-SATA connector can only be mated with FPC cable, the compliance point shall be after the mated assembly, where the necessary Tx and Rx measurements were measured. 6.4.1 General description This internal LIF-SATA connector is designed to enable connection of a new family of slim 1.8” form factor HDD’s to the Serial ATA interface. The internal LIF Serial ATA connector uses the 0.5 mm pitch configuration for both the signal and power segments. The signal segment has the same configuration as the internal standard Serial ATA connector but power segment provides the present voltage requirement support of 3.3 V, and provision for a future voltage requirement of 5 V. In addition, there is P8 that is defined as Device Activity Signal/Disable Staggered Spin up. Finally, there are 6 vendor pins, P18, 19, 20 and 21 for HDD customer usage, and P22 and P23 for HDD manufacturing usage. Serial ATA Revision 3.0 Gold Revision page 138 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Care must be taken in the application of this drive so that excessive stress is not exerted on the drive or connector. 6.4.2 Connector Locations 6.4.2.1 Connector location on Hard Disk Drive (HDD) Form Factor, - (Reference) The internal LIF-SATA connector location on the HDD is shown in Figure 85 for reference purposes only. See SFF-8146 for form factor definition and connector location. Figure 85 - Internal LIF-SATA connector location for 1.8” HDD 6.4.2.2 Connector location on Solid State Drive (SSD) Form Factor, - (Reference) Serial ATA Revision 3.0 Gold Revision page 139 of 663 The internal LIF-SATA connector location on SSD Bulk Type is shown in Figure 86 for reference purposes only. Figure 86 - Internal LIF-SATA connector location for 1.8” SSD bulk of single-sided mount type Serial ATA Revision 3.0 Gold Revision page 140 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 6.4.3 Mating interfaces 6.4.3.1 Device internal LIF-SATA embedded type connector Figure 87 defines the interface dimensions for the internal LIF-SATA embedded type connector with both signal and power segments. Serial ATA Revision 3.0 Gold Revision page 141 of 663 Recommended PCB layout. Figure 87 - Device internal LIF SATA embedded type connector Serial ATA Revision 3.0 Gold Revision page 142 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 6.4.3.2 Device internal LIF-SATA surface mounting type connector Figure 88 defines the interface dimensions for the internal LIF-SATA device surface mounting type connector. Recommended PCB layout. Figure 88 - Device internal LIF-SATA surface mounting type connector 6.4.3.3 FPC for Internal LIF-SATA Serial ATA Revision 3.0 Gold Revision page 143 of 663 Figure 89 defines the interface dimensions for the FPC of LIF-SATA. Figure 89 - FPC for Internal LIF SATA Serial ATA Revision 3.0 Gold Revision page 144 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 6.4.4 Internal LIF-SATA pin signal definition and contact mating sequence Table 15 details the pin names, types and contact order of the two internal LIF-SATA plug options. A brief description is also included for signal, ground and power pins. There are total 24 pins. Table 15 - Signal and Power Internal LIF-SATA Plug Name Type Description P1 GND P2 V33 P3 V33 P4 GND 3.3 V Power 3.3 V Power P5 V5 P6 V5 5 V Power 5 V Power1 P7 GND P8 DAS/DSS Device Activity Signal/Disable Staggered Spinup2 P9 GND P10 GND P11 A+ P12 A- Differential Signal Pair A P13 GND P14 B- P15 B+ Differential Signal Pair B P16 GND P17 GND P18 Vendor Vendor Specific P19 Vendor Vendor Specific P20 Vendor Vendor Specific P21 Vendor P22 Vendor P23 Vendor Vendor Specific Vendor Specific - Mfg pin3 Vendor Specific - Mfg pin3 P24 GND NOTE: 1. The 5 V supply voltage pins are included to meet future product requirements. Future revisions of this specification may require 5 V supply voltage be provided. 2. The corresponding pin to be mated with Pin8 shall always be grounded. For specific optional usage of Pin8 see section 6.4 Serial ATA Revision 3.0 spec. 3. No connect on the host side. Serial ATA Revision 3.0 Gold Revision page 145 of 663 6.4.5 Housing and contact electrical requirement The internal LIF-SATA connector and cable shall meet the requirements as defined for standard internal SATA cables and connectors in 6.1.10 of Serial ATA Revision 3.0, Connector and FPC assembly requirements and test procedures, with the exceptions listed below in Table 16. Table 16 - Unique Connector Mechanical Testing Procedures and Requirements Insertion force for FPC Removal force for FPC Durability Minimum current Measure the force necessary to mate the connector assemblies at a max. rate of 12.5 mm per minute. Measure the force necessary to unmate the connector assemblies at a max. rate of 12.5 mm per minute. 10 cycles for internal cabled application; Test done at a maximum rate of 200 cycles per hour. • Mount the connector to a test PCB • Wire power pins P2, P3, P5, P6 in parallel for power • Wire ground pins P1, P4, P7, P9, P10, P13, P16, P17, P24 in parallel for return • Supply 2A total DC current to the power pins in parallel, returning from the parallel ground pins • Record temperature rise when thermal equilibrium is reached 6 N Max. 6 N Min. through 10 cycles No physical damage. 0.5 A per pin minimum. The temperature rise above ambient shall not exceed 30° C at any point in the connector when contact positions are powered. The ambient condition is still air at 25° C. Serial ATA Revision 3.0 Gold Revision page 146 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 6.5 External cables and connectors 6.5.1 External Single Lane The External Single Lane system provides a single lane connection between a PC/Laptop and a commodity storage device using Gen1i/Gen2i Serial ATA devices. This interface is for the use of an external device that resides outside the PC chassis, similar to USB or 1394 hard drives and optical drives. While this does not exclude other usages, the requirements are derived based on this usage model. Power is supplied to the external storage device via a separate means, which is outside the scope of this specification. This separate means is expected to be similar to power delivery for USB or 1394 external drives. This section defines the external interconnect, compliance points, and associated electrical requirements/parameters for device interoperability. The primary implementation is: • An HBA connected to a shielded external connector. A buffer IC is required to interface to a Gen1i/Gen2i Serial ATA host unless the Serial ATA host is Gen1m/Gen2m compliant and designed for direct external connection. • A shielded Serial ATA cable designed for external usage. • A Serial ATA device enclosure with a corresponding external connector. A buffer IC is required to interface to a Gen1i/Gen2i Serial ATA device unless the Serial ATA device is Gen1m/Gen2m compliant and designed for direct external connection. This implementation is shown in Figure 90. Serial ATA Revision 3.0 Gold Revision page 147 of 663 Figure 90 – Usage Model for HBA with external cable and single device enclosure A second potential implementation is a Serial ATA host directly assembled on the motherboard connected to a shielded external connector via a pigtail to the motherboard connection. In this implementation, the external Serial ATA cable and the device assembly are similar to Figure 131, but another cable and connector pair between the motherboard and the external cable is introduced, placing an additional discontinuity point between host and device. There are two compliance points for the External Single Lane system, one at each shielded external connector. As with other cable and connector system descriptions, interconnect between the IC/Phy and the connectors at the mating interface are outside the scope of the definition and are considered part of the delivered Phy solution. Implementations that have additional connections between the Phy/IC and the shielded external connector shall provide such interconnects as part of the engineered solution. For an implementation such as shown in Figure 91, the compliance points remain at the shielded external connectors. Serial ATA Revision 3.0 Gold Revision page 148 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Figure 91 – Usage Model for on-Board Serial ATA Connector with extension cable to external cable to disk The typical cable length is two meters (six feet); long enough to reach from a floor mounted PC to a device placed on the desktop. The compliance points for both ends of the external cable shall meet the Gen2m electrical specification. The use of a standard internal Serial ATA host or device not specifically designed for direct external connection requires a buffer IC as part of the implementation. Note that since Single Lane External Serial ATA cables are a straight through design, (pin to pin), the host and device external connections, using the same external connector, have the same pin one locations but opposite signal definitions. Refer to Table 3 for both host and device connection signal assignments. 6.5.1.1 External Serial ATA Component General Descriptions Five components are defined in this section to support external Serial ATA. • A shielded external cable receptacle for use with shielded (external Serial ATA) cabling. • A fully shielded RA PCB mounted SMT plug, (and reversed pin-out version). • A fully shielded RA PCB mounted through-hole plug. • A fully shielded vertical PCB mounted SMT plug. • A fully shielded vertical PCB mounted through-hole plug. Serial ATA Revision 3.0 Gold Revision page 149 of 663 Footprints and recommended panel cutouts are included to encourage greater interoperability from multiple vendors. The external cable connector is a shielded version of the internal single lane connector defined in section 6, with these basic differences: • The External connector has no “L” shaped feature, and the guide features are vertically offset and reduced in size. This prevents the use of unshielded internal cables in external applications. • To prevent ESD damage, the insertion depth is increased from 5 mm to 6.6 mm and the contacts are mounted further back in both the receptacle and plug. • The retention features are springs built into the shield on both the top and bottom surfaces. External Serial ATA Connector renderings: Figure 92 – Renderings of External Serial ATA cable receptacle and right angle plug 6.5.1.1.1 External Serial ATA Connector Mechanical drawings Serial ATA Revision 3.0 Gold Revision page 150 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Figure 93 – Mechanical dimensions of External Serial ATA cable receptacle assembly Serial ATA Revision 3.0 Gold Revision page 151 of 663 Figure 94 – Mechanical dimensions of External Serial ATA RA SMT plug Serial ATA Revision 3.0 Gold Revision page 152 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Figure 95 – Mechanical dimensions of External SATA RA SMT plug – Reversed Pin Out Serial ATA Revision 3.0 Gold Revision page 153 of 663 Figure 96 – Mechanical dimensions of External Serial ATA RA Through-hole Serial ATA Revision 3.0 Gold Revision page 154 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Figure 97 – Mechanical dimensions of External Serial ATA Vertical SMT plug Serial ATA Revision 3.0 Gold Revision page 155 of 663 Figure 98 – Mechanical dimensions of External Serial ATA Vertical Through-hole plug Serial ATA Revision 3.0 Gold Revision page 156 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 6.5.1.2 External Serial ATA Electrical Requirements The external cable assembly shall meet the electrical characteristics defined in Table 19. The Single Lane External Serial ATA Data Interface Phy electrical performance shall comply with the following: • Electrical characteristics defined in Table 19, Gen1m and/or Gen2m at the shielded external connector compliance points. • Support hot plugging and non-powered device attachment. • AC coupling is required at the device interface and recommended at the host interface. 6.5.1.3 External Serial ATA Mechanical Requirements The external connector mechanical performance specifications shall be consistent with the internal single lane connector specifications in section 6.5.1, with the following exceptions: • Durability shall be 2500 cycles with no exposure of the base metal of the signal contacts. • Insertion force shall be a maximum of 40 N. • Removal force shall be a minimum of 10 N at the conclusion of the durability test. 6.5.1.4 External Serial ATA Device Direct Connection Requirements Serial ATA devices may have data interfaces specifically designed for direct connection in the Single Lane External Serial ATA environment without requiring a buffer IC. The data interface of the Single Lane External Serial ATA device shall comply with all external Serial ATA mechanical requirements of section 6.5.1.3. The Phy electrical performance shall comply with the following: • Electrical characteristics defined in section 6.6, Gen1m and/or Gen2m at the shielded external connector compliance points. • Support hot plugging and non-powered device attachment. • AC coupling is required at the device interface and recommended at the host interface. 6.5.2 External Multilane This section defines standard cable assemblies and headers for connecting multiple Serial ATA channels from a RAID host bus adapter to an intelligent backplane in an adjacent JBOD (just a bunch of disks) unit. The RAID HBA and the JBOD units are envisioned as using different power supplies. This cable/connector set is based on the SFF-8470 specification. The SFF-8470 specification also describes the cable/connector set used by Serial Attached SCSI (SAS). 6.5.2.1 Multilane Cable Conformance Criteria The External Multilane cable/connector shall be used with Gen1m/Gen2m and Gen1x/Gen2x signal levels only. If Gen1m/Gen2m signal levels are used, the cable length is limited to two meters. If Gen1x/Gen2x signal levels are used, cable lengths up to and greater than two meters are supported. 6.5.2.1.1 Electrical Parameters The External Multilane cable assembly operating at Gen1m and Gen2m levels shall meet the electrical characteristics defined in Table 20. The External Multilane cable assembly operating at Gen1x and Gen2x levels shall meet the electrical characteristics defined in Table 21. Serial ATA Revision 3.0 Gold Revision page 157 of 663 6.5.2.1.2 Mechanical Parameters Detailed mechanical requirements are specified in SFF-8470, reference type 4X with thumbscrews. The PCI add-in card form factor supports two 4X interfaces. Figure 99 –External Multilane cable and connector 6.5.2.2 Keying Requirements The Serial ATA External Multilane cable/connector may include keying features, a variant from the SFF-8470. The Serial ATA key locations are shown in Figure 100. Optional keying allows connection between Serial ATA HBAs and JBODs but disallows connection to SAS HBAs or JBODs if the SAS units do not have connectors with key slots. If present, the External Multilane cable connector blocking key locations shall be 3, 4 and 5 and the corresponding mating connector blocking key locations shall be 1, 2, and 6. Serial ATA Revision 3.0 Gold Revision page 158 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Figure 100 – Multilane Cable Connector Blocking Key Locations Serial ATA Revision 3.0 Gold Revision page 159 of 663 Figure 101 – Plug/Receptacle Keying Serial ATA Revision 3.0 Gold Revision page 160 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 6.5.2.3 4 Lane Pin Assignments Table 17 – Multilane Pin Assignments Signal Signal pin to use based on number of physical links supported by the cable One Two Three Four Rx 0+ S1 S1 S1 S1 Rx 0- S2 S2 S2 S2 Rx 1+ N/C S3 S3 S3 Rx 1- N/C S4 S4 S4 Rx 2+ N/C N/C S5 S5 Rx 2- N/C N/C S6 S6 Rx 3+ N/C N/C N/C S7 Rx 3- N/C N/C N/C S8 Tx 3- N/C N/C N/C S9 Tx 3+ N/C N/C N/C S10 Tx 2- N/C N/C S11 S11 Tx 2+ N/C N/C S12 S12 Tx 1- N/C S13 S13 S13 Tx 1+ N/C S14 S14 S14 Tx 0- S15 S15 S15 S15 Tx 0+ S16 S16 S16 S16 SIGNAL GROUND G1-G9 CHASSIS GROUND Housing Note: N/C: Not connected 6.5.3 Mini SATA External Multilane This section defines standard cable assemblies and headers for connecting multiple Serial ATA channels from a RAID host bus adapter to an intelligent backplane in an adjacent JBOD (just a bunch of disks) unit. The RAID HBA and the JBOD units are envisioned as using different power supplies. This cable/connector system is based on the SFF-8086 and SFF-8088 specifications. Both SFF8086 and SFF-8088 specifications are also used by Serial Attached SCSI (SAS). 6.5.3.1 Conformance Criteria Serial ATA Revision 3.0 Gold Revision page 161 of 663 The External Multilane cable/connector shall be used with either Gen1m/Gen2m or Gen1x/Gen2x signal levels. • 4 lanes, SAS/Serial ATA signals. • Cable length is two meters maximum for Gen1m and Gen2m applications. • Cable length is up to and greater than two meters for Gen1x and Gen2x applications. • RX, TX, RX, TX pin sequencing to minimize crosstalk. • Ground reference between each pair. • Performance for 3.0 Gbps. • Keying features for “m” and “x” cables. 6.5.3.1.1 Electrical Parameters The External Multilane cable assembly operating at Gen1m and Gen2m levels shall meet the electrical characteristics defined in Table 20. The External Multilane cable assembly operating at Gen1x and Gen2x levels shall meet the electrical characteristics defined in Table 21. 6.5.3.1.2 Mechanical Parameters Detailed mechanical requirements are specified in SFF-8086 and SFF-8088. The Mini SATA External Multilane cables and connectors shall use the 26-circuit version plug and receptacle defined in SFF-8086 and SFF-8088. The pull-tab for the Mini SATA External Multilane connector, if present, shall be red (Pantone #207). 6.5.3.2 Mini SATA External Multilane Keying Requirements The Mini SATA External Multilane cable/connector shall include keying features from SFF-8088. The Serial ATA defined key locations are shown in Figure 102. Unique keying requirements for x-level signal levels, is shown in Figure 103. Unique keying requirements for m-level signal levels is shown in Figure 104. Figure 102 Mini SATA External Multilane System, Key Features Serial ATA Revision 3.0 Gold Revision page 162 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Figure 103 Mini SATA External Multilane System, Key Slots 1 and 4 for “x level” Signals Key Slot 7 Key 7 Figure 104 Mini SATA External Multilane System, Key Slots 7 for “m level” Signals 6.5.3.3 Mini SATA External Multilane Pin Assignments Serial ATA Revision 3.0 Gold Revision page 163 of 663 The Mini SATA External Multilane connector pin assignments are shown in Figure 105. B13 B1 A1 A13 Signal SIGNAL GND RX 0+ RX 0SIGNAL GND RX 1+ RX 1SIGNAL GND RX 2+ RX 2SIGNAL GND RX 3+ RX 3SIGNAL GND SIGNAL GND TX 0+ TX 0SIGNAL GND TX 1+ TX 1SIGNAL GND TX 2+ TX 2SIGNAL GND TX 3+ TX 3SIGNAL GND CHASSIS GROUND Signal pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 HOUSING Figure 105 Mini SATA External Multilane Connector Pin Assignments Serial ATA Revision 3.0 Gold Revision page 164 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 6.6 Cable and Connector Electrical Specifications The purpose of this section is to specify the electrical characteristics of the cable and connector for all cabled usage models. The electrical characteristics defined herein describe relevant electrical characteristics required for high-speed signal transmission. An example test methodology is presented in Table 22 and Table 23 that may be used as a tool for characterizing cables, connectors, and PCB signal paths, i.e. microstrip and stripline traces. Different test methodologies and/or equipment may be used as long as they provide equivalent results. The cable and connector shall meet the electrical requirements listed below before and after all the tests listed in Table 6 and Table 9 are performed. 6.6.1 Serial ATA Cable 6.6.1.1 Electrical Requirements The electrical requirements for the internal single lane and Multilane Serial ATA cables and connectors for systems operating at Gen1i, Gen2i or Gen3i levels are listed in Table 18. Table 18 – Internal Cable / Connector Measurement Parameter and Requirements Parameter Mated Connector Differential Impedance Cable Absolute Differential Impedance Cable Pair Matching Impedance Common Mode Impedance Maximum Insertion Loss of Cable (10-4500 MHz) Maximum Crosstalk, single lane: NEXT (10-4500 MHz) Maximum Crosstalk, Multilane: CXT (10 – 4500 MHz) Maximum Rise Time Maximum Inter-Symbol Interference Maximum Intra-Pair Skew Requirement 100 Ohms ±15% 100 Ohms ±10% ±5 Ohms 25 - 40 Ohms 6 dB 26 dB loss 30 dB loss 85 ps (20-80%) 50 ps 10 ps Procedure P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Note: The Internal Multilane and Mini SATA Internal Multilane maximum crosstalk is different than single lane. Since these cables are Multilane and have multi-aggressors, the additional requirement is to have crosstalk measured using the CXT method. The electrical requirements for the External Single Lane cable and connector for systems operating at Gen1m or Gen2m levels are defined in Table 19. Table 19 – External Single Lane Cable / Connector Measurement Parameter and Requirements Parameter Mated Connector Differential Impedance Cable Absolute Differential Impedance Cable Pair Matching Impedance Common Mode Impedance Maximum Insertion Loss of Cable (10-4500 MHz) Maximum Crosstalk: NEXT (10-4500 MHz) Maximum Rise Time Maximum Inter-Symbol Interference Maximum Intra-Pair Skew Requirement 100 Ohms ±15% 100 Ohms ±10% ±5 Ohms 25 - 40 Ohms 8 dB 26 dB loss 150 ps (20-80%) 50 ps 20 ps Procedure P1 P2 P3 P4 P5 P6 P8 P9 P10 Serial ATA Revision 3.0 Gold Revision page 165 of 663 The electrical requirements for the External Multilane cable and connector for systems operating at Gen1m or Gen2m levels are defined in Table 20. Table 20 – Limited External Multilane Cable / Connector Measurement Parameter and Requirements Parameter Mated Connector Differential Impedance Cable Absolute Differential Impedance Cable Pair Matching Impedance Common Mode Impedance Maximum Insertion Loss of Cable (10-4500 MHz) Maximum Crosstalk: CXT (10-4500 MHz) Maximum Rise Time Maximum Inter-Symbol Interference Maximum Intra-Pair Skew Requirement 100 Ohms ±10% 100 Ohms ±5% ±5 Ohms 25 Ohms - 40 Ohms 8 dB 30 dB CXT 150 ps (20-80%) 50 ps 20 ps Procedure P1 P2 P3 P4 P5 P7 P8 P9 P10 Note: External Multilane cables for Gen1m or Gen2m signaling are limited to 2 meters in length. The electrical requirements for the External Multilane cable and connector for systems operating at Gen1x or Gen2x levels are defined in Table 21. Table 21 – Extended External Multilane Cable / Connector Measurement Parameter and Requirements Parameter Mated Connector Differential Impedance Cable Absolute Differential Impedance Cable Pair Matching Impedance Common Mode Impedance Maximum Insertion Loss of Cable (10-4500 MHz) Maximum Crosstalk: CXT (10-4500 MHz) Maximum Rise Time Maximum Inter-Symbol Interference Maximum Intra-Pair Skew Requirement 100 Ohms ±10% 100 Ohms ±5% ±5 Ohms 25 Ohms - 40 Ohms 16 dB 30 dB CXT 150 ps (20-80%) 60 ps 20 ps Procedure P1 P2 P3 P4 P5 P7 P8 P9 P10 Note: All External Multilane cables longer than 2 meters use Gen1x or Gen2x levels. 6.6.2 Cable/Connector Test Methodology 6.6.2.1 Test Equipment Serial ATA Revision 3.0 Gold Revision page 166 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization The following list identifies the type and performance of suggested equipment to perform the characterization procedures outlined in Table 22 and Table 23. • High Bandwidth Sampling Oscilloscope • TDR Module – < 35 ps (20% - 80%) Edge Rate Step Response • Vector Network Analyzer – 4 port, 13.5 GHz BW o Suggested 20 GHz BW • High Performance Coaxial Cables – = 20 GHz BW • Low Jitter 3.0 Gb/s Pattern Source – 20%-80% rise time of 136 ps minimum. (The rise time should be as close to 136 ps as is practical.) 6.6.2.2 Test and Measurement Conditions Unless otherwise specified, all tests and measurements shall be performed under the following conditions: • Cable/Connector Mated • Temperature: 15° to 35° C • Relative Humidity: 20% to 80% • Atmospheric Pressure: 650 mm to 800 mm of Hg 6.6.2.3 Test Fixture Considerations Characterization of the cable/connector configuration requires an interface between the unit under test (UUT) and the test equipment and is commonly referred to as the test fixture. A primary objective in using a test fixture is to eliminate, as much as possible, the adverse signal integrity effects of the PCB. The following guidelines should be followed when defining the test fixture. Consider the following: • The test fixture should use differential microstrip traces (100 ±5 Ohms) over a ground plane (single ended 50 ±2.5 Ohms). • Open or shorted traces with the same length as the input signal traces shall be provided to enable the following: o Establish system input rise time o Synchronize pulses o Establish reference plane • Traces for crosstalk measurements should diverge from each other. • Provisions for attenuation reference measurement should also be provided. Serial ATA Revision 3.0 Gold Revision page 167 of 663 6.6.2.4 Test Definition / Methodology There are a number of steps within the test procedures used in preparation of making a measurement and are referred to as common procedures. They consist of calibration, deskewing, establishing a reference plane, and establishing a rise time reference trace. Prior to performing any procedures or gathering data, ensure that the test equipment has been properly calibrated. The methodology to complete each of the common procedures is outlined in Table 22. Serial ATA Revision 3.0 Gold Revision page 168 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Table 22 – Common Interconnect Measurement Procedure Methodologies C1 Minimizing Skew between V+ and V-, Diff Signals 1. Define Differential Channel Stimulus a. Channel 1/3 positive edge step response (V+) b. Channel 2/4 negative edge step response (V-) 2. Differential response, e.g. Response Use math – Identify the differential signal function to obtain Vdiff = V+ - (VV-di(ffC) Has1-aCsHc2opoer CH3-CH4) 3. Minimize skew between the V+ (positive) and V- (negative) edges by adjusting either the V+ (CH1/3) or V- (CH2/4) edge forward or backward in time until both edges align to within 1ps. C2 Establishing a reference plane at the connector 1. Follow calibration procedures outlined in the firmware of the oscilloscope. 2. Select the define reference plane option within the scope firmware to establish a reference plane at the input of the test fixture. 3. When establishing a new reference plane, use precision 50 Ohm loads or precision air lines that are terminated with 50 Ohm loads for the test fixture. C3 Establishing the rise time reference trace 1. Configure the TDR modules to generate a differential step impulse response and identify the differential rising edge of the trace. 2. Identify the high and low voltage values of the impulse response. 3. Identify the 20% and 80% voltage levels and verify that the rise time of the step impulse is between 25 ps and 35 ps. There are two methods for adjusting the step impulse response to be within the desired range: a. The system rise time is to be set via equipment filtering techniques. The filter programmed equals t2 r (observed ) t2 r (stimulus) b. Capture the measurement data and perform a post processing step to filter the captured data to the desired rise time within a waveform viewer or TDR SW application. 4. Once the correct rise time has been established, verify the rise time using the reference traces on the PCB fixture. Serial ATA Revision 3.0 Gold Revision page 169 of 663 The test methodologies and procedures outlined in Table 23 refer to the common procedures described in Table 22. The actual specification requirement values for each of these methodologies are listed in section 6.6.1.1. Table 23 – Interconnect Test Methodologies / Procedures P1 Mated Connector Differential Impedance 1. Calibrate the instrument and system using the measurement traces, then follow common procedures C1, C2, and C3. 2. The instrument rise time shall be set or the results filtered for a minimum of 55 ps to a maximum of 70 ps (20-80%) system risetime. The system risetime shall be set as close to 70 ps (20-80%) as practical. 3. Measure and record the maximum and minimum values of the near end connector differential impedance. P2 Cable Absolute Differential Impedance 1. Calibrate the instrument and system using the measurement traces, then follow common procedures C1, C2, and C3. 2. The instrument rise time shall be set or the results filtered for a minimum of 55 ps to a maximum of 70 ps (20-80%) system risetime. The system risetime shall be set as close to 70 ps (20-80%) as practical. 3. Measure and record maximum and minimum cable differential impedance values from the TDR trace in the first 500 ps of cable response following any vestige of the connector response. P3 Cable Pair Matching 1. Calibrate the instrument and system using the measurement traces, then follow common procedures C1, C2, and C3. 2. The instrument rise time shall be set or the results filtered for a minimum of 55 ps to a maximum of 70 ps (20-80%) system risetime. The system risetime shall be set as close to 70 ps (20-80%) as practical. 3. Measure and record the single-ended cable impedance of each cable within a pair, e.g. ZL1, ZL2. 4. Measure and record maximum and minimum cable impedance values from the TDR trace in the first 500 ps of cable response following any vestige of the connector response, e.g. ZL1-max, ZL1-min and ZL2-max, ZL2-min. 5. The desired parameter equals Zmax = ZL1-max – ZL2-max and Zmin = ZL1-min – ZL2-min. Serial ATA Revision 3.0 Gold Revision page 170 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization P4 Common Mode Impedance 1. Calibrate the instrument and system using the measurement traces, then follow common procedures C1, C2, and C3. 2. The instrument rise time shall be set or the results filtered for a minimum of 55 ps to a maximum of 70 ps (20-80%) system risetime. The system risetime shall be set as close to 70 ps (20-80%) as practical. 3. Select the negative edge step response channel to be a positive edge step response such that both channels generate a positive edge step response. 4. Measure the even mode impedance from the TDR trace of the first step generator in the first 500 ps of cable response following any vestige of the connector response. 5. Perform a math function on the waveform to divide the even mode impedance response by 2. The result is the Common Mode Impedance. 6. Make the same measurement and math calculation of the second step generator. 7. The Common Mode Impedance for each step generator shall meet the requirement. P5 Insertion Loss 1. Calibrate the instrument and system using the measurement traces, then follow common procedures C1 and C2. 2. Measure and store the insertion loss (IL) of the fixturing using the IL reference traces provided on the board over a frequency range of 10 to 4500 MHz, e.g. ILfixture. 3. Measure and record the IL of the sample, which includes fixturing IL, over a frequency range of 10 to 4500 MHz, e.g. ILsystem. 4. The insertion loss of the sample is calculated by ILsample = ILsystem – ILfixture. Serial ATA Revision 3.0 Gold Revision page 171 of 663 P6 Differential to Differential Crosstalk: NEXT 1. Calibrate the instrument and system using the measurement traces, then follow common procedures C1, C2, and C3. 2. Terminate the far ends of the reference trace with characteristic impedance loads of 50 Ohms. 3. Measure and record the system and fixturing crosstalk. It is defined as the noise floor, e.g. Vnoise. 4. Terminate the far ends of the device and listen lines with characteristic impedance loads of 50 Ohms. 5. Connect the source to the device pair and the receiver to the near-end of the listen pair. 6. Measure the NEXT over a frequency range of 10 to 4500 MHz, e.g. VNEXT. 7. Verify that the sample crosstalk is out of the noise floor, e.g. VNEXT > Vnoise. Serial ATA Revision 3.0 Gold Revision page 172 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization P7 Multilane (Multi Disturber) Differential Crosstalk: ML-CXT 1. Calibrate the instrument and system using the measurement traces, then follow common procedures C1, C2, and C3. 2. Terminate the far ends of the reference trace with characteristic impedance loads of 50 Ohms. 3. Measure and record the system and fixturing crosstalk. It is defined as the noise floor, e.g. Vnoise. 4. Terminate the far ends of the device and listen lines with characteristic impedance loads of 50 Ohms. 5. Connect the source to the device pair and the receiver to the near-end of the listen pair. 6. Measure the CXT over a frequency range of 10 to 4500 MHz, e.g. VCXT. 7. Verify that the sample crosstalk is out of the noise floor, e.g. VCXT > Vnoise. 71 8. MLCXT ( f ) = 20 × log 10 VCXT ( f )l 20 A=1 where: MLCXT(f) is the Multilane Cable assembly Crosstalk at frequency f observed on any given receive lane. VCXT (f)A is the relative crosstalk at frequency f between the receiver/victim and any combination of aggressor A1, which exhibits less than 40 dB of isolation. f is the frequency ranging from 10 MHz to 4.5 GHz A is the 1,2 –7 (receiver/victim to aggressor1 pair combinations) 1. Aggressor: Any lane identified as a Tx (input) shall be considered as a potential aggressor. This includes near end and far end Tx lane Note: MLCXT summation calculations accounts for any aggressor1 relative to a receiver/victim pair which exhibit less than 40 dB of isolation. Serial ATA Revision 3.0 Gold Revision page 173 of 663 P8 Differential Rise Time 1. Calibrate the instrument and system using the measurement traces, then follow common procedures C1, C2, and C3. 2. Connect the TDR step impulse response generators to the near end of the signal path under test. 3. Record the output rise time at the far end of the signal path under test. P9 Inter-Symbol Interference Note: As incident (test system induced) DJ may not be de-convolved from the end results, it’s critical one use a high quality (low jitter) fixture and stimulus system when performing this measurement. 1. Connect a differential pattern source at the input of the test fixture. The 20%-80% rise time and fall time of the pattern source shall be 136 ps minimum. The rise and fall times should be as close to 136 ps as is practical, to minimize the resulting DJ and produce the most accurate results. Generate a LBP at 3.0 Gbps through the fixture. The Lone Bit Pattern emphasizes ISI. 2. Using a JMD, evaluate the Deterministic Jitter (DJ) introduced at the end of the cable. P10 Intra-Pair Skew 1. Calibrate the instrument and system using the measurement traces, then follow common procedures C1, C2, and C3. 2. Measure the propagation delay of each single ended signal within a pair at the mid point of the voltage swing, e.g. tdelay = Vmid+ - Vmid- where Vmid = Vhigh 2 Vlow . 6.7 Power Segment Pin P11 Definition (Optional) Pin P11 of the power segment of the device connector may be used by the device to provide the host with an activity indication and it may be used by the host to indicate whether staggered spinup should be used. To accomplish both of these goals, pin P11 acts as an input from the host to the device prior to PHYRDY for staggered spin-up control and then acts as an output from the device to the host after PHYRDY for activity indication. The activity indication provided by pin P11 is primarily for use in backplane applications. Reference section 13.14 for information on activity LED generation for desktop applications. A device may optionally support activity indication via pin P11, staggered spin-up control via pin P11, or both features. If neither feature is supported, then pin P11 is a no-connect at the device as specified in Table 3. A host may only support one pin P11 feature, either receiving activity indication or staggered spin-up disable control. If a host supports receiving activity indication via pin P11, then the host Serial ATA Revision 3.0 Gold Revision page 174 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization shall not use pin P11 to disable staggered spin-up. If a host does not support receiving activity indication via pin P11, then the host may use pin P11 to disable staggered spin-up. 6.7.1 Device Activity Signal 6.7.1.1 Electrical Definition The signal the device provides for activity indication is a low-voltage low-current driver intended for efficient integration into current and future IC manufacturing processes. The signal is not suitable for directly driving an LED and shall first be buffered using a circuit external to the device before driving an LED. The activity signal is based on an open-collector or open-drain active-low driver. The device shall tolerate the activity signal being shorted to ground. The device shall tolerate a no-connect floating activity signal. Table 24 and Table 25 define the electrical parameters and requirements for the activity signal for both the device and the host. Figure 106 is an example of an activity signal implementation for illustrative purposes. Note that the host should not rely on a particular resistor pull-up value on the device side, nor should the device rely on particular host resistor values. No direct support for wired-OR signals from multiple devices is accommodated. Host implementations that produce a single activity signal by combining multiple device inputs should buffer the signals prior to combining them. +V +VHH +VLED Spinup Control Activity Power RPU segment connector R2 R1 D1 I D + Pin P11 + -Activity V V D H Pin P12 - GND - LED Driver DEVICE HOST Figure 106 – Example activity signal electrical block diagram All voltage references in Table 24 and Table 25 are to ground pin P12 on the device connector. All voltages and currents in Table 24 and Table 25 are measured at pin P11 on the device connector. Serial ATA Revision 3.0 Gold Revision page 175 of 663 Table 24 – Power segment pin P11 activity signal electrical parameters Parameter V DIn V DAct V DInact I DInact Min Value -0.5 V 0 mV -0.1 V -10 uA Max Value 2.1 V 225 mV 3.3 V 100 uA Description & Conditions Tolerated input voltage Device output voltage when driving low under the condition I less than or equal to D 300 uA Device output voltage when not driving low Device leakage current when not driven Parameter V HIn V HH V HL I HAct Table 25 – Host activity signal electrical parameters Min Value -0.5 V -0.1 V Max Value 3.3 V 2.1 V 300 uA Description & Conditions Tolerated input voltage Host voltage presented to device when device not driving signal low. (Also see section 6.7.2 for staggered spin-up control). Minimum allowable host voltage that may be presented to the device. Host current delivered to device when device driving signal low. Value specified at V voltage of 0 V. DAct 6.7.1.2 LED Driver Circuit (Informative) The LED driver circuit provided by the host to drive an activity LED is vendor specific. Figure 107 illustrates two conceptual driver circuits that satisfy the electrical requirements and provide a signal suitable for driving an activity LED. Variations in the driver circuits may be employed to drive the LED when active or to drive the LED when the device is inactive through the use of an inverting or non-inverting buffering arrangement. Serial ATA Revision 3.0 Gold Revision page 176 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Figure 107 – Example host LED driver circuits 6.7.1.3 Functional Definition Table 26 defines the two activity signal states and the corresponding conditions. Table 26 – Activity signal functional states State Condition Signal asserted (driven low) Command(s) outstanding1 Signal negated (high impedance) All other conditions Notes: 1. Devices may omit asserting the activity signal for commands that do not access the media and have an expected service time too short to allow visual perception of the signal. Command(s) outstanding does not include the software reset, power-on reset, or COMRESET command protocols. As a consequence, pin P11 shall not be driven low by the device prior to return of the reset signature for the reset command protocols. This is behaviorally different than the parallel ATA DASP- signal. 6.7.2 Staggered Spin-up Disable Control 6.7.2.1 Electrical and Functional Definition The staggered spin-up feature is defined in section 13.10. Devices may optionally provide support to disable staggered spin-up through pin P11 of the power segment connector. The staggered spin-up disable control is an active asserted low host signal. Before the device spins up its media, devices that support staggered spin-up disable control shall detect whether pin P11 is asserted low by the host. If pin P11 is asserted low the device shall disable staggered spin-up and immediately initiate media spin-up. If pin P11 is not connected in the host (floating), devices that support staggered spin-up disable through pin P11 shall enable Serial ATA Revision 3.0 Gold Revision page 177 of 663 staggered spin-up. Table 27 defines the electrical signal requirements for the device detection of staggered spin-up disable. Table 27 – Host staggered spin-up control electrical requirements Parameter V HEnb V HDis Min Value 1.8 V -0.1 V Max Value V HHmax 225 mV Description & Conditions Host voltage presented to device to not disable staggered spin-up in devices that support staggered spin-up control. Value specified for all allowable I leakage DInact currents. Host voltage presented to device to disable staggered spin-up in devices that support staggered spin-up control. Value specified for all allowable I leakage currents. DInact The staggered spin-up control indication provided by a host or storage subsystem shall be static and shall not be changed while power is applied. If the signal is pulled low by the host during the staggered spin-up disable detection period, the signal shall remain low. Devices shall disable the activity signal if the host signals staggered spin-up disable. If supported, the device shall sample the staggered spin-up disable condition after the time DC power is applied and before PHYRDY is asserted. 6.7.2.2 Staggered Spin-up Disable Circuit (Informative) The host circuit for signaling staggered spin-up disable by pulling pin P11 low is vendor specific. Figure 108 illustrates a conceptual host circuit that would satisfy the electrical requirements for signaling staggered spin-up disable. It is permissible for the host to statically short pin P11 to ground or for the host to actively drive the signal low. +V Spinup Control Power RPU segment connector Activity I D + Pin P11 + -Activity V D V H - Pin P12 GND - DEVICE HOST Figure 108 – Example host circuit for signaling staggered spin-up disable Serial ATA Revision 3.0 Gold Revision page 178 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 6.8 Precharge and Device Presence Detection For a storage subsystem, hot-plug capability is required as well as the ability to seamlessly handle presence detection in those cases where the storage subsystem may remove power to individual receptacles. 6.8.1 Device Requirements In order to accommodate hot-insertion with the use of the precharge feature as well as a means for presence detection, Serial ATA devices shall bus together all power delivery pins for each supply voltage. 6.8.2 Receptacle Precharge (Informative) The Serial ATA device connector has been specifically designed to accommodate a robust hotplug capability. One feature of the device connector is the ability for receptacles to limit the instantaneous inrush current through the use of a precharge scheme. This scheme relies on one power delivery contact for each voltage being longer than the remaining contacts in order to allow power to be delivered through this longer contact through a current limiting device. Figure 109 illustrates one hot-plug power delivery scheme that utilizes the precharge connector feature. Drive Back plane A RL B + V1 - Figure 109 – Typical precharge configuration All burden for limiting the inrush current for a newly inserted device is borne by the receptacle/backplane. The exact current limiting resistor size appropriate for a particular backplane solution depends on the details of the implementation. A few of the variables to be considered in sizing the current limiting resistor include: - Device insertion velocity - Effective capacitance of the inserted device - Contact current carrying capacity A survey of these variables by the group indicated that for one particular application, the maximum insertion velocity yielded a contact precharge time of approximately 3 ms. A poll of several disk drive vendors indicated a typical effective capacitance for disk drive devices of approximately 20 uF. For illustrative purposes, these values are presumed in an example scenario for estimating the precharge resistor value. The amount of time required to charge the effective capacitance to 90% of full charge is roughly 2.2 • R • C. Thus: Serial ATA Revision 3.0 Gold Revision page 179 of 663 T = 2.2 R CEQ R = T 2.2 CEQ For the example charging time of 3 ms and an effective capacitance of 20 uF, the resultant precharge resistor value is approximately: R= 3ms 2.2 20uF = 68 Because the Serial ATA power conductors support currents up to 1.5 A, the computed resistor size may be substantially reduced without adverse consequence in order to reduce the sensitivity to the device’s actual effective capacitance. For the 12 V supply rail, the resistor may be as small as 8 Ohms and still not exceed the current carrying capacity of the precharge contact. Depending on the details of the actual enclosure subsystem design, typical precharge resistor values for the illustrative example scenario may therefore be in the range of 10-20 Ohms. 6.8.3 Presence Detection (Informative) Presence detection relies on the device signaling the host using the OOB sequence to indicate its presence after a hot insertion. This approach presumes the device is inserted into a hot receptacle and also presumes the device inserted is not malfunctioning. In a storage subsystem, these assumptions may not be appropriate since such storage solutions may have the ability to unpower individual device receptacles in order to make device insertion/removal safer. Thus, a means for determining device presence in a receptacle that does not have power applied and without the device having to function is desired. One possible device presence detection mechanism utilizes the precharge circuit outlined in section 6.8.2. The basic approach is to determine presence of a device by measuring the impedance between points A and B in the diagram. Because devices bus together their respective power delivery contacts, the impedance between points A and B in the diagram is R L with no device present and is effectively zero with a device inserted in the receptacle. Figure 110 illustrates one possible circuit for handling device presence detect with the receptacle either powered or unpowered. The example circuit is subject to tolerance buildup of the selected components and the supply voltages, and are only presented as conceptual examples. Serial ATA Revision 3.0 Gold Revision page 180 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 12V Drive 330 12V 330 Host A R =20 L + C B 10 + 240 240 5V - Figure 110 – Example presence detection implementation Table 28 – Comparator voltages for alternate example presence detection circuit Receptacle Powered Receptacle unpowered Device not present V = 5.40 V V = 5.17 V V = 5.29 V V = 5.17 V A C A C Device present V = 5.0 V V = 5.17 V *V = 5.05 V V = 5.17 V A C A C *If the inserted device provides a finite impedance to ground, then V should be lower than this A value increasing the voltage differential further and increasing the margins. Serial ATA Revision 3.0 Gold Revision page 181 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7 Phy Layer This section describes the physical layer of Serial ATA. The information that is provided is comprised of two types – informative and normative. Unless otherwise described, the information should be considered normative in nature and is included in this document as a necessary requirement in order to properly allow a piece of equipment to attach to another piece of equipment. The normative information is deliberately structured to constrain and define areas only to the degree that is required for compatibility. The information that is provided and marked informative is provided only to help the reader better understand the normative sections and should be taken as examples only. Exact implementations may vary. 7.1 Descriptions of Phy Electrical Specifications The following terms have been developed for the various Electrical Specifications: • Gen1i: Generation 1 Electrical Specifications: These are the 1.5 Gbps electrical specifications for internal host to device applications. • Gen1m: Generation 1 Electrical Specifications for Short Backplane and external cabling applications: These are the 1.5 Gbps electrical specifications aimed at short 1.5 Gbps internal backplane applications, External Desktop Applications using the external single lane cable, and System-to-System Data Center Applications using external Multilane cables up to two meters in length. These include only modified receiver Differential input specifications. All other electrical specifications relating to Gen1m compliance points are identical to Gen1i specifications. This specification is for these limited applications only and is not intended for any other system topology. • Gen1x: Extended Length 1.5 Gbps Electrical Specifications: These are electrical specifications aimed at 1.5 Gbps links in Long Backplane and System-to-System Data Center Applications supporting external Multilane cables up to and greater than two meters. These specifications are based upon the SAS references. • Gen2i: Generation 2 Electrical Specifications: These are 3.0 Gbps electrical specifications for internal host to device applications. • Gen2m: Generation 2 Electrical Specifications for Short Backplane and External Desktop Applications: These are 3.0 Gbps electrical specifications aimed at short internal backplane applications, External Desktop Applications using the external single lane cable, and System-to-System Data Center Applications using external Multilane cables up to two meters in length. These include only modified receiver differential input specifications. All other electrical specifications relating to Gen2m compliance points are identical to Gen2i specifications. This specification is for this limited application only and is not intended for any other system topology. • Gen2x: Extended Length 3.0 Gbps Electrical Specifications: These are electrical specifications aimed at 3.0 Gbps links in Long Backplane and System-to-System Data Center Applications supporting external Multilane cables up to and greater than two meters. These specifications are based upon the SAS references. • Gen3i: Generation 3 Electrical Specifications: These are 6.0 Gbps electrical specifications for internal host to device applications. 7.1.1 List of Services • Transmit a 1.5 Gbps,3.0 Gbps, or 6.0 Gbps differential NRZ serial stream at specified voltage levels. • Provide a 100 Ohm matched termination (differential) at the transmitter. • Serialize a 10, 20, 40, or other width parallel input from the Link for transmission. • Receive a 1.5 Gbps,3.0 Gbps, or 6.0 Gbps differential NRZ serial stream with data rates of ±350 ppm with +0/-5000 ppm (due to SSC profile) from the nominal data rate. • Provide a 100 Ohms matched termination (differential) at the receiver. Serial ATA Revision 3.0 Gold Revision page 183 of 663 • Extract data (and, optionally, clock) from the serial stream. • De-serialize the serial stream. • Detect the K28.5 comma character and provide a bit and word aligned 10, 20, 40, or other width parallel output. • Provide specified OOB signaling detection and transmission. • Use OOB signaling protocol for initializing the Serial ATA interface, and use this OOB sequence to execute a pre-defined speed negotiation function. • Perform proper power-on sequencing and speed negotiation. • Provide device status to Link layer. - Device present. - Device absent. - Device present but failed to negotiate communications. • Optionally support power management modes. • Optionally perform transmitter and receiver impedance calibration. • Handle the input data rate frequency variation due to a spread spectrum transmitter clock. • Accommodate request to go into Far-End retimed loopback, and other BIST Activate FIS test modes of operation when commanded. 7.1.2 Low Level Electronics Block Diagrams (Informative) The following block diagrams are provided as a reference for the following sections of this document. Although informative in nature, the functions of the blocks described herein provide the basis upon which the normative specifications apply. The individual blocks provided are provided as an example of one possible implementation. 7.1.2.1 Physical Plant Block Diagram Serial ATA Revision 3.0 Gold Revision page 184 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization DATAIN[0:n]* I * Note: Signals annotated with an asterisk (*) are required in all compliant devices. Fixed Pattern Source HRESET* I PHYRDY* o SLUMBER* I PARTIAL* I NEARAFELB* I FARAFELB* I SPDSEL I SPDMODE o SYSTEMCLOCK I Device Detect o PHY Internal Error o Control Block TxClock Analog Front End o TX(+)* o TX(-)* COMMA o Fixed Pattern Detect DATAOUT[0:n]* o RXCLOCK o COMINIT*/ o COMRESET COMWAKE* o Recovered Clock Data Extraction Block I RX(+)* I RX(-)* Figure 111 – Physical Plant Overall Block Diagram (Informative) Serial ATA Revision 3.0 Gold Revision page 185 of 663 Physical Plant Overall Block Diagram Description Analog front end This block is the basic interface to the transmission line. This block consists of the high-speed differential drivers and receivers as well as the OOB signaling circuitry. Control block This block is a collection of logic circuitry that controls the overall functionality of the Physical plant circuitry. Fixed pattern source Fixed pattern detect Data extraction block This block provides the support circuitry that generates the patterns as needed to implement ALIGNP activity. This block provides the support circuitry to allow proper processing of the ALIGNP primitives. This block provides the support circuitry to separate the clock and data from the high-speed input stream. TX clock This signal is internal to the Physical plant and is a reference signal that regulates the frequency at which the serial stream is sent via the high speed signal path TX + / TX - These signals are the outbound high-speed differential signals that are connected to the serial ATA cable. RX + / RX - These signals are the inbound high-speed differential signals that are connected to the serial ATA cable. DATAIN Data sent from the Link layer to the Phy layer for serialization and transmission. PHYRESET This input signal causes the Phy to initialize to a known state and start generating the COMRESET OOB signal across the interface. PHYRDY Signal indicating Phy has successfully established communications. The Phy is maintaining synchronization with the incoming signal to its receiver and is transmitting a valid signal on its transmitter. SLUMBER Causes the Phy layer to transition to the Slumber power management state. PARTIAL Causes the Phy layer to transition to the Partial power management state NEARAFELB Causes the Phy to loop back the serial data stream from its transmitter to its receiver FARAFELB Causes the Phy to loop back the serial data stream from its receiver to its transmitter SPDSEL Causes the control logic to automatically negotiate for a usable interface speed or sets a particular interface speed. The actual functionality of this input is vendor specific and varies from manufacturer to manufacturer. Serial ATA Revision 3.0 Gold Revision page 186 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization SPDMODE Output signal that reflects the current interface speed setting. The actual functionality of this signal is vendor specific and varies from manufacturer to manufacturer. SYSTEMCLOCK This input is the clock source for much of the control circuit and is the basis from which the transmitting interface speed is established. COMMA This signal indicates that a K28.5 character was detected in the inbound high-speed data stream. DATAOUT Data received and de-serialized by the Phy and passed to the Link layer RX CLOCK / Recovered clock This signal is derived from the high speed input data signal and determines when parallel data has been properly formed at the DATAOUT pins and is available for transfer to outside circuitry. COMRESET / COMINIT Host: Signal from the OOB detector that indicates the COMINIT OOB signal is being detected. Device: Signal from the OOB detector that indicates the COMRESET OOB signal is being detected. COMWAKE Signal from the OOB detector that indicates the COMWAKE OOB signal is being detected. Serial ATA Revision 3.0 Gold Revision page 187 of 663 TX 50 • TX+ TX data REF • 50 TX Termination Calibration RX RX Data + • 50 • 50 RX+ • • RX • • COMWAKE COMRESET / COMINIT OOB Signal Detector PLL Squelch Voltage Regulator Figure 112 – Analog Front End (AFE) Block Diagram [External AC caps not shown] Serial ATA Revision 3.0 Gold Revision page 188 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.1.2.2 Analog Front End (AFE) Block Diagram Description TX This block contains the basic high-speed driver electronics. RX This block contains the basic high-speed receiver electronics. Termination calibration This block is used to establish the impedance of the RX block in order to properly terminate the high-speed serial cable. Squelch This block establishes a limit so that detection of a common mode signal may be properly accomplished. OOB signal detector This block decodes OOB signal from the high-speed input signal path. PLL This block is used to synchronize an internal clocking reference so that the input high-speed data stream may be properly decoded. Voltage Regulator This block stabilizes the internal voltages used in the other blocks so that reliable operation may be achieved. This block may or may not be required for proper operation of the balance of the circuitry. The need for this block is implementation specific. TX+ / TX- This is the same signal as described in the previous section: Physical plant overall block diagram description. RX+ / RX- This is the same signal as described in the previous section: Physical plant overall block diagram description. TxData Serially encoded 10b data attached to the high-speed serial differential line driver. RxData Serially encoded 10b data attached to the high-speed serial differential line receiver. COMWAKE This is the same signal as described in the previous section: Physical plant overall block diagram description. COMRESET / COMINIT This is the same signal as described in the previous section: Physical plant overall block diagram description. Serial ATA Revision 3.0 Gold Revision page 189 of 663 TX Data RX Data COMWAKE COMRESET / COMINIT OOB Signal Detector PLL REF Termination Calibration • • Squelch Voltage Regulator + TX RX 50 50 • • TX+ TX 50 50 • • • Device AFE • RX+ RX TX+ TX RX+ RX • • Host AFE Squelch Voltage Regulator • • • 50 50 TX • 50 50 + RX OOB Signal Detector PLL Termination Calibration • REF • TX Data RX Data COMWAKE COMRESET / COMINIT Figure 113 – Analog Front End (AFE) Cabling [Editors note: External AC Coupling Capacitors not shown] Serial ATA Revision 3.0 Gold Revision page 190 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.1.3 Compliance Testing This document provides electrical specifications that when met by hosts, devices, and interconnects, satisfy the link performance specifications when combined into a system. This section of the document provides an overview of how to determine whether a Host, Device, or Interconnect is compliant to the specifications of this document. Each electrical specification requires a specific measurement, test setup and data patterns. This section ties all of these requirements together to aid the reader in understanding what is needed for compliance testing. Table 29, Table 30, Table 31, Table 32, Table 33, and Table 34 detail the electrical requirements for SATA compliance. Each requirement is defined in section 7.2.2. Jitter is described in section 7.3. Measurement methods for each specification are detailed in section 7.4. Section 7.5 discusses Interface States relating to OOB and power management. Section 6.6 describes the Interconnect requirements. The Phy layer is divided into a transmitter, interconnect, and a receiver. The SATA link is a full duplex point to point link as continuous data activity exists on each direction. For purposes of compliance testing of Hosts and Devices, the full duplex link is broken into two simplex links, one for the Host transmitting to the Device and the other for the Device transmitting to the Host. Each link is tested for compliance separately. Each transmitter to receiver Link contains the following elements: Transmitter (IC/PCB/SATA Connector) – to – Interconnect (Connector/Cable or PCB/Connector) – to – Receiver (SATA Connector / PCB / IC) Transmitter Interconnect Receiver PCB PCB Transmitter IC Plug Receptacle Receptacle Plug Receiver IC (AC Capacitors are optional for Gen 1i) Figure 114 – The Simplex Link In testing the compliance of SATA components that make up a system there are five Compliance Areas to be measured: 1. “Transmitted Signal”– Examine the transmitted signal quality at the compliance point for the Host/Device into a Laboratory Load. Electrical specifications include amplitude, rise/fall time, frequency, jitter, etc. The Electrical specifications apply to the signal output from the Transmitter-Under-Test at the mated connector when driving a Laboratory Load. No attempt has been made to specify the signal when attached to a cable, backplane or directly into another Device. Actual signals “In-System” may vary. Serial ATA Revision 3.0 Gold Revision page 191 of 663 2. “Transmitter” – Examine all specified characteristics of the Transmitter from the compliance point. This includes specifications such as differential and common-mode impedance. The “Transmitter” includes the IC, which incorporates the transmitter, the PCB, the SATA connector as well as any additional components between the IC and the SATA connector. 3. “Receiver” – Examine all specified characteristics of the Receiver from the compliance point. This includes specifications such as differential and common-mode impedance. The “Receiver” includes the SATA connector, the PCB and the IC, which incorporates the receiver as well as any additional components between the IC and the SATA connector. 4. “Receiver Tolerance” – When the Receiver is presented with a worst-case “Lab-Sourced Signal”, and operating with its active transmitter, shall meet the specified Frame Error Rates. This requires carefully controlled signal sources in order to generate a worst-case signal. 5. "Interconnect" -- Examine all specified characteristics of the interconnect, using test equipment. The interconnect includes SATA connector pairs at each end. The testing requirements and procedures are described in section 6.6. In order to determine compliance to the specifications of this document, measurements shall be performed separately with Host, Device, or Interconnect being tested when connected to test equipment. Compliance tests are not done with a Host, Device, or Interconnect connected together. Unless otherwise specified, all compliance measurements shall be taken through the mated connector pair. NOTE: The electrical specifications in the Receiver Tolerance Table do not describe the characteristics of the received signal; these describe the Lab-Sourced Signal calibrated into a Laboratory Load and subsequently applied to the Receiver. The Receiver Tolerance Table does not describe the characteristics of a signal from a Transmitter through an Interconnect into a Laboratory Load. Received signals in a system are potentially worse due to the non-ideal impedance match of the transmitter and the receiver. 7.1.4 Link Performance The performance of a SATA system with Host and Device linked together with an Interconnect is measured by the frame error rate, using a set of reference frames, defined by a specific set of ordered test patterns within the frame. An operating Host-Device duplex link that meets the Frame Error Rate (FER) specifications of Table 29 for both of its simplex links is deemed to fulfill Serial ATA performance levels. A Host or Device is commanded to generate the various test patterns through the use of the BIST Activate FIS or other vendor unique commands to the device under test. 7.2 Electrical Specifications The goal of this specification is to provide a description of characteristics to ensure interoperability of SATA components; devices, hosts, and interconnects. Any combination of compliant components should provide the stated link performance. Secondly a means of validation to the requirements is described in section 7.4. Validation consists of performing tests on individual SATA components. Serial ATA devices and hosts shall comply with the electrical specifications shown in Table 29, Table 30, Table 31, Table 32, Table 33, and Table 34. The transmitter consists of the driver integrated circuit (IC), printed circuit board, and mated connector pair. The receiver consists of the receiver IC, printed circuit board, and mated connector pair. Unless otherwise stated, all specifications include the mated connector pair. Serial ATA Revision 3.0 Gold Revision page 192 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.1 Physical Layer Requirements Tables Parameters Units Limit Table 29 – General Specifications Electrical Specification Detail Cross-Ref Section Measurement Cross-Ref Section Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i Channel Speed Gbps Nom Fbaud GHz Nom FER, Frame Error Max Rate TUI, Unit Interval Min ps Nom Max ftol, Min TX Frequency ppm Long Term of Fbaud Max Accuracy fSSC, SpreadSpectrum Modulation Frequency Min kHz Max SSCtol, SpreadSpectrum Modulation Deviation Min ppm of Fbaud Max 1.5 1.5 8.2e-8 at 95% confidence level 666.4333 666.6667 670.2333 -350 +350 30 33 -5350 +350 3.0 3.0 8.2e-8 at 95% confidence level 333.2167 333.3333 335.1167 -350 +350 30 33 -5350 +350 6.0 6.0 8.2e-8 at 95% confidence level 166.6083 166.6667 167.5583 -350 +350 30 33 -5350 +350 7.2.2.1.1 - 7.2.2.1.2 7.2.2.1.3 7.2.2.1.4 7.2.2.1.5 7.3.3 7.2.2.1.6 7.3.3 7.4.1 7.4.14 7.4.7 7.4.14 7.4.14 Serial ATA Revision 3.0 Gold Revision page 193 of 663 Parameters Units Limit Electrical Specification Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i Vcm,dc, DC Coupled Common Mode mV Voltage Vcm,ac coupled, AC Coupled Common Mode Voltage Zdiff, Nominal Differential Impedance Cac coupling AC Coupling Capacitance tsettle,cm, Common Mode Transient Settle Time mV Ohm nF ns Vtrans, Sequencing Transient V Voltage Min Nom Max Min Max Nom Max Max Min Max 200 - 250 - 450 - 0 - 2000 - 100 - 12 10 - -2.0 2.0 (AC only) (AC only) (AC only) - - 12 -2.0 2.0 (AC only) (AC only) (AC only) - 100 12 -2.0 2.0 Detail Cross-Ref Section Measurement Cross-Ref Section 7.2.2.1.7 7.4.5 7.2.2.1.8 7.4.29 7.2.2.1.9 7.4.26 7.2.2.1.10 7.4.17 7.2.2.2.13 7.2.5.3 7.2.2.1.11 7.4.16 Serial ATA Revision 3.0 Gold Revision page 194 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Parameters Units Limit Table 30 – Transmitter Specifications Electrical Specification Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i Vtrans, Sequencing Transient V Min - - -1.2 Voltage LL Max - - 1.2 ZdiffTX, TX Pair Differential Ohm Min 85 85 - 85 - Impedance Max 115 115 - 115 - Zs-eTX, TX Single-Ended Ohm Min 40 - - - Impedance Detail Measurement Cross-Ref Cross-Ref Section Section 7.2.2.1.12 7.4.30 7.2.2.2.1 7.4.26 7.2.2.2.2 7.4.27 Serial ATA Revision 3.0 Gold Revision page 195 of 663 Parameters Units Limit Electrical Specification Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i 75 MHz150MHz 14 14 - - - - - 150 MHz300 MHz 8 8 - 14 14 - - RLDD11,TX, 300 MHz600 MHz 6 6 - 88 - - TX Differential Mode Return Loss dB 600 MHz1.2 GHz 6 6 - 66 - - (All Values Min) 1.2 GHz2.4 GHz 3 3 - 66 - - 2.4 GHz3.0 GHz 1 - - 33 - - 3.0 GHz5.0 GHz - - -1- - - RLDD11,TX, TX Differential Mode Return Loss dB Min at 300MHz - --- 14 Start for slope Slope of TX Differential Mode dB/dec Nom - --- -13 Return Loss TX Differential Mode Return Loss Max GHz Max - --- 3 Frequency Detail Measurement Cross-Ref Cross-Ref Section Section 7.2.2.2.3 7.4.13 7.2.2.2.6 7.4.13 Serial ATA Revision 3.0 Gold Revision page 196 of 663 Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Parameters Units Limit 150 MHz300 MHz - 300 MHz600 MHz - RLCC11,TX, TX Common Mode Return 600 MHzdB 1.2 GHz - Loss (all Values Min) 1.2 GHz2.4 GHz - 2.4 GHz3.0 GHz - 3.0 GHz5.0 GHz - 150 MHz300 MHz - 300 MHz600 MHz - RLDC11,TX, 600 MHz1.2 GHz - TX Impedance Balance dB 1.2 GHz2.4 GHz - (all values Min) 2.4 GHz3.0 GHz - 3.0 GHz5.0 GHz - 5.0 GHz6.5 GHz - Electrical Specification 85 - - 55 - - 22 - - 11 - - 11 - - 1- - - 30 30 - 30 20 20 - 30 10 10 - 20 10 10 - 10 44 - 10 4- - 4 --- 4 Detail Measurement Cross-Ref Cross-Ref Section Section 7.2.2.2.4 7.4.13 7.2.2.2.5 7.4.13 Serial ATA Revision 3.0 Gold Revision page 197 of 663 Parameter Units Limit Table 31 – Transmitted Signal Requirements Electrical Specification Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i VdiffTX, TX Differential Output Voltage mVppd UIVminTX, TX Minimum Voltage UI Measurement Interval t20-80TX, ps TX Rise/Fall Time (UI) tskewTX, TX Differential Skew Vcm,acTX, TX AC Common Mode Voltage ps mVp-p Min Min Nom Max Max Min 2080% Max 2080% Max Max 400 400 400 400 400 400 - -- - -- 500 - - 600 1600 700 1600 - - - - 0.45-0.55 0.5 0.45-0.55 0.5 - - - - 100 (.15) 67 (.10) 273 (.41) 273 (.41) 20 67 (.20) 136 (.41) 20 15 - 50 - 240 900 - 0.50 33 (0.20) 68 (0.41) 20 - Detail Measurement Cross-Ref Cross-Ref Section Section 7.2.2.2.7 7.2.2.2.8 7.4.5 7.4.3 7.4.5 7.4.3 7.4.5 7.4.3.2 7.2.2.2.9 7.4.4 7.2.2.2.10 7.4.15 7.2.2.2.11 7.4.20 Serial ATA Revision 3.0 Gold Revision page 198 of 663 Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Parameter Units Limit Electrical Specification Vcm,acTX, TX AC Common Mode Voltage dBmV (rms) 3 GHz Max 6 GHz Max - - - - 26 30 DVdiffOOB, OOB Differential mV Max - 25 25 25 Delta DVcmOOB, OOB Common mV Max - 50 50 50 Mode Delta R/Fbal, TX Rise/Fall % Max - - 20 - - Imbalance Ampbal, TX Amplitude % Max - 10 10 - Imbalance TJ at Connector, Clk-Data, fBAUD/500 UI Max 0.37 - 0.37 - - JTF Defined DJ at Connector, Clk-Data, fBAUD/500 UI Max 0.19 - 0.19 - - JTF Defined Jitter Transfer Min 1.1 - 1.1 - - Function Bandwidth MHz Nom 2.1 - 2.1 - - (D24.3, high pass -3dB) Max 3.1 - 3.1 - - Serial ATA Revision 3.0 Gold Revision page 199 of 663 Detail Measurement Cross-Ref Cross-Ref Section Section 7.2.2.2.12 7.4.21 7.2.2.2.14 7.4.23 7.2.2.2.15 7.4.22 7.2.2.2.16 7.4.19 7.2.2.2.17 7.4.18 7.2.2.2.18 7.3 7.4.8 7.4.9 7.3.2 7.3.2 7.3.2 7.4.8 7.4.8 7.4.8 Parameter Units Limit Electrical Specification Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i Min 0 - 0 - - Jitter Transfer Function Peaking dB Nom 0 - 0 - - Max 3.5 - 3.5 - - Jitter Transfer Min 69 - 69 - - Function Low Frequency dB Nom 72 - 72 - - Attenuation Max 75 - 75 - - Jitter Transfer Function Low Frequency Attenuation kHz 30±1% - 30±1% - - Measurement Frequency Jitter Transfer Min - - - - 2.2 Function Bandwidth (D24.3, high pass MHz Nom - - - - 4.2 -3dB) Max - - 6.2 (Gen3) Jitter Transfer Min - - - - 0 Function Peaking dB Nom - - - - 0 (Gen3) Max - - - - 3.5 Detail Measurement Cross-Ref Cross-Ref Section Section 7.3.2 7.3.2 7.3.2 7.3.2 7.3.2 7.3.2 7.4.8 7.4.8 7.4.8 7.4.8 7.4.8 7.4.8 7.3.2 7.4.8 7.3.2.4 7.3.2.4 7.3.2.4 7.3.2.4 7.3.2.4 7.3.2.4 7.4.8 7.4.8 7.4.8 7.4.8 7.4.8 7.4.8 Serial ATA Revision 3.0 Gold Revision page 200 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Parameter Units Limit Electrical Specification Detail Measurement Cross-Ref Cross-Ref Section Section Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i Jitter Transfer Function Low Frequency dB Attenuation (Gen3) Jitter Transfer Function Low Frequency Attenuation kHz Measurement Frequency (Gen3) TJ after CIC, ClkData, fBAUD/1667 UI DJ after CIC, ClkData, fBAUD/1667 UI TJ before and after CIC, Clk-Data UI JTF Defined RJ before CIC, MFTP Clk-Data UI JTF Defined Min Nom Max Max Max Max Max - - - - - - - - - 0.55 - 0.35 - - - - - - - - 35.2 38.2 41.2 7.3.2.4 7.3.2.4 7.3.2.4 - - 420 +/- 1% 7.3.2.4 - 0.55 - 0.35 - - - RJ p-p meas. + 0.34 0.18 p-p - (2.14 ps 1 sigma) 7.2.2.2.18 7.3 7.2.2.2.18 7.3 7.4.8 7.4.8 7.4.8 7.4.8 7.4.8 7.4.9 7.4.8 7.4.10 Serial ATA Revision 3.0 Gold Revision page 201 of 663 Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i Table 32 – Receiver Specifications Parameter Units Limit Electrical Specification ZdiffRX, RX Pair Differential Impedance Ohm Min Max 85 115 - 85 - - 115 - Zs-eRX, RX SingleEnded Ohm Min 40 - - - Impedance Detail Cross-Ref Section Measurement Cross-Ref Section 7.2.2.3.1 7.4.26 7.2.2.3.2 7.4.27 Serial ATA Revision 3.0 Gold Revision page 202 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Parameter Units Limit Electrical Specification Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i 75MHz150MHz 18 18 - - - - - 150 MHz300 MHz 14 14 - 18 18 - - RLDD11,RX, RX Differential 300 MHz600 MHz 10 10 - 14 14 - - Mode Return Loss dB 600 MHz1.2 GHz 8 8 - 10 10 - - (all values Min) 1.2 GHz2.4 GHz 3 3 - 88 - - 2.4 GHz3.0 GHz 1 - - 3 3 - - 3.0 GHz5.0 GHz - - - 1 - - - RLDD11,RX, RX Differential Mode Return dB Min at 300MHz - Loss Slope of RX Differential Mode Return dB/dec Nom - Loss - 18 - -13 RX Differential Mode Return Loss Max GHz Max - Frequency - 6.0 Detail Cross-Ref Section Measurement Cross-Ref Section 7.2.2.3.3 7.4.13 7.2.2.2.6 7.4.13 Serial ATA Revision 3.0 Gold Revision page 203 of 663 Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i Parameter Units Limit Electrical Specification 150 MHz300 MHz - 5 5 - - RLCC11,RX, 300 MHz600 MHz - 5 5 - - RX Common 600 MHz- Mode Return Loss dB 1.2 GHz 1.2 GHz- (all values Min) 2.4 GHz - 2 2 - 1 1 - - 2.4 GHz3.0 GHz - 1 1 - - 3.0 GHz5.0 GHz - 1 - - - Detail Cross-Ref Section Measurement Cross-Ref Section 7.2.2.3.4 7.4.13 Serial ATA Revision 3.0 Gold Revision page 204 of 663 Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Parameter Units Limit Electrical Specification 150 MHz300 MHz - 30 30 - 30 300 MHz600 MHz - 30 30 - 30 RLDC11,RX, 600 MHz1.2 GHz - 20 20 - 20 RX Impedance Balance dB 1.2 GHz2.4 GHz - 10 10 - 10 (all values Min) 2.4 GHz3.0 GHz - 4 4 - 10 3.0 GHz5.0 GHz - 4 - - 4 5.0 GHz6.5 GHz - 4 - - 4 Detail Cross-Ref Section Measurement Cross-Ref Section 7.2.2.3.5 7.4.13 Serial ATA Revision 3.0 Gold Revision page 205 of 663 Table 33 – Lab-Sourced Signal (for Receiver Tolerance Testing) Electrical Specification Parameter Units Limit Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i Min 325 240 275 275 240 275 VdiffRX, RX Differential Input Voltage mVppd Min Nom Max - - 400 600 - - - - - - - - 1600 750 750 1600 Max - - - - - t20-80RX, RX Rise/Fall Time Min 100 (.15) 67 (.10) 20-80% ps - - (UI) Max 273 (.41) 20-80% - 67 (.20) 136 (.41) - UIVminRX, RX Minimum Voltage UI Measurement Interval tskewRX, RX Differential ps Skew Vcm,acRX, RX AC Common mVp-p Mode Voltage Max Max - 0.5 0.5 - - - - 80 50 75 100 150 100 150 240 1000 62 (0.37) 75 (0.45) - 0.5 30 100 Serial ATA Revision 3.0 Gold Revision page 206 of 663 Detail Cross-Ref Section Measurement Cross-Ref Section 7.2.2.5.1 7.2.2.5.2 7.2.2.5.3 7.4.6 7.4.3 7.4.12 7.4.6 7.4.3 7.4.12 7.4.4 7.4.4 7.4.12 7.4.4 7.4.4 7.4.12 7.4.6 7.4.3.2 7.2.2.5.4 7.4.15 7.2.2.5.5 7.4.11 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Parameter Units Limit Electrical Specification Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i fcm,acRX, Min 2 2 2 AC Common MHz Mode Frequency Max 200 200 200 Detail Cross-Ref Section Measurement Cross-Ref Section 7.2.2.5.6 7.4.11 Serial ATA Revision 3.0 Gold Revision page 207 of 663 Parameter Units Limit TJ at Connector, Clk-Data, fBAUD/500 UI Max JTF Defined DJ at Connector, Clk-Data, fBAUD/500 UI Max JTF Defined TJ at Connector, Clk-Data, UI Max fBAUD/1667 DJ at Connector, Clk-Data, UI Max fBAUD/1667 TJ after CIC, Clk-Data UI Max JTF Defined RJ before CIC, MFTP Clk-Data UI Max JTF Defined Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i Electrical Specification 0.60 0.60 - - 0.42 0.42 - - - 0.65 - 0.65 - 0.35 - 0.35 - - - - - - - - - - 0.60 0.18 p-p (2.14 ps 1 sigma) Detail Cross-Ref Section Measurement Cross-Ref Section 7.2.2.5.7 7.3 7.4.8 7.4.11 7.2.2.5.7 7.3 7.4.8 7.4.12 Serial ATA Revision 3.0 Gold Revision page 208 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Table 34 – OOB Specifications Parameter Units Limit Electrical Specification Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i Vthresh, OOB Signal Detection Threshold mVppd UIOOB, UI During OOB ps Signaling COMINIT/ COMRESET and COMWAKE ns Transmit Burst Length COMINIT/ COMRESET Transmit Gap ns Length COMWAKE Transmit Gap ns Length Min Nom Max Min Nom Max Min Nom Max Min Nom Max Min Nom Max 50 120 100 - 200 240 646.67 666.67 686.67 75 120 125 - 200 240 646.67 666.67 686.67 103.5 106.7 109.9 310.4 320.0 329.6 103.5 106.7 109.9 75 125 200 646.67 666.67 686.67 Detail Measurement Cross-Ref Cross-Ref Section Section 7.2.2.6.2 7.4.24 7.2.2.6.3 - 7.2.2.6.4 7.2.2.6.1 7.4.25 7.2.2.6.5 7.4.25 7.2.2.6.6 7.4.25 Serial ATA Revision 3.0 Gold Revision page 209 of 663 Parameter Units Limit May COMWAKE Gap Detection ns Windows detect Shall detect Shall not detect May COMINIT/ detect COMRESET Gap Detection ns Shall detect Windows Shall not detect Gen1i Gen1m Gen1x Gen2i Gen2m Gen2x Gen3i Electrical Specification 35 _ T < 175 101.3 _ T _ 112 T < 35 or T `175 175 _ T < 525 304 _ T _ 336 T < 175 or T ` 525 Detail Measurement Cross-Ref Cross-Ref Section Section 7.2.2.6.7 7.4.25 7.2.2.6.8 7.4.25 Serial ATA Revision 3.0 Gold Revision page 210 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.2 Phy Layer Requirements Details 7.2.2.1 General Specifications Details This section contains the details on Table 29 entries. 7.2.2.1.1 Channel Speed A reference value showing the nominal rate of data through the channel. 7.2.2.1.2 Frame Error Rate Frame error rate is the measure of link performance using all the intermediate circuit blocks in the chain from low-level Phy layer, Link layer, through Transport layer. Frame error rate is a system level test, not a compliance test. Error detection is at the frame level using the CRC (Cyclic Redundancy Check) error detection mechanism, and respective reporting to the higher layer levels. 7.2.2.1.3 Unit Interval This is the operating data period (nominal value, architecture specific), excluding jitter. This value includes the long-term frequency accuracy and the Spread Spectrum Clock FM frequency deviation (rounded to 4 places). This is the time interval value of each cycle of the Reference Clock. 7.2.2.1.4 TX Frequency Long Term Stability This specifies the allowed frequency variation from nominal; this does not include frequency variation due to jitter, Spread Spectrum Clocking, or phase noise of the clock source. 7.2.2.1.5 Spread Spectrum Modulation Frequency The modulation frequency of the Spread Spectrum frequency modulation. See further details of Spread Spectrum in section 7.3.3. 7.2.2.1.6 Spread Spectrum Modulation Deviation This is the allowed frequency variation from the nominal Fbaud value in Table 27 when Spread Spectrum Clocking (SSC) is used. This deviation includes the long-term frequency variation of the transmitter clock source, and the SSC frequency modulation on the transmitter output. The frequency variation limits are measured using the SSC profile measurement described in section 7.4.11. See further details of Spread Spectrum in section 7.3.3. 7.2.2.1.7 DC Coupled Common Mode Voltage (Gen1i) The Common mode DC level is defined as [(TX+) + (TX-)]/2 and [(RX+) + (RX-)]/2 measured at the mated connector. This requirement only applies to Gen1i DC-coupled designs (no blocking capacitors) that hold the common-mode DC level at the connector. The four possible common mode biasing configurations shown in Figure 115 below demonstrate that only DC-coupled designs need sustain the specified common-mode level to ensure interoperability. AC coupled designs may allow the DC level at the connector to float. The SATA interfaces defined as Gen1x, Gen2i, Gen2x, and Gen3i shall be AC-coupled and this requirement does not apply to these. Serial ATA Revision 3.0 Gold Revision page 211 of 663 A DC-coupled receiver shall weakly hold the common-mode level of its inputs to the Vcm,dc value specified in Table 29. A DC-coupled transmitter shall transmit with the Vcm,dc value specified in Table 29 while driving into a 100 Ohm differential impedance. 250 mV 50 50 N/A DC to DC Coupling 50 50 >10k 250 mV 250 mV 50 50 N/A DC to AC Coupling 50 50 N/A N/A N/A 50 50 N/A AC to DC Coupling 50 50 >10k 250 mV N/A 50 50 N/A AC to AC Coupling 50 50 N/A N/A NOTE: For N/A, see 7.4.16 and 7.4.30. Figure 115 – Common Mode Biasing Examples for Gen1i (Informative) Serial ATA Revision 3.0 Gold Revision page 212 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.2.1.8 AC Coupled Common Mode Voltage The SATA interface, defined as Gen1i, may be AC or DC coupled as shown in Figure 115. The SATA interfaces defined as Gen1x, Gen2i, Gen2x, and Gen3i shall be AC-coupled. Figure 116 shows an example of a fully AC-coupled system. Compliance points for SATA are defined at the connector. The AC coupled common mode voltage in Table 29 defines the open circuit DC voltage level of each single-ended signal at the IC side of the coupling capacitor in an AC coupled Phy and it shall be met during all possible power and electrical conditions of the Phy including power off and power ramping. Since the Gen1x, Gen2i, Gen2x, and Gen3i specification defines only the signal characteristics as observable at the connector, this value is not applicable to those specifications. The common mode transient requirements defined in Table 29 were determined sufficient to limit stresses on the attached components under transient conditions, which was the sole intent of the AC, coupled common mode voltage requirement. Due to this, the following is true even for Gen1i where Vcm,ac coupled applies: AC coupled common mode voltage levels outside the specified range may be used provided that the transient voltage requirements of Table 29 are met. N/A 50 50 N/A AC to AC Coupling 50 50 N/A N/A NOTE: For N/A, see 7.4.16 and 7.4.30. Figure 116 – Common Mode Biasing for Gen1x, Gen2i, Gen2x, and Gen3i 7.2.2.1.9 Nominal Differential Impedance (Gen1i) The nominal impedance of all components in a SATA system. 7.2.2.1.10 AC Coupling Capacitance The value of the coupling capacitor used in AC coupled implementations. AC coupling is optional for Gen1i and mandatory of Gen1x, Gen2i, Gen2x, and Gen3i. Coupling Capacitor Characteristics (Informative): The physical size of the capacitor should be as small as practical to reduce the capacitance to ground. Body sizes larger than 0603 (or values less than 300 pF) should be avoided since they are likely to result in a failure of the return loss requirements in 7.2.2.2.3, and 7.2.2.3.3. The physical size of the capacitor should be as small as practical to reduce the capacitance to ground. Body sizes larger than 0603 should be avoided, as they are likely to result in a failure of the return loss requirements in Table 30 and Table 31. 7.2.2.1.11 Sequencing Transient Voltage This parameter addresses the transient voltages on the serial data bus during power sequencing and power mode changes. Since either the receiver or the transmitter may be affected by power Serial ATA Revision 3.0 Gold Revision page 213 of 663 sequencing transients, the term "aggressor" is used to indicate the sequencing interface circuit and the term "victim" is used for the interface circuit receiving the transient. In order to limit the voltage and energy seen by the victim receiver or transmitter circuitry during power sequencing, several parameters of the aggressor and victim are involved. Although parameters of the victim, such as common mode voltage and single ended impedance, affect the observed transient, this measurement addresses limiting the aggressor contribution. The aggressor common mode voltage, single ended impedance, and AC coupling capacitor value determine the level of the sequencing transient. This measurement addressed the common mode voltage of the aggressor. The rate of change of the power on or power off ramp also affects this level. The limits provided allow for power up or power down ramps at rates faster than the time constants of the signal lines, although practical systems may not achieve this rate. This measurement shall include the test conditions of power on and power off ramping at the fastest possible rate expected in systems using the Phy, as well as any power mode transitions. 7.2.2.1.12 Sequencing Transient Voltage Lab Load (Gen3i) This parameter addresses the transient voltages on the serial data bus during power sequencing under the test condition of a lab load (see 7.2.2.4 for lab load details). Measuring the transient voltage with a lab load combines the effects of the bias voltage and series termination. Separately measuring the impedance of the circuit is not required. Since some circuits calibrate the impedance after power ramping is compete, measuring impedance during a transient condition becomes challenging. An open circuit voltage measurement, as outlined in 7.4.16, Sequencing Transient Voltage, shall be required to prevent overstressing victim circuits with high impedance common mode voltage. 7.2.2.2 Transmitter Specification Details This section contains the details on Table 30 entries. 7.2.2.2.1 TX Pair Differential Impedance (Gen1i) As seen by a differential TDR with 100 ps (max) edge looking into connector (20%-80%). Measured with TDR in differential mode. 7.2.2.2.2 TX Single-Ended Impedance (Gen1i) As seen by TDR with 100 ps (max) edge looking into connector (20%-80%). The TDR is set to produce simultaneous positive pulses on both signals of the TX pair. Single-ended impedance is the resulting (even mode) impedance of each signal. Both signals shall meet the single ended impedance requirement. This requirement shall be met during all possible power and electrical conditions of the Phy including power off and power ramping. Serial ATA Revision 3.0 Gold Revision page 214 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.2.2.3 TX and RX Differential Mode Return Loss (Gen2i, Gen2m) (Gen1i, Gen1m alternate) This specification describes transmitter output impedance and receiver input impedance in terms of both the peak value of a reflection given an incident step of known risetime and also in terms of return loss. The return loss measurement shall be sufficient to verify compliance with Gen1 and Gen2 requirements. In order to ensure Gen1 designs passing the TDR differential impedance method as previously required are not invalidated due to this change, either method shall be sufficient to verify compliance with Gen 1 requirements. Verification of compliance by both methods shall not be required. The differential mode return loss is defined as the ratio (expressed in dB) of differential mode incident power to differential mode reflected power both at a 100 Ohm impedance level. In the system environment the purpose of controlling the return loss of devices and hosts is to limit signal reflections that cause data dependent jitter. These signal reflections in question are over and above those that exist in compliance testing when connected to a matched source or load. .15 .30 .60 1.2 2.4 5.0 Frequency (GHz) Figure 117 – Differential Return Loss Limits Serial ATA Revision 3.0 Gold Revision page 215 of 663 7.2.2.2.4 TX Common Mode Return Loss (Gen2i, Gen2m) The common mode return loss is defined as the ratio (expressed in dB) of common mode incident power to common mode reflected power both at a 25 Ohm impedance level. The intended signal propagation mode in SATA is the differential mode. However, imperfections in the system create some coupling between the common and differential modes. This has three consequences: radiated emissions, noise susceptibility, and signal degradation. Common mode reflections exacerbate these impairments. The common mode return loss is a bound on the magnitude of common mode reflections in the system. .15 .30 .60 1.2 2.4 5.0 Frequency (GHz) Figure 118 – Common Mode Return Loss Limits 7.2.2.2.5 TX Impedance Balance (Gen2i, Gen2m, Gen3i) Impedance balance is defined as the ratio (expressed in dB) of common mode incident power at a 100 Ohm impedance level to differential mode reflected power at a 25 Ohm impedance level. The impedance balance is a bound on the coupling between common and differential modes. .15 .30 .60 1.2 2.4 5.0 Frequency (GHz) Figure 119 – Impedance Balance Limits Serial ATA Revision 3.0 Gold Revision page 216 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.2.2.6 TX and RX Differential Mode Return Loss (Gen3i) This specification describes transmitter output impedance and receiver input impedance in terms of return loss. Return loss is specified as starting and ending points, with a defined slope between. The return loss shall remain below the line shown in Figure 120, from the starting frequency to the ending frequency. The differential mode return loss is defined as the ratio (expressed in dB) of differential mode incident power to differential mode reflected power both at a 100 Ohm impedance level. In the system environment the purpose of controlling the return loss of devices and hosts is to limit signal reflections that cause data dependent jitter. These signal reflections in question are over and above those that exist in compliance testing when connected to a matched source or load. RL (dB) - RL (dB) TX RX 0.30 0.30 Slope 13 dB/dec 3.0 Log Freque3n.c0y (GHz) 6.0 Log Frequency (GHz) Figure 120 – Differential Return Loss Limits,Gen3i, TX and RX Serial ATA Revision 3.0 Gold Revision page 217 of 663 Transmitted Signal Requirements Details This section contains the details on Table 31 entries. 7.2.2.2.7 TX Differential Output Voltage The differential voltage [(TX+) – (TX-)] measured at the Transmitter shall comply with the respective electrical specifications of section 7.2. This is measured at mated Serial ATA connector on transmit side including any pre-emphasis. For Gen3i the maximum differential output voltage is likewise measured at the TX compliance point, but the minimum differential output voltage is measured after the Gen3i CIC. (see section 7.4.3) 7.2.2.2.8 TX Minimum Voltage Measurement Interval The point within a UI where the signal shall meet minimum levels. 7.2.2.2.9 TX Rise/Fall Time Rise times and fall times are measured between 20% and 80% of the signal, see Figure 121. The rise and fall time requirement tr/f applies to differential transitions (TX+ – TX-), for both normal and OOB signaling. Differential Data Lines Rise Time 80% 20% Tr Fall Time 80% 20% Tf Figure 121 – Signal Rise and Fall Times Serial ATA Revision 3.0 Gold Revision page 218 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.2.2.10 TX Differential Skew TX Differential Skew is the time difference between the single-ended mid-point of the TX+ signal rising/falling edge, and the single-ended mid-point of the TX- signal falling/rising edge. It is an important parameter to control as excessive skew may result in increased high frequency jitter and common mode noise levels seen at the far end of the interconnect. The effects on the receiver are addressed in more detail in section 7.2.2.5.4. Excessive TX Differential Skew also increases EMI emissions. TX(+) MINIMAL-SKEW TX(-) Diff-Rx TX(+) LATE-SKEW TX(-) TX(+) EARLY-SKEW TX(-) Diff-Rx Skew Skew Diff-Rx Figure 122 – TX Intra-Pair Skew Serial ATA Revision 3.0 Gold Revision page 219 of 663 7.2.2.2.11 TX AC Common Mode Voltage (Gen2i, Gen1x, Gen2x) Maximum sinusoidal amplitude of common mode signal measured at the transmitter connector. The Transmitter shall comply to the electrical specifications of section 7.2, when subjected to a sinusoidal interfering signal with peak-to-peak voltage, and swept from the frequency range extremes, at a sweep rate period no shorter than 33.33 us. 7.2.2.2.12 TX AC Common Mode Voltage (Gen3i) Maximum sinusoidal amplitude of common mode signal measured at the transmitter connector. The Transmitter shall not deliver more output voltage than that specified in Table 30 using the common mode voltage measuring technique defined in section 7.4.21. 7.2.2.2.13 Common Mode Transient Settle Time (Gen1i) In Gen1i transmitters, this is the maximum time for common-mode transients to settle to within 25 mV of their previous state common mode voltage during transitions to and from the idle bus condition. 7.2.2.2.14 OOB Differential Delta (Gen2i,Gen3i, Gen2m,Gen1x, Gen2x) The difference between the average differential value during the idle bus condition and the average differential value during burst on transitions to and from the idle bus condition. During OOB transmission, imperfections and asymmetries in transmitters may generate error signals that impair proper detection by a receiver. The OOB Differential Delta describes an error from the difference in transmitter DC offset during the idle and active conditions. Since the transmitter is alternating between idle and active conditions each with different DC offsets, an AC error voltage is generated which is a square wave at about 1 / (2*106 ns) = 4.7 MHz. The AC error voltage propagates through the interconnect and causes an offset in the receiver OOB detector. V (t) DVdiffOOB Vmax V (t) = 0 Vmin Vmax Vmin Figure 123 – OOB Differential Delta (at Compliance Point with AC Coupling) 7.2.2.2.15 OOB Common Mode Delta (Gen2i, Gen3i,Gen1x, Gen2x) The difference between the common mode value during the idle bus condition and the common mode value during a burst on transitions to and from the idle bus condition. 7.2.2.2.16 TX Rise/Fall Imbalance Serial ATA Revision 3.0 Gold Revision page 220 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization The match in the rise of TX+ and fall of TX- determined by the functions: absolute value (TX+,rise – TX-,fall)/average where average is (TX+,rise + TX-,fall)/2 and all rise and fall times are 20-80%. The match in the fall of TX+ and rise of TX- determined by the function: absolute value (TX+,fall – TX-,rise)/average where average is (TX+,fall + TX-,rise)/2 and all rise and fall times are 20-80%. 7.2.2.2.17 TX Amplitude Imbalance (Gen2i, Gen1x, Gen2x) The match in the amplitudes of TX+ and TX- determined by the function: absolute value (TX+ amplitude - TX- amplitude)/average where average is (TX+ amplitude + TX- amplitude)/2 and all amplitudes are determined by mode (most prevalent) voltage. 7.2.2.2.18 Clock-to-Data Transmit Jitter (Gen1i, Gen1m, Gen1x, Gen2i, Gen2m, Gen2x, Gen3i) Transmitters shall meet the jitter specifications for the Reference Clock characteristics specified in each case. Table 31 shows the maximum amount of jitter that a transmitter may generate and still be SATA compliant and section 7.4.8 describes the measurement. Since this specification places the compliance point afterthe connector, any jitter generated at the package connection, on the printed circuit board, and at the board connector shall be included in the measurement. 7.2.2.3 Receiver Specification Details This section contains the details on Table 32 entries. 7.2.2.3.1 RX Pair Differential Impedance (Gen1i) As seen by a differential TDR with 100 ps (max) edge looking into connector (20%-80%). Measured with TDR in differential mode. 7.2.2.3.2 RX Single-Ended Impedance (Gen1i) As seen by TDR with 100 ps (max) edge looking into connector (20%-80%). TDR set to produce simultaneous positive pulses on both signals of the RX pair. Single-ended impedance is the resulting (even mode) impedance of each signal. Both signals shall meet the single ended impedance requirement. This requirement shall be met during all possible power and electrical conditions of the Phy including power off and power ramping. 7.2.2.3.3 RX Differential Mode Return Loss (Gen2i, Gen2m) Receiver differential mode return loss is measured similar to transmitter differential mode return loss. See details in section 7.2.2.2.3. 7.2.2.3.4 RX Common Mode Return Loss (Gen2i, Gen2m) Receiver common mode return loss is measured similar to transmitter common mode return loss. See details in section 7.2.2.2.4. 7.2.2.3.5 RX Impedance Balance (Gen2i, Gen2m) Receiver impedance balance is measured similar to transmitter impedance balance. See details in section 7.2.2.2.5. Serial ATA Revision 3.0 Gold Revision page 221 of 663 7.2.2.3.6 RX Differential Mode Return Loss (Gen3i) Receiver differential mode return loss is measured similar to transmitter differential mode return loss. See details in section 7.2.2.2.6. 7.2.2.4 Lab Load Details The Lab Load is an electrical test system connected to the unit under test. The serial transmitter signals from the UUT are connected through a “mated SATA connector pair” module consisting of connectors and cables to a HBWS terminated into two 50 Ohms (plus and minus 5 Ohms) loads. The cables shall be 50 Ohms (plus and minus 5 Ohms) impedance. The inputs of the Laboratory Load (from the back of the mated SATA connector to the 50 Ohm load within the HBWS) shall have an individual return loss greater than 20 dB over a bandwidth of 100 MHz to 5.0 GHz, and greater than 10 dB from 5 GHz to 8 GHz. The skew between the channels under test shall have 10 Picoseconds or less after compensation. The LL consists of this total assembly. The LL does not include the “other half of the mated connector” which is considered part of the UUT but is physically located on the LL. The LL is shown in Figure 124. Test Signals Compliance Point SATA Adapter (Receptacle) SATA Mated Connector Pair DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms 50 Ohms HBWS / JMD Laboratory Load (LL) Figure 124 – LL Laboratory Load The electrical characteristics of the LL shall be greater than the required performance of the parameter being measured such that the LL effects of the on the parameter under test may be successfully compensated for, or de-embedded, in the measured data. 7.2.2.5 Lab-Sourced Signal Details This section contains the details on Table 33 entries. The Laboratory Sourced Signal or Lab-Sourced Signal is an instrument and electrical test system connected to the unit under test. The LSS provides a signal to the UUT at the defined impedance level of 100 Ohms differential and 25 Ohms common mode. The LSS may also provide a SATA signal with impairments such as jitter and common mode noise. The LSS may consist of several instruments in combination with fixturing to create a signal with impairments. Serial ATA Revision 3.0 Gold Revision page 222 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization RX Signals to UUT Compliance Point SATA Adapter (Receptacle) SATA Mated Connector Pair DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms 50 Ohms Data Signal Source Lab Sourced Signal Figure 125 – LSS Lab-Sourced Signal The Lab-Sourced signal is a laboratory generated signal which is calibrated into an impedance matched load of 100 Ohms differential and 25 Ohms common mode and then applied to the RX+ and RX- signals of the Receiver Under Test.In the case of Gen3i, the Gen3i CIC is inserted in the signal path applied to the RX. (see section 7.4.12) The load used to calibrate the LSS shall have an individual return loss greater than 20 dB over a bandwidth of 100 MHz to 5.0 GHz, and greater than 10 dB from 5 GHz to 8 GHz. During calibration, the characteristics of the Lab-Sourced signal shall comply with the specifications of Table 33. When this signal is then applied to the Receiver Under Test the Frame Error Rate specifications of Table 29 shall be met. Serial ATA Revision 3.0 Gold Revision page 223 of 663 7.2.2.5.1 RX Differential Input Voltage The RX Differential Input Voltage is the range of input voltage under compliance test conditions that a receiver shall operate to the required link performance level. This is one range of input conditions a receiver shall tolerate (see section 7.4.11). The Serial ATA system has a transmitter and receiver with impedances near the nominal system impedance of 100 Ohms. The voltage at compliance points is strongly dependent on the transmitter, receiver, and interconnect impedances. The RX differential input voltage is delivered from an impedance matched signal source into a matched load (see Figure 126). When the actual receiver is substituted for the matched load, the voltage changes by an amount that is receiver design dependent. This change is part of the receiver design burden. Rs = 100 ohms VdiffRX Vsrc RL = 100 ohms Figure 126 – RX Differential Input Voltage Conditions The RX differential input voltage does not describe the voltage delivered from the interconnect. The interconnect output impedance is not equal to the nominal system impedance over the entire frequency range. It is not the voltage at a matched load delivered from interconnects, nor is it the voltage at a receiver delivered from the interconnect. Example calculations demonstrating this are given in section 7.4.5. 7.2.2.5.2 RX Rise/Fall Times Rise times and fall times are measured between 20% and 80% of the signal. The rise and fall time requirement t20-80RX applies to differential transitions (applied to RX+ and RX- for Gen1 and Gen2). For Gen3i the maximum and minimum RX rise time and fall time requirements are applied to the Data Signal Source before the Gen3i CIC. (see Section 7.4.12) 7.2.2.5.3 RX Minimum Voltage Measurement Interval The point in a UI that the signal shall meet minimum levels. Serial ATA Revision 3.0 Gold Revision page 224 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.2.5.4 RX Differential Skew (Gen2i, Gen1x, Gen2x, Gen3i) RX Differential Skew is the time difference between the single-ended mid-point of the RX+ signal rising/falling edge, and the single-ended mid-point of the RX- signal falling/rising edge, as measured at the RX connector. The receiver should tolerate the RX skew levels per Table 33, as generated by a Lab-Sourced Signal. The receiver differential skew is an important parameter to consider, as excessive skew may result in increased high frequency jitter and high frequency common mode noise seen at the highspeed differential receiver. Figure 127 depicts how late and early skew signaling affect the time at which the differential receiver resolves the differential input signals. For the minimal skew case, when the single-ended slew rate is at maximum, at the crossover, the UI width is also maximized. However, this is not the case for the early and late skew cases. The high frequency common mode noise is a result of the rapid changing of the operating point of the high-speed receiver. Section 7.4.15 describes the applicable measurement method that should be used to calibrate the intentionally skewed Lab-Sourced Signal output into the receiver. RX(+) MINIMAL-SKEW RX(-) Diff-Rx RX(+) LATE-SKEW RX(-) RX(+) EARLY-SKEW RX(-) Diff-Rx Skew Skew Diff-Rx Figure 127 – RX Intra-Pair Skew Serial ATA Revision 3.0 Gold Revision page 225 of 663 7.2.2.5.5 RX AC Common Mode Voltage (Gen2i, Gen1x, Gen2x) Max peak-to-peak sinusoidal amplitude of AC common mode signal [(RX+) + (RX-)]/2. The Receiver shall operate to within the frame error rate cited in Table 29, when subjected to a sinusoidal common mode interfering signal with peak-to-peak voltage VcmRX,ac defined in Table 33 and swept across the frequency range, fcm,acRX, defined in Table 33 at a sweep rate period no shorter than 33.33 us. 7.2.2.5.6 AC Common Mode Frequency All receivers shall be able to tolerate sinusoidal common-mode noise components inside this frequency range with amplitude of Vcm,acRX. 7.2.2.5.7 Clock-Data Receiver Jitter Tolerance (Gen1i, Gen1m, Gen2i, Gen2m, Gen1x, Gen2x) Jitter tolerance is the ability of the receiver to recover data in the presence of jitter. The minimum amount of jitter that a receiver shall be able to operate is the jitter tolerance specification provided in Table 33 and section 7.4.11 describes the measurement for Gen1 and Gen2. 7.2.2.5.8 Clock-Data Receiver Jitter Tolerance (Gen3i) See 7.4.12 for Gen3i jitter tolerance measurement details. 7.2.2.6 OOB Specifications Details This section provides details on Table 34. 7.2.2.6.1 OOB Signal Burst Generation Out-Of-Band (OOB) signals are groupings of waveforms made up of low frequency, waveform bursts, interspersed with idle gaps. These do not appear during normal data stream transfers, but are used to communicate low frequency identification information during initial notification and calibration periods, before data transfers begin. The OOB signal consists of a defined amount of idle time followed by a defined amount of burst time, this combination repeated for multiple iterations. During the idle time, the physical link carries D.C. idle. During the burst time, the physical link carries low frequency signal transitions intended to be repetitive waveshapes for envelope detection means. These bursts are translated into ON/OFF times as a means for very low speed communication. The OOB signal OFF time is determined by the length of idle time between the waveform bursts. The signal patterns used during the OOB bursts shall be comprised of D24.3 characters (preferred) or ALIGN primitives (allowed), transmitted at the Gen1 rate. The OOB burst is only required to generate an envelope for detection by A.C. coupled detection circuitry. A burst of D24.3 characters at Gen1 speed is equivalent to a square wave pattern that is a ‘1’ for 2 UIoob periods and then a ‘0’ for 2 UIoob periods, or simply, a squarewave with a period of 2.66 nsec. All data speed generations shall use the Gen1 OOB burst speed, establishing a singular requirement for all OOB detection circuitry. 7.2.2.6.2 OOB Signal Detection Threshold Differential signal amplitude detected as activity by the squelch detector during OOB signaling. VdiffRX signals less than the minimum Vthresh defined in Table 34 shall not be detected as activity. Signal levels greater than the maximum Vthresh defined in Table 34 shall be detected as activity. Serial ATA Revision 3.0 Gold Revision page 226 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.2.6.3 UI During OOB Signaling (UIOOB) Average data period during OOB burst transmission (at Gen1 speed +/- 3%). 7.2.2.6.4 COMINIT/COMRESET and COMWAKE Transmit Burst Length Burst length in ns, as measured from the first crossing point (+100mV or –100mV) of the burst to the last crossing point (+100mV or –100mV) of the burst. 7.2.2.6.5 COMINIT/COMRESET Transmit Gap Length Gap length in ns, as measured from the last crossing point (+100mV or –100mV) of one COMINIT/COMRESET burst to the first crossing point (+100mV or –100mV) of the following COMINIT/COMRESET burst. 7.2.2.6.6 COMWAKE Transmit Gap Length Gap length in ns, as measured from the last crossing point (+100mV or –100mV) of one COMWAKE burst to the first crossing point (+100mV or –100mV) of the following COMWAKE burst. 7.2.2.6.7 COMWAKE Gap Detection Windows Three timing ranges defining the validation and invalidation of COMWAKE gaps; see Table 34. Any OOB gap between bursts falling in the defined “may detect” range may be recognized as a valid COMWAKE gap. Any OOB gap between bursts falling in the “shall detect” range shall be recognized as a valid COMWAKE gap. Any OOB gap between bursts falling in the “shall not detect” ranges shall be recognized as an invalid COMWAKE gap (shall not be recognized as a valid COMWAKE gap). 7.2.2.6.8 COMINIT/COMRESET Gap Detection Windows Three timing ranges defining the validation and invalidation of COMINIT and COMRESET gaps; see Table 34. Any OOB gap between bursts falling in the defined “may detect” range may be recognized as a valid COMINIT or COMRESET gap. Any OOB gap between bursts falling in the “shall detect” range shall be recognized as a valid COMINIT or COMRESET gap. Any OOB gap between bursts falling in the “shall not detect” ranges shall be recognized as an invalid COMINIT or COMRESET gap (shall not be recognized as a valid COMINIT or COMRESET gap). 7.2.3 Loopback In addition to meeting all electrical specifications in Table 29 through Table 34, all Hosts and Devices shall provide Far-End Retimed Loopback mode. Two other loopback modes are optional but if implemented shall comply with sections 7.2.3.2 and 7.2.3.3. a) Far-End Retimed - b) Far-End Analog - c) Near-End Analog (Effectively Retimed) - Required Optional Optional Serial ATA Revision 3.0 Gold Revision page 227 of 663 7.2.3.1 Far-End Retimed Figure 128 below, illustrates the scope, at the architectural block diagram level, of the Far-End Retimed loopback. As this loopback scheme needs a specific action from the far-end connected interface, this mode shall be entered by way of the BIST Activate FIS described in section 10.3.9. The Far-End Interface shall remain in this Far-End Retimed Loopback, until receipt of the COMRESET/COMINIT OOB Signaling sequence. As a minimum, Far-End Retimed Loopback shall involve far-end circuitry such that the data stream, at the Far-End interface, is extracted by the deserializer and data recovery circuit (DRC) before being sent back through the serializer and transmitter with appropriately inserted retiming ALIGNP primitives as described in section 7.6. The data may be decoded and descrambled in order to provide testing coverage for those portions of the device, provided the data is rescrambled using the same sequence of scrambler syndromes. The returned data shall be the same as the received data with the exception that the returned data may be encoded with different starting running disparity. TX+ O TX- O Fixed Pattern Source Fixed Pattern Detect Analog Front End Data Extraction Block RX+ I I RX- I RX+ I RX- Data Extraction Block Analog Front End Silicon Loopback TX+ O O TX- Figure 128 – Far-End Retimed Loopback Serial ATA Revision 3.0 Gold Revision page 228 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.3.2 Far-End Analog (Optional) Figure 129 illustrates the scope, at the architectural block diagram level, of the Far-End Analog Loopback. As this loopback scheme needs a specific action from the far-end connected interface, this mode shall be entered by way of the BIST Activate FIS described in section 10.3.9. The Far-End Interface shall remain in this Far-End Analog Loopback mode, until receipt of a COMRESET or COMINIT. TX+ O TX- O Fixed Pattern Source Fixed Pattern Detect Analog Front End Data Extraction Block RX+ I I RX- I RX+ I RX- Analog Front End TX+ O O TX- Figure 129 – Far-End Analog Loopback Data Extraction Block Silicon Loopback Serial ATA Revision 3.0 Gold Revision page 229 of 663 7.2.3.3 Near-End Analog (Optional) Figure 130 illustrates the scope, at the architectural block diagram level, of the Near-End Analog Loopback. This loopback scheme needs the far-end connected interface to be in a nontransmitting mode, such as Slumber, or Partial interface power management states. Entry to and exit from this mode is vendor specific. + O TX+* - O TX-* Fixed Pattern Source Fixed Pattern Detect Analog Front End Data Extraction Block + - I RX+* I RX-* Silicon Loopback Figure 130 – Near-End Analog Loopback 7.2.4 Test Pattern Requirements Test patterns shall be used for compliance testing of the Serial ATA interfaces. This section defines various patterns to be used in compliance testing. Individual sections within section 7.4 define which patterns are to be used for specific tests. The patterns are classified in two categories: a) Non-compliant patterns b) Compliant patterns Non-compliant patterns are those patterns that are used for baseline jitter measurements, and assessment of signal quality, given specified stimulus. These patterns do not comply with the required FIS formats, but are just a repeated selected set of 8b/10b characters. Compliant patterns are those specified patterns that contain the leading SOFP primitive, the specified pattern as data content, and trailing CRCP and EOFP primitives. There is no suppression of the dual-consecutive ALIGNP primitive during stimulus with this class of pattern. Serial ATA Revision 3.0 Gold Revision page 230 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Test patterns cited in this section are used as stimulus to verify interface compliance and signal integrity, using the following test models: a) Non-compliant test patterns for jitter measurements, physical connection media tests, and electrical parameter testing. b) Compliant test patterns for frame error rate testing and in-system tests. 7.2.4.1 Non-Compliant Patterns Electrical parameters of section 7.2 shall be verified using the patterns identified in the measurement method section 7.4. a) Lone Bit Patterns as per section 7.2.4.3.5. b) High Frequency Test Pattern as per section 4.1.59. c) Mid Frequency Test Pattern as per section 4.1.78. d) Low Frequency Test Pattern as per section 4.1.75. 7.2.4.2 Compliant Frame Patterns The frame error rates specified in section 7.4.1.2 shall be tested for compliance when subjected to any implementation-determined worst-case compliant patterns, as well as the following set of compliant patterns: a) Compliant Lone Bit Patterns as per section 7.2.4.3.5. b) Compliant composite patterns as per section 7.2.4.3.6. Where the qualifying prefix term "compliant" signifies transmission of the cited pattern encapsulated in payload of a Data FIS, and used in a Serial ATA operational transmission context. Note that the cited patterns should appear on the wire, and the N parameters of the reference patterns shall be extended to achieve the maximum frame length. These compliant patterns contain the necessary SOFP leading primitive, the Dword header containing the FIS Type indicating a Data FIS, the specified test pattern, the calculated CRC, and the trailing EOFP, as shown in Figure 131. To generate these patterns on the SATA link, scrambling needs to be taken into account. SOFP Data FIS Header Specified Test Pattern CRC Figure 131 – Compliant Test Patterns EOFP Serial ATA Revision 3.0 Gold Revision page 231 of 663 7.2.4.3 Test Bit Patterns and Sequence Characteristics There are various types of bit sequence patterns that emphasize low/high transition density patterns, as well as low/high frequency patterns. a) Low transition density patterns (LTDP) are those patterns containing long runs of ones and zeroes, intended to create inter-symbol interference by varying the excursion times at either extreme of the differential signaling levels. b) High transition density patterns (HTDP) are those patterns containing short runs of ones and zeroes, also intended to create inter-symbol interference. c) Low frequency spectral content patterns (LFSCP) are a good test of the input high pass filter circuitry, more specifically, introduced amplitude signal distortion, due to a marginal design. These bit patterns are a better test than those bit patterns having high frequency spectral content. d) Simultaneous switching outputs patterns (SSOP) are achieved by transmitting alternating ones complement bit patterns (10-bits) for recovery at the receiver. These patterns create worst case power supply, or chip substrate, noise, and are achieved by selecting bit test pattern sequences that maximize current extremes at the recovered bit pattern parallel interface. These patterns induce Ldi/dt noise into substrate supply, and are a good test of the receiver circuitry. e) The lone-bit patterns (LBP) are comprised of the consecutive combination of certain 10b patterns that result in a lone-bit. These patterns create a condition where the preceding 4-bit run-length results in minimum amplitude of the lone-bit as well as its time-width in comparison to its surrounding segments. This is often the worst-case condition that the receiving data recovery circuits may encounter. f) The intent of random bit patterns is to provide those patterns containing sufficiently broad spectral content, and minimal peaking, that should be used for both component, and system level architecture measurement of jitter output, and bit-errorrate performance. These patterns are also intended to be the common baseline pattern stimulus, for system/component vendor comparative testing, attributing the transmit jitter output measurement to the component performance, and not to the spectral profile of the data pattern used. The test patterns illustrated in the following sections are indicated to start with negative running disparity for illustrative purposes only in order to convey the encoded 10b patterns transmitted for each sequence. Serial ATA Revision 3.0 Gold Revision page 232 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.4.3.1 Low Transition Density Patterns (LTDP) Low transition density bit patterns (LTDP), as shown in Table 35 and Table 36 below, contain long runs of ones and zeroes. These patterns create jitter due to inter-symbol interference. This is aggravated when part of the composite pattern described in section 7.2.4.3.6. Bit sequences are shown for both cases, where the starting running disparity is negative or positive. Table 35 – Low Transition Density Pattern (LTDP) Starting with RDTransmission Order D17.7(F1h)- D30.7(FEh)+ D7.1(27h)+ D14.7(EEh)+ - 1000 1101 1110 0001 1110 0001 1110 0101 1100 1000 - 8 D E 1 E 1 E 5 C 8 D30.7(FEh)- D7.6(C7h)- D30.3(7Eh)- D30.3(7Eh)+ - - 0111 1000 0111 1000 0110 0111 1000 1110 0001 1100 7 8 7 8 6 7 8 E 1 C D30.3(7Eh)- D30.3(7Eh)+ D30.3(7Eh)- D30.3(7Eh)+ - - 0111 1000 1110 0001 1100 0111 1000 1110 0001 1100 7 8 E 1 C 7 8 E 1 C Above Dword is repeated a total of 2045 times for long version. Above Dword is repeated a total of 125 times for short version. D3.7(E3h)- D28.7(FCh)+ D3.7(E3h)- D28.7(FCh)+ - - 1100 0111 1000 1110 0001 1100 0111 1000 1110 0001 C 7 8 E 1 C 7 8 E 1 Long version total: 3 + 2045 = 2048 Dwords. Short version total: 3 + 125 = 128 Dwords. Serial ATA Revision 3.0 Gold Revision page 233 of 663 Table 36 – Low Transition Density Pattern (LTDP) starting with RD+ Transmission Order + D14.7(EEh)+ D30.7(FEh)- D7.6(C7h)+ D17.7(F1h)- + 0111 0010 0001 1110 0001 1110 0001 1010 0011 0111 7 2 1 E 1 E 1 A 3 7 + D30.7(FEh)+ D7.1(27h)+ D30.3(7Eh)+ D30.3(7Eh)- + 1000 0111 1000 0111 1001 1000 0111 0001 1110 0011 8 7 8 7 9 8 7 1 E 3 + D30.3(7Eh)+ D30.3(7Eh)- D30.3(7Eh)+ D30.3(7Eh)- + 1000 0111 0001 1110 0011 1000 0111 0001 1110 0011 8 7 1 E 3 8 7 1 E 3 Above Dword is repeated a total of 2045 times for long version. Above Dword is repeated a total of 125 times for short version. + D28.7(FCh)+ D3.7(E3h)- D28.7(FCh)+ D3.7(E3h)- + 0011 1000 0111 0001 1110 0011 1000 0111 0001 1110 3 8 7 1 E 3 8 7 1 E Long version total: 3 + 2045 = 2048 Dwords Short version total: 3 + 125 = 128 Dwords Serial ATA Revision 3.0 Gold Revision page 234 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.4.3.2 High Transition Density Patterns (HTDP) High transition density patterns are those patterns containing short runs of ones and zeroes, as shown in Table 37 and Table 38. These patterns create jitter due to inter-symbol interference, becoming more pronounced when part of the composite pattern described in section 7.2.4.3.6. There are two types of high-transition density patterns of interest: a) Half-rate high transition density bit pattern sequence b) Quarter-rate high transition density bit pattern sequence Both types are used in the high transition density test pattern. Bit sequences are shown for both cases, where the starting running disparity is negative or positive. Table 37 – High Transition Density Pattern (HTDP) Starting with RD– Transmission Order - D21.5(B5h)- D21.5(B5h)- D21.5(B5h)- D21.5(B5h)- - 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 A A A A A A A A A A Above Dword is repeated a total of 512 times for long version. Above Dword is repeated a total of 32 times for short version. - D24.3(78h)- D24.3(78h)+ D24.3(78h)- D24.3(78h)+ - 1100 1100 1100 1100 1100 1100 1100 1100 1100 1100 C C C C C C C C C C Above Dword is repeated a total of 512 times for long version. Above Dword is repeated a total of 32 times for short version. - D10.2(4Ah)- D10.2(4Ah)- D10.2(4Ah)- D10.2(4Ah)- - 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 5 5 5 5 5 5 5 5 5 5 Above Dword is repeated a total of 512 times for long version. Above Dword is repeated a total of 32 times for short version. - D25.6(D9h)- D6.1(26h)+ D25.6(D9h)- D6.1(26h)+ - 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 9 9 9 9 9 9 9 9 9 9 Above Dword is repeated a total of 512 times for long version. Above Dword is repeated a total of 32 times for short version. Long version total: 4 * 512 = 2048 Dwords Short version total: 4 * 32 = 128 Dwords Serial ATA Revision 3.0 Gold Revision page 235 of 663 Table 38 – High Transition Density Pattern (HTDP) Starting with RD+ Transmission Order D21.5(B5h)+ D21.5(B5h)+ D21.5(B5h)+ D21.5(B5h)+ + 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 + A A A A A A A A A A Above Dword is repeated a total of 512 times for long version. Above Dword is repeated a total of 32 times for short version. D24.3(78h)+ D24.3(78h)+ D24.3(78h)+ D24.3(78h)+ + 0011 0011 0011 0011 0011 0011 0011 0011 0011 0011 + 3 3 3 3 3 3 3 3 3 3 Above Dword is repeated a total of 512 times for long version. Above Dword is repeated a total of 32 times for short version. D10.2(4Ah)+ D10.2(4Ah)+ D10.2(4Ah)+ D10.2(4Ah)+ + 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 + 5 5 5 5 5 5 5 5 5 5 Above Dword is repeated a total of 512 times for long version. Above Dword is repeated a total of 32 times for short version. D25.6(D9h)+ D6.1(26h)+ D25.6(D9h)+ D6.1(26h)+ + 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 + 9 9 9 9 9 9 9 9 9 9 Above Dword is repeated a total of 512 times for long version. Above Dword is repeated a total of 32 times for short version. Long version total: 4 * 512 = 2048 Dwords Short version total: 4 * 32 = 128 Dwords Serial ATA Revision 3.0 Gold Revision page 236 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.4.3.3 Low Frequency Spectral Content Pattern (LFSCP) Bit patterns that contain low frequency spectral components, as shown in Table 39 and Table 40, are a good test of the interconnect transmission, especially any AC coupling capacitors. Poor transmission through these components introduces signal distortion shown by this test pattern. Bit sequences are shown for both cases, where the starting running disparity is negative or positive. Table 39 – Low Frequency Spectral Content Pattern (LFSCP) Starting with RD– Transmission Order D20.2(54h)- D20.2(54h)- D20.2(54h)- D20.2(54h)- - 0010 1101 0100 1011 0101 0010 1101 0100 1011 0101 - 2 D 4 B 5 2 D 4 B 5 Above Dword is repeated a total of 1023 times for long version. Above Dword is repeated a total of 63 times for short version. D20.2(54h)- D20.7(F4h)- D11.5(ABh)+ D11.5(ABh)+ - 0010 1101 0100 1011 0111 1101 0010 1011 0100 1010 + 2 D 4 B 7 D 2 B 4 A D11.5(ABh)+ D11.5(ABh)+ D11.5(ABh)+ D11.5(ABh)+ + 1101 0010 1011 0100 1010 1101 0010 1011 0100 1010 + D 2 B 4 A D 2 B 4 A Above Dword is repeated a total of 1023 times for long version. Above Dword is repeated a total of 63 times for short version. D11.5(ABh)+ D11.7(EBh)+ D20.2.(54h)- D20.2(54h)- + 1101 0010 1011 0100 1000 0010 1101 0100 1011 0101 - D 2 B 4 8 2 D 4 B 5 Long version total: 2 + 2 * 1023 = 2048 Dwords. 4095 bytes of D11.5, 4095 bytes of D20.2. 1 D11.7 transitional byte including 0000010 run, 1 D20.7 transitional byte including 1111101 run. Short version total: 2 + 2 * 63 = 128 Dwords 255 bytes of D11.5, 255 bytes of D20.2 1 D11.7 transitional byte including 0000010 run, 1 D20.7 transitional byte including 1111101 run Serial ATA Revision 3.0 Gold Revision page 237 of 663 Table 40 – Low Frequency Spectral Content Pattern (LFSCP) Starting with RD+ Transmission Order D11.5(ABh)+ D11.5(ABh)+ D11.5(ABh)+ D11.5(ABh)+ + 1101 0010 1011 0100 1010 1101 0010 1011 0100 1010 + D 2 B 4 A D 2 B 4 A Above Dword is repeated a total of 1023 times. Above Dword is repeated a total of 63 times for short version. D11.5(ABh)+ D11.7(EBh)+ D20.2.(54h)- D20.2(54h)- + 1101 0010 1011 0100 1000 0010 1101 0100 1011 0101 - D 2 B 4 8 2 D 4 B 5 D20.2(54h)- D20.2(54h)- D20.2(54h)- D20.2(54h)- - 0010 1101 0100 1011 0101 0010 1101 0100 1011 0101 - 2 D 4 B 5 2 D 4 B 5 Above Dword is repeated a total of 1023 times. Above Dword is repeated a total of 63 times for short version. D20.2(54h)- D20.7(F4h)- D11.5(ABh)+ D11.5(ABh)+ - 0010 1101 0100 1011 0111 1101 0010 1011 0100 1010 + 2 D 4 B 7 D 2 B 4 A Long version total: 2 + 2 * 1023 = 2048 Dwords 4095 bytes of D11.5, 4095 bytes of D20.2 1 D11.7 transitional byte including 0000010 run, 1 D20.7 transitional byte including 1111101 run Short version total: 2 + 2 * 63 = 128 Dwords 255 bytes of D11.5, 255 bytes of D20.2 Serial ATA Revision 3.0 Gold Revision page 238 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.4.3.4 Simultaneous Switching Outputs Pattern (SSOP) The simultaneous switching outputs bit pattern (SSOP), shown in Table 41 and Table 42, induces inductive switching (Ldi/dt) noise into substrate supply of a receiver providing a good test of noise control. The SSOP pattern, alternating 1's complement bit patterns (10-bits), are applied to a receiver. Bit sequences are shown for both cases, where the starting running disparity is negative or positive. Table 41 – Simultaneous Switching Outputs Pattern (SSOP) Starting with RD– Transmission Order D31.3(7Fh)- D31.3(7Fh)+ D31.3(7Fh)- D31.3(7Fh)+ - 1010 1100 1101 0100 1100 1010 1100 1101 0100 1100 - A C D 4 C A C D 4 C Above Dword is repeated a total of 2048 times for long version. Above Dword is repeated a total of 128 times for short version. Long version total: 1 * 2048 = 2048 Dwords. Short version total: 1 * 128 = 128 Dwords. Table 42 – Simultaneous Switching Outputs Pattern (SSOP) Starting with RD+ Transmission Order D31.3(7Fh)+ D31.3(7Fh)- D31.3(7Fh)+ D31.3(7Fh)- + 0101 0011 0010 1011 0011 0101 0011 0010 1011 0011 + 5 3 2 B 3 5 3 2 B 3 Above Dword is repeated a total of 2048 times for long version. Above Dword is repeated a total of 128 times for short version. Long version total: 1 * 2048 = 2048 Dwords. Short version total: 1 * 128 = 128 Dwords. Serial ATA Revision 3.0 Gold Revision page 239 of 663 7.2.4.3.5 Lone-Bit Pattern (LBP) The lone-bit patterns, shown in Table 43 and Table 44, are comprised of the combination of adjacent 10B patterns, resulting in a lone one bit prefixed by a run length of four zeros, and suffixed by a run length of three zeros. It also results in a lone zero bit prefixed by a run length of two ones, one zero, two ones, one zero, four ones, and suffixed by a single one. This is a good test of the receiver jitter tolerance under adverse signaling conditions. The lone bit may be attenuated and narrower than expected. Bit sequences are shown for both cases, where the starting running disparity is negative or positive. Table 43 – Lone-Bit Pattern (LBP) Starting with RD– Transmission Order D12.0(0Ch)- D11.4(8Bh)+ D12.0(0Ch)- D11.3(6Bh)+ - 0011 0110 1111 0100 0010 0011 0110 1111 0100 0011 + 3 6 F 4 2 3 6 F 4 3 D12.0(0Ch)+ D11.4(8Bh)- D12.0(0Ch)+ D11.3(6Bh)- + 0011 0101 0011 0100 1101 0011 0101 0011 0100 1100 - 3 5 3 4 D 3 5 3 4 C Long version total: 1 * 2048 = 2048 Dwords. Short version total: 1 * 128 = 128 Dwords. Table 44 – Lone-Bit Pattern (LBP) Starting with RD+ Transmission Order D12.0(0Ch)+ D11.4(8Bh)- D12.0(0Ch)+ D11.3(6Bh)- + 0011 0101 0011 0100 1101 0011 0101 0011 0100 1100 - 3 5 3 4 D 3 5 3 4 C D12.0(0Ch)- D11.4(8Bh)+ D12.0(0Ch)- D11.3(6Bh)+ - 0011 0110 1111 0100 0010 0011 0110 1111 0100 0011 + 3 6 F 4 2 3 6 F 4 3 Long version total: 1 * 2048 = 2048 Dwords. Short version total: 1 * 128 = 128 Dwords. 7.2.4.3.6 Composite Pattern (COMP) For the measurement of jitter, the composite patterns, as shown in Table 45 and Table 46, should combine low frequency, low transition density, and high transition density patterns. All these combinations, but the low frequency spectral content class may be performed for relatively short test time intervals, for good jitter performance measurements. The lower frequency pattern needs to be tested for longer interval periods to be able to observe the lower frequency jitter effects on the interface. Serial ATA Revision 3.0 Gold Revision page 240 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization The composite pattern (COMP) stresses the interface components within the link with low and high frequency jitter, tests for component, and various amplitude distortions due to marginal receiver input circuitry, or interface components. Note that for the sequence that totals only 128 Dwords, the 128-Dword composite pattern is too short to get a sufficient number of continuous repeats for each pattern type. Table 45 – Composite-Bit Pattern (COMP) Starting with RD– Transmission Order D31.3(7Fh)- D31.3(7Fh)+ D31.3(7Fh)- D31.3(7Fh)+ - 1010 1100 1101 0100 1100 1010 1100 1101 0100 1100 - A C D 4 C A C D 4 C Above Dword is repeated a total of 256 times for long version. Above Dword is repeated a total of 16 times for short version. D21.5(B5h)- D21.5(B5h)- D21.5(B5h)- D21.5(B5h)- - 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 - A A A A A A A A A A Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. D24.3(78h)- D24.3(78h)+ D24.3(78h)- D24.3(78h)+ - - 1100 1100 1100 1100 1100 1100 1100 1100 1100 1100 CCCCCC C C C C Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. D10.2(4Ah)- D10.2(4Ah)- D10.2(4Ah)- D10.2(4Ah)- - - 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 5 5 5 5 5 5 5 5 5 5 Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. D25.6(D9h)- D6.1(26h)+ D25.6(D9h)- D6.1(26h)+ - - 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 9 9 9 9 9 9 9 9 9 9 Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. D17.7(F1h)- D30.7(FEh)+ D7.1(27h)+ D14.7(EEh)+ - - 1000 1101 1110 0001 1110 0001 1110 0101 1100 1000 8 D E 1 E 1 E 5 C 8 D30.7(FEh)- D7.6(C7h)- D30.3(7Eh)- D30.3(7Eh)+ - - 0111 1000 0111 1000 0110 0111 1000 1110 0001 1100 7 8 7 8 6 7 8 E 1 C Serial ATA Revision 3.0 Gold Revision page 241 of 663 Transmission Order D30.3(7Eh)- D30.3(7Eh)+ D30.3(7Eh)- D30.3(7Eh)+ - - 0111 1000 1110 0001 1100 0111 1000 1110 0001 1100 7 8 E 1 C 7 8 E 1 C Above Dword is repeated a total of 509 times for long version. Above Dword is repeated a total of 29 times for short version. D3.7(E3h)- D28.7(FCh)+ D3.7(E3h)- D28.7(FCh)+ - - 1100 0111 1000 1110 0001 1100 0111 1000 1110 0001 C 7 8 E 1 C 7 8 E 1 D12.0(0Ch)- D11.4(8Bh)+ D12.0(0Ch)- D11.3(6Bh)+ + - 0011 0110 1111 0100 0010 0011 0110 1111 0100 0011 3 6 F 4 2 3 6 F 4 3 D12.0(0Ch)+ D11.4(8Bh)- D12.0(0Ch)+ D11.3(6Bh)- - + 0011 0101 0011 0100 1101 0011 0101 0011 0100 1100 3 5 3 4 D 3 5 3 4 C Above 2 Dwords are repeated a total of 128 times for long version. Above 2 Dwords are repeated a total of 8 times for short version. D20.2(54h)- D20.2(54h)- D20.2(54h)- D20.2(54h)- - - 0010 1101 0100 1011 0101 0010 1101 0100 1011 0101 2 D 4 B 5 2 D 4 B 5 Above Dword is repeated a total of 255 times for long version. Above Dword is repeated a total of 15 times for short version. D20.2(54h)- D20.7(F4h)- D11.5(ABh)+ D11.5(ABh)+ + - 0010 1101 0100 1011 0111 1101 0010 1011 0100 1010 2 D 4 B 7 D 2 B 4 A D11.5(ABh)+ D11.5(ABh)+ D11.5(ABh)+ D11.5(ABh)+ + + 1101 0010 1011 0100 1010 1101 0010 1011 0100 1010 D 2 B 4 A D 2 B 4 A Above Dword is repeated a total of 255 times for long version. Above Dword is repeated a total of 15 times for short version. D11.5(ABh)+ D11.7(EBh)+ D20.2.(54h)- D20.2.(54h)- - + 1101 0010 1011 0100 1000 0010 1101 0100 1011 0101 D 2 B 4 8 2 D 4 B 5 - D21.5(B5h)- D21.5(B5h)- D21.5(B5h)- D21.5(B5h)- - Serial ATA Revision 3.0 Gold Revision page 242 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transmission Order 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 A A A A A A A A A A Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. D24.3(78h)- D24.3(78h)- D24.3(78h)- D24.3(78h)- - - 1100 1100 1100 1100 1100 1100 1100 1100 1100 1100 C C C C C CCCC C Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. D10.2(4Ah)- D10.2(4Ah)- D10.2(4Ah)- D10.2(4Ah)- - - 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 5 5 5 5 5 5 5 5 5 5 Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. D25.6(D9h)- D6.1(26h)+ D25.6(D9h)- D6.1(26h)+ - - 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 9 9 9 9 9 9 9 9 9 9 Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. Long version total: 2048 Dwords total 256DW SSOP 256DW HTDP (64DW, 64DW, 64DW, 64DW) 512DW LTDP (1DW, 1DW, 509DW, 1DW) 256DW LBP ((1DW,1DW) x 128) 512DW LFSCP (255DW, 1DW, 255DW, 1DW) 256DW HTDP (64DW, 64DW, 64DW, 64DW) Short version total: 128 Dwords total 16DW SSOP 16DW HTDP (4DW, 4DW, 4DW, 4DW) 32DW LTDP (1DW, 1DW, 29DW, 1DW) 16DW LBP ((1DW,1DW) x 8) 32DW LFSCP (15DW, 1DW, 15DW, 1DW) 16DW HTDP (4DW, 4DW, 4DW, 4DW) Serial ATA Revision 3.0 Gold Revision page 243 of 663 Table 46 – Composite-Bit Pattern (COMP) Starting with RD+ Transmission Order D31.3(7Fh)+ D31.3(7Fh)- D31.3(7Fh)+ D31.3(7Fh)- + 0101 0011 0010 1011 0011 0101 0011 0010 1011 0011 + 5 3 2 B 3 5 3 2 B 3 Above Dword is repeated a total of 256 times for long version. Above Dword is repeated a total of 16 times for short version. D21.5(B5h)+ D21.5(B5h)+ D21.5(B5h)+ D21.5(B5h)+ + 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 + A A A A A A A AAA Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. D24.3(78h)+ D24.3(78h)+ D24.3(78h)+ D24.3(78h)+ + 0011 0011 0011 0011 0011 0011 0011 0011 0011 0011 + 3 3 3 3 3 3 3 3 3 3 Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. D10.2(4Ah)+ D10.2(4Ah)+ D10.2(4Ah)+ D10.2(4Ah)+ + 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 + 5 5 5 5 5 5 5 5 5 5 Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. D25.6(D9h)+ D6.1(26h)+ D25.6(D9h)+ D6.1(26h)+ + 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 + 9 9 9 9 9 9 9 9 9 9 Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. D14.7(EEh)+ D30.7(FEh)- D7.6(C7h)+ D17.7(F1h)- + + 0111 0010 0001 1110 0001 1110 0001 1010 0011 0111 7 2 1 E 1 E 1 A 3 7 D30.7(FEh)+ D7.1(27h)+ D30.3(7Eh)+ D30.3(7Eh)- + + 1000 0111 1000 0111 1001 1000 0111 0001 1110 0011 8 7 8 7 9 8 7 1 E 3 D30.3(7Eh)+ D30.3(7Eh)- D30.3(7Eh)+ D30.3(7Eh)- + + 1000 0111 0001 1110 0011 1000 0111 0001 1110 0011 8 7 1 E 3 8 7 1 E 3 Above Dword is repeated a total of 509 times for long version. Above Dword is repeated a total of 29 times for short version. Serial ATA Revision 3.0 Gold Revision page 244 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transmission Order D28.7(FCh)+ D3.7(E3h)- D28.7(FCh)+ D3.7(E3h)- + + 0011 1000 0111 0001 1110 0011 1000 0111 0001 1110 3 8 7 1 E 3 8 7 1 E D12.0(0Ch)+ D11.4(8Bh)- D12.0(0Ch)+ D11.3(6Bh)- - + 0011 0100 0011 0100 1101 0011 0101 0011 0101 1100 3 5 3 4 D 3 5 3 4 C D12.0(0Ch)+ D11.4(8Bh)- D12.0(0Ch)+ D11.3(6Bh)- + - 0011 0110 1111 0100 0010 0011 0110 1111 0100 0011 3 6 F 4 2 3 6 F 4 3 Above 2 Dwords are repeated a total of 128 times for long version. Above 2 Dwords are repeated a total of 8 times for short version. D11.5(ABh)+ D11.5(ABh)+ D11.5(ABh)+ D11.5(ABh)+ + + 1101 0010 1011 0100 1010 1101 0010 1011 0100 1010 D 2 B 4 A D 2 B 4 A Above Dword is repeated a total of 255 times for long version. Above Dword is repeated a total of 15 times for short version. D11.5(ABh)+ D11.7(EBh)+ D20.2.(54h)- D20.2(54h)- - + 1101 0010 1011 0100 1000 0010 1101 0100 1011 0101 D 2 B 4 8 2 D 4 B 5 D20.2(54h)- D20.2(54h)- D20.2(54h)- D20.2(54h)- - - 0010 1101 0100 1011 0101 0010 1101 0100 1011 0101 2 D 4 B 5 2 D 4 B 5 Above Dword is repeated a total of 255 times for long version. Above Dword is repeated a total of 15 times for short version. D20.2(54h)- D20.7(F4h)- D11.5(ABh)+ D11.5(ABh)+ + - 0010 1101 0100 1011 0111 1101 0010 1011 0100 1010 2 D 4 B 7 D 2 B 4 A Serial ATA Revision 3.0 Gold Revision page 245 of 663 Transmission Order D21.5(B5h)+ D21.5(B5h)+ D21.5(B5h)+ D21.5(B5h)+ + + 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 A A A A A A A AAA Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. D24.3(78h)+ D24.3(78h)+ D24.3(78h)+ D24.3(78h)+ + + 0011 0011 0011 0011 0011 0011 0011 0011 0011 0011 3 3 3 3 3 3 3 3 3 3 Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. D10.2(4Ah)+ D10.2(4Ah)+ D10.2(4Ah)+ D10.2(4Ah)+ + + 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 5 5 5 5 5 5 5 5 5 5 Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. D25.6(D9h)+ D6.1(26h)+ D25.6(D9h)+ D6.1(26h)+ + + 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 9 9 9 9 9 9 9 9 9 9 Above Dword is repeated a total of 64 times for long version. Above Dword is repeated a total of 4 times for short version. Long version total: 2048 Dwords total 256DW SSOP 256DW HTDP (64DW, 64DW, 64DW, 64DW) 512DW LTDP (1DW, 1DW, 509DW, 1DW) 256DW LBP ((1DW,1DW) x 128) 512DW LFSCP (255DW, 1DW, 255DW, 1DW) 256DW HTDP (64DW, 64DW, 64DW, 64DW) Short version total: 128 Dwords total 16DW SSOP 16DW HTDP (4DW, 4DW, 4DW, 4DW) 32DW LTDP (1DW, 1DW, 29DW, 1DW) 16DW LBP ((1DW,1DW) x 8) 32DW LFSCP (15DW, 1DW, 15DW, 1DW) 16DW HTDP (4DW, 4DW, 4DW, 4DW) Note that only 128 Dwords total for the composite pattern is too short to get a sufficient number of continuous repeats for each pattern type. Serial ATA Revision 3.0 Gold Revision page 246 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.5 Hot Plug Considerations 7.2.5.1 Hot Plug Overview The purpose of this section is to provide the minimum set of normative requirements necessary for a Serial ATA Host or Device to be declared as “Hot-Plug Capable”. As there exists various Hot-Plug events, there are relevant electrical and operational limitations for each of those types of events. The events are defined below, and the Hot-Plug Capability is further classified into: a) Surprise Hot-Plug capable b) OS-Aware Hot-Plug capable When a Host or Device is declared Hot-Plug Capable without any qualifier, this shall imply that the SATA interface is Surprise Hot-Plug Capable. For the purposes of this specification, Hot-Plug operations are defined as insertion or removal operations, between SATA hosts and devices, when either side of the interface is powered. Gen1x / Gen 2x / Gen1m and Gen2m interfaces shall meet the requirements to be classified as Hot-Plug Capable. These requirements are not applicable to Gen1i and Gen2i cabled interfaces, however, Gen1i/Gen2i Devices used in Short Backplane applications shall be Hot-Plug Capable. Hot-Plug Capable Hosts/Devices shall not suffer any electrical damage, or permanent electrical degradation, and shall resume compliant Tx/Rx operations after the applicable OOB operations, following the Hot-Plug Events. • Asynchronous Signal Hot Plug / Removal: A signal cable is plugged / unplugged at any time. Power to the Host/Device remains on since it is sourced through an alternate mechanism, which is not associated with the signal cable. This applies to External Single-Lane and Multilane Cabled applications. • Unpowered OS-Aware Hot Plug / Removal: This is defined as the insertion / removal of a Device into / from a backplane connector (combined signal and power) that has power shutdown. Prior to removal, the Host is placed into a quiescent state (not defined here) and power is removed from the backplane connector to the Device. After insertion, the backplane is powered; both the Device and Host initialize and then operate normally. The mechanism for powering the backplane on/off and transitioning the Host into/out of the “quiescent” state is not defined here. During OS-Aware events, the Host is powered. This applies to “Short” and “Long” Backplane applications. • Powered OS-Aware Hot Plug / Removal: This is defined as the removal of a Device into / from a backplane connector (combined signal and power) that has power on. After insertion, both the Device and Host initialize and then operate normally. Prior to insertion or removal, the Host is placed into a quiescent state (not defined here) but the backplane connector to the Device is powered at all times. The mechanism for transitioning the Host into/out of the “quiescent” state is not defined here. During OS-Aware events, the Host is powered. This applies to “Short” and “Long” Backplane applications. • Surprise Hot-Plug / Removal: This is defined as the insertion / removal of a Host or Device into / from a backplane connector (combined signal and power) that has power on. After insertion, both the Device and Host initialize and then operate normally. The powered Host or Device is not in a quiescent state. NOTE: This does not imply transparent resumption of system-level operation since data may be lost, the device may have to be re-discovered and initialized, etc. Regardless of the above definitions, the removal of a device, which is still rotating, is not recommended and should be prevented by the system designer. 7.2.5.2 Electrical Requirements Serial ATA Revision 3.0 Gold Revision page 247 of 663 AC coupling shall be required. Additional hot plug electrical characteristics should include considerations for: common-mode transients, ESD, and drive body discharge. 7.2.5.3 Common-Mode Transients (Informative) It is a requirement that the Hot-Plug Capable SATA component is designed to handle hot-plug events; this informative section highlights the maximum transient events encountered during hotplug operations. An example is presented depicting some of the Hot-Plug relevant specifications of Table 29 (Sequencing Transient Voltage and Common Mode Transient Settle Time), where the impact on hosts/devices is shown. The maximum current induced by a common mode transient is limited by Vcm and the minimum single-ended impedance of 42.5 Ohms. Hence the worst possible surge current would be 2 V / 42.5 Ohms = 47 mA. The duration of this current is limited by the time constant, C * Rtx ~ 0.5 microseconds. This current should be further reduced by supplying common mode termination at the victim end, assuming ESD diodes do not turn on. Vcm Rtx C Rrx Figure 132 – Example Circuit for Common Mode Transients 0 < Vcm < 2 V 21.25 < Rtx < 40 Ohms 21.25 < Rrx < 40 Ohms C < 0.024 uF (Two 0.012 uF capacitors in parallel) The maximum voltage step that may be transmitted to the "victim" end by a transient at the "aggressor" end is the maximum Vcm. This voltage is added to the existing bias voltage at the victim end. Since terminators have no maximum, single-ended limit, this step is not guaranteed to be reduced by any resistive divider. Voltage transients at the "victim" end, however, may be limited by clamping action of ESD diode structures. Serial ATA Revision 3.0 Gold Revision page 248 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.5.4 ESD (Informative) There is no ESD requirement on the SATA connector interface pins. However, it is recommended that the semiconductors used in the Hot Plug Capable Hosts and Devices meet the following ESD specifications. Receiver and Transmitter semiconductor signal pins and power pins should tolerate a minimum of 2000 V using test methods per JEDEC EIA-JESD22-A114-B, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). Receiver and transmitter semiconductor signal pins should tolerate 500 V per JESD22-C101-A, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 7.2.5.5 Drive Body Discharge (Informative) For all Serial ATA backplane systems, the device canister or enclosure should provide sufficient electrical bonding such that electrostatic potential is discharged from the device body ground to the enclosure ground prior to the connector mating. It is strongly advised for all Serial ATA backplane systems, and device canisters for hot-plug capable devices, that the guide-rails are designed to be electrically conductive. The device canister should be designed to have an electrical ground connection to device ground, and the guide-rails within the canister system should be connected to system ground. Serial ATA Revision 3.0 Gold Revision page 249 of 663 7.2.6 Mated Connector Pair Definition The compliance point for receiver and transmitter is at the device/host I/O including the mated connector pair. Figure 133 shows the mated connector pair detail. The compliance point includes the "tails" of the receptacle pins. The physical description of the receptacle pin tails is shown in Figure 134. Serial ATA Mated Connector Pair Device/Host Reference Plane Plug Receptacle Compliance Point Figure 133 – Mated Connector Pair The signal interface to the mated pair connector pin tails should be done with care to minimize parasitic capacitance or inductance. The connector pin, tails are a coplanar waveguide transmission line in a ground, signal, signal, ground (GSSG) configuration. The signal interface to the pin, tails should maintain the GSSG configuration. 2.3 0.8 1.27 Receptacle Figure 134 – Mated Connector Pair, Pin Tail Detail Serial ATA Revision 3.0 Gold Revision page 250 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.2.7 Compliance Interconnect Channels (Gen1x, Gen2x, Gen3i) Compliance Interconnect Channels are defined as a set of calibrated physical test circuits applied to the Transmitter mated connector, intended to be representative of the highest-loss interconnects. The Compliance Interconnect Channel (CIC) is used to verify that the signal electrical characteristics at the Transmitter mated connector are sufficient to ensure compliance to the input electrical specifications for Gen1x, Gen2x and Gen3i receivers as delivered through worst-case media. The magnitude of this worst-case loss as a function of frequency is defined mathematically as a Transmitter Compliance Transfer Function (TCTF). There is a Gen3i TCTF, Gen2x TCTF and a Gen1x TCTF. Any linear, passive, differential two-port (e.g., a SATA cable) with loss greater than the TCTF at all frequencies and which meets the ISI loss constraint (defined below) is defined to be a CIC. (See also section 7.2.7.1.1.) A combination of a zero-length test load (i.e., the Laboratory Load) plus the applicable CIC (Gen1x/Gen2x/Gen3i) is used for the specification of the host-controller or device transmitter characteristics. A Gen1x/Gen2x/Gen3i transmitter signal is specified by: 1. Meeting all parameters in Table 311 for Gen1x, Gen2x or Gen3i when transmitting into a Laboratory Load. 2. Meeting Table 31 input swing (VdiffTX) and jitter (TJ after CIC and DJ after CIC) requirements for Gen1x or Gen2x when transmitting through the appropriate Gen1x or Gen2x CIC into a Laboratory Load while using the same transmitter settings (emphasis, amplitude, etc.) as in the first test.2 (see sections 7.4.5 and 7.4.9) 3. Meeting Table 31 input swing (VdiffTx) and total jitter (TJ after CIC) requirements for Gen3i when transmitting through the appropriate Gen3i CIC into a Laboratory Load while using the same transmitter settings (emphasis, amplitude, etc.) as in the first test. The transmission magnitude response, |S21|, of the Gen3i TCTF satisfies the following two inequalities3: | S21 | ≤ -20 log10 (e) {[3.0 x 10-6 (f 0.5)] + [1.1 x 10-10 (f)] } dB for 50 MHz < f < 9.0 GHz, (f expressed in Hz), | S21 | at 600 MHz - | S21 | at 3000 MHz > 2.7 dB 1 Note that the Transmitter Compliance Specifications are defined and measured into a Laboratory Load. Received signal attenuation or amplification due to actual receiver terminator tolerance as well as additional received signal ISI due to the actual receiver return loss may further degrade the actual receiver’s input signal. Transmitter Compliance Specifications are expected to be only slightly tighter than Receiver Specifications. 2 While not permitted in this specification, this second requirement can be approximated by mathematically processing through a TCTF the signal captured by the HBWS using only the Laboratory Load in the first requirement. 3 Please note that “e” in the first expression is the base of the natural logarithms, approximately 2.71828. Hence, the first factor, 20 log10(e), evaluates to approximately 8.6859. This value is the conversion factor from nepers (defined as the natural logarithm of a power ratio) to decibels. Serial ATA Revision 3.0 Gold Revision page 251 of 663 S 21 0 ISI Loss > 2.7dB -11.1dB 0.6 3.0 Interconnect Sample Compliance 9.0 Frequency (GHz) Figure 135 – Compliance Channel Loss for Gen3i The second constraint, termed ISI loss, may be motivated as follows: |S21| at one tenth the data rate is the attenuation of the fundamental component of a repeating five-ones-five-zeroes pattern, the longest possible run lengths in 8b/10b encoded data. Similarly, |S21| at one half the data rate is the attenuation of the fundamental component of a repeating …010101… pattern, the shortest possible run lengths in 8b/10b encoded data. Hence, for an output waveform of this TCTF, ISI loss approximates the ratio between a) the peak-peak voltage (established by the long run lengths) and b) the inside vertical eye opening (established by the high frequency pattern). Any TCTF with a flatter loss characteristic (i.e., with more broadband attenuation) would generate less inter-symbol interference (ISI) and therefore less output jitter. This constraint prohibits such a TCTF. The transmission magnitude response, |S21|, of the Gen2x TCTF satisfies the following three inequalities4: | S21 | ≤ -20 log10 (e) {[1.7 x 10-5 (f 0.5)] + [1.0 x 10-10 (f)] } dB for 50 MHz < f < 3.0 GHz, (f expressed in Hz), | S21 | ≤ -10.7 dB for 3.0 GHz < f < 5.0 GHz, and | S21 | at 300 MHz - | S21 | at 1500 MHz > 3.9 dB 4 Please note that “e” in the first expression is the base of the natural logarithms, approximately 2.71828. Hence, the first factor, 20 log10(e), evaluates to approximately 8.6859. This value is the conversion factor from nepers (defined as the natural logarithm of a power ratio) to decibels. Serial ATA Revision 3.0 Gold Revision page 252 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization S 21 0 ISI Loss > 3.9dB -10.7dB Sample Compliance Interconnect 0.3 1.5 3.0 Frequency (GHz) Figure 136 – Compliance Channel Loss for Gen2x The third constraint, termed ISI loss, may be motivated as follows: |S21| at one tenth the data rate is the attenuation of the fundamental component of a repeating five-ones-five-zeroes pattern, the longest possible run lengths in 8b/10b encoded data. Similarly, |S21| at one half the data rate is the attenuation of the fundamental component of a repeating …010101… pattern, the shortest possible run lengths in 8b/10b encoded data. Hence, for an output waveform of this TCTF, ISI loss approximates the ratio between a) the peak-peak voltage (established by the long run lengths) and b) the inside vertical eye opening (established by the high frequency pattern). Any TCTF with a flatter loss characteristic (i.e., with more broadband attenuation) would generate less inter-symbol interference (ISI) and therefore less output jitter. This constraint prohibits such a TCTF. The transmission magnitude response, |S21|, of the Gen1x TCTF satisfies the following three inequalities: | S21 | ≤ -20 log10 (e) {[1.7 x 10-5 (f 0.5)] + [1.0 x 10-10 (f)] } dB for 50 MHz < f < 1.5 GHz, (f expressed in Hz), | S21 | ≤ -7.0 dB for 1.5 GHz < f < 5.0 GHz, and | S21 | at 150 MHz - | S21 | at 750 MHz > 2.0 dB Serial ATA Revision 3.0 Gold Revision page 253 of 663 S 21 0 ISI loss > 2.0dB -7.0dB Sample Compliance Interconnect 0.15 0.75 1.5 Frequency (GHz) Figure 137 – Compliance Channel Loss for Gen1x 7.2.7.1.1 Calibration of Compliance Interconnect Channels The TCTF defines the worst-case loss exclusive of the two SATA connectors in the path from transmitter to receiver. However, the loss due to these two connectors shall be included in the transmitter characterization. That is, the transmitter shall be tested with the TCTF-defined loss plus two mated SATA connector pairs. For a CIC implemented with SMA connectors, it is seen in Figure 145 that the addition of a SATA adapter (plug) following the CIC and driving into a Laboratory Load provides the required total loss of TCTF (embodied in the CIC loss) plus the loss of two SATA connectors. 7.2.8 Impedance Calibration (Optional) Hosts and devices may employ on-chip adaptive impedance matching circuits to ensure best possible termination for both its transmitter and receiver. The host, since it is given the first opportunity to calibrate during the power on sequence, cannot assume that the far end of the cable is calibrated yet. For this reason, the host controller should utilize a separate reference to perform calibration. In a desktop system, the cable provides the optimal impedance reference for calibration. Using Time Domain Reflectometry (TDR) techniques, the host may launch a step waveform from its transmitter, so as to get a measure of the impedance of the transmitter, with respect to the cable, and adjust its impedance settings as necessary. In a mobile system environment, where the cable is small or non-existent, the host controller should make use of a separate reference (such as an accurate off-chip resistor) for the calibration phase. The device, on the other hand, may assume that the termination on the far side (host side) of the cable is fully calibrated, and may make use of this as the reference. Using the host termination Serial ATA Revision 3.0 Gold Revision page 254 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization as the calibration reference allows the devices operating in both the desktop and the mobile system environment to use the same hardware. Signals generated for the impedance calibration process shall not duplicate the OOB signals, COMWAKE, COMINIT, or COMRESET. Signals generated for the impedance calibration process shall not exceed the normal operating voltage levels, cited in section 7.2. See the power management section for suggested times to perform calibration during power-on. 7.3 Jitter Jitter is the short-term variations of the zero crossings from ideal positions in time. A "Reference Clock" (defined in section 7.3.2) defines the ideal positions in time. The Reference Clock method provides for the separation of jitter from SSC, tracking SSC and other low frequency modulation but not jitter. There are several types of jitter separated into two classes: deterministic and random. Deterministic jitter is bounded and random jitter is not. The amount of tolerable jitter is limited by the desired bit error rate performance of the channel. Two classes of jitter are used in analysis because they accumulate differently. The Serial ATA data stream employs an embedded clock; no clock signal is separately sent. At the receiver, the Serial ATA data stream is re-clocked to form a parallel digital signal. Adequate timing margin is required for this process to function properly. Jitter analysis is the timing analysis used in systems with an embedded clock. In SATA systems, random jitter is a significant portion of the total jitter causing occasional errors to occur. When a bit error occurs, the error is detected when an entire frame of bits is received. The bit error is corrected by retransmitting the frame. If two bit errors occur within a single frame, the corrective action is the same. The data throughput on the channel is diminished when frames are retransmitted. Frame Error Rate is the channel performance measure. Since a portion of the jitter is random, a measurement of jitter also has a random nature. That is, repeated measurements yield results that are somewhat different. As the sample size of each measurement increases, the spread of the measurement results decreases. A measured value of random jitter is determined to a known confidence level. A frame error rate test is a system performance test done on a combination of SATA compliant components. To achieve a statistically significant estimate of the frame error rate a large sample size is necessary. A frame error rate test on a SATA channel is lengthy requiring about an hour at Gen2 rates. Jitter tests are compliance tests done on an individual SATA component, a device, host, or interconnect to ensure system performance. Compliance tests help to predict the performance of combinations of compliant components. It is often desirable to make jitter measurements in a short period of time rather than hours. Consequently, jitter measurements are done with small sample sizes and the results are extrapolated to predict results with larger sample size. Extrapolation of results from small sample size to large sample size involves assumptions. This specification defines two assumptions as normative. First, the random jitter has a Gaussian distribution. Second, the total jitter is the sum of the deterministic jitter plus 14 times the standard deviation of the random jitter. These allow the separation of deterministic from random jitter, and an estimate of the total jitter for an equivalent BER of 10-12 from a much smaller sample size. Serial ATA Revision 3.0 Gold Revision page 255 of 663 7.3.1 Jitter Definition Jitter is defined as the difference in time between a data transition and the associated Reference Clock event. The jitter at the receiver is the result of the aggregate jitter in the transmission path. First, jitter is generated during clocking of the data in the transmitter. Then, each element in the channel between the transmitter and the receiver influences the jitter. Finally, the receiver shall be able to recover the data despite the jitter, otherwise errors occur. The receiver jitter tolerance shall be greater than the transmitter's generated jitter and the expected jitter accumulation through the channel. Jitter budgets are dependent on the desired bit error rate (BER). SATA assumes a BER target of less than 10-12. Jitter levels are defined as Reference Clock to data. The Reference Clock is extracted from a serial data stream using either a PLL (hardware) or a clock recovery algorithm (software). The Reference Clock to data jitter methodology allows for jitter measurements to be made on a device or host using a Spread Spectrum Clock or a non-spreading clock. 7.3.2 Reference Clock Definition The Reference Clock is defined as that clock recovered from a Serial ATA data stream. The Reference Clock provides the distinction between Spread Spectrum Clocking (SSC) and jitter. The Reference Clock tracks SSC and wander, but not jitter. In addition, it provides a definition for determining the SSC profile. Reference Clock extraction is performed using either hardware or software PLLs Serial ATA Revision 3.0 Gold Revision page 256 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.3.2.1 Gen1i, Gen1m, Gen2i and Gen2m Normative Requirements For Gen1i, Gen1m, Gen2i and Gen2m, the Reference Clock characteristics are controlled by the resulting JTF (Jitter Transfer Function) characteristics obtained by taking the time difference between the Type 2 PLL output (the Reference Clock) and the data stream sourced to the PLL. The PLL CLTF -3 dB corner frequency, and other adjustable CLTF parameters such a peaking, are determined by the value required to meet the requirements of the JTF. (See section 7.4.7 for JTF information) The JTF for Gen1i and Gen1m shall have the following characteristics for an encoded Gen1 D24.3 pattern (1100110011 0011001100). This is the Gen1 MFTP which is a test pattern that has clock-like characteristics and a transition density of 0.5. The JTF for Gen2i and Gen2m shall have the following characteristics for an encoded Gen2 D24.3 pattern (1100110011 0011001100). This is the Gen2 MFTP which is a test pattern that has clock-like characteristics and a transition density of 0.5. 1) 1) The -3 dB corner frequency of the JTF shall be as shown in Table 31 Jitter Transfer Function Bandwidth (D24.3, high pass -3dB). 2) The magnitude peaking of the JTF shall be as shown in Table 31 Jitter Transfer Function Peaking. 3) The attenuation at Jitter Transfer Function Low Frequency Attenuation Measurement Frequency in Table 31 shall be as shown in Table 31 Jitter Transfer Function Low Frequency Attenuation. The JTF -3dB corner frequency and the magnitude peaking requirements shall be measured with sinusoidal PJ applied, with a peak-to-peak amplitude of 0.3 UI +/- 10%. The attenuation at 30 KHz shall be measured with sinusoidal phase (time) modulation applied, with a peak-to-peak amplitude of 20.8 ns +/- 10%. 7.3.2.2 Gen1i, Gen1m, Gen2i, and Gen2m Informative Comments Typically a CLTF -3 dB corner frequency of fBAUD /500 could provide a JTF with characteristics close to the requirements, but due to differences in Type 2 PLL designs, the actual CLTF settings required to meet the required JTF can vary widely. It is desired that the phase response of the JTF of a JMD (Reported Jitter / Applied Jitter) be that of the JTF of the time difference of the output of a Type 2 PLL to the Data stream applied to the PLL. This is the reference design. In the presence of multiple jitter component frequencies, the relative phase at these frequencies determines how they are combined to construct the final reported jitter value. In the case of discrepancies between the reported jitter levels, between JMDs with the same JFT magnitude response, the JMD with the JTF phase characteristics closest to that of the reference design, is to be considered correct. The JTF phase response of a JMD is important, but it is not always possible to determine this without proprietary information concerning the JMD processing methods, and it is not externally observable in some classes of JMDs. The JTF of the time difference of the output of a Type 2 PLL to the Data stream applied to the PLL, or the reference design, is defined with a pattern that has a transition density of 0.5. Since this Type 2 PLL contains a sampled data mode phase detector, with a gain that varies proportionally with transition density, the JTF -3 dB corner frequency will change with the transition density of the applied pattern. For a well designed PLL, with significant phase margin in the open loop response, the JTF -3 dB corner frequency, with shift proportionally with the change of pattern transition density. For example, the 2.1 MHz JTF -3dB corner frequency, set with a pattern with a transition density of 0.5, will shift to 4.2 MHz when a pattern with a transition Serial ATA Revision 3.0 Gold Revision page 257 of 663 density of 1.0, such as the D10.2 pattern, is applied. A proportional decrease of the JTF -3dB corner frequency will also be observed for a decrease in pattern transition density compared to a 0.5 transition density. This is the expected JMD response to changes in pattern transition density as the reference design would exhibit. If a JMD shifts the JTF -3dB corner frequency in a manner that does not match this characteristic, or does not shift at all, measurements of jitter with patterns with transition densities significantly different than 0.5 may lead to discrepancies in reported jitter levels. In the case of reported jitter discrepancies between JMDs, the JMD with the shift of the -3dB corner frequency, closest to the proportional characteristic of the reference design, it to be considered correct. This characteristic may be measured using the conditions defined above for measuring the -3dB corner frequency, using multiple patterns with different transition densities. 7.3.2.3 Gen1x and Gen2x Normative Requirements For Gen1x and Gen2x, the Reference Clock PLL is defined as type 2 PLL with a -3 dB corner frequency fc3dB = fBAUD /1667 given a transition density of 1.0 (corresponding to a 1010101010 clock-like pattern) and damping factor = 0.707 min to 1.00 max. 7.3.2.4 Gen3i Normative Requirements For Gen3i the Reference Clock characteristics are controlled by the resulting JTF (Jitter Transfer Function) characteristics obtained by taking the time difference between the Type 2 PLL output (the Reference Clock) and the data stream sourced to the PLL. The PLL CLTF -3 dB corner frequency, and other adjustable CLTF parameters such a peaking, are determined by the value required to meet the requirements of the JTF. (See section 7.4.8 for JTF information) The JTF for Gen3i shall have the following characteristics for an encoded Gen3 D24.3 pattern (1100110011 0011001100). This is the Gen3 MFTP, which is a test pattern that has clock-like characteristics and a transition density of 0.5. 1) The -3 dB corner frequency of the JTF shall be 4.2 MHz +/- 2 MHz. as shown in Table 31 Jitter Transfer Function Bandwidth (D24.3, high pass -3dB)(Gen3). 2) The magnitude peaking of the JTF shall be 3.5 dB maximum. as showna in Table 31 Jitter Transfer Function Peaking (Gen3). 3) The attenuation at 420 KHz +/- 1% Jitter Transfer Function Low Frequency Attenuation Measurement Frequency (Gen3) in Table 31 shall be 38.2 dB +/- 3 dB. as shown in Table 31 Jitter Transfer Function Low Frequency Attenuation (Gen3). The JTF -3dB corner frequency and the magnitude peaking requirements shall be measured with sinusoidal PJ applied, with peak-to-peak amplitude of 0.3 UI +/- 10%. The attenuation at 420 KHz shall be measured with sinusoidal phase (time) modulation applied, with peak-to-peak amplitude of 1.0 ns +/- 10%. The attenuation is measured on the 40 dB/Dec slope of the JTF at 1/10 the -3 dB corner frequency nominal target value. This is equivalent to 72 dB at 60 KHz for an ideal 40 dB/Dec slope that corresponds to a 2X increase of JTF BW for Gen3i compared to Gen2i. This shift in measurement point allows for improved practical measurements and lower test signal phase modulation level requirements. 7.3.3 Spread Spectrum Clocking Serial ATA allows the use of spread spectrum clocking, or intentional low frequency modulation of the transmitter clock. The purpose of this modulation is to spread the spectral energy to mitigate the unintentional interference to radio services. The modulation frequency of SSC shall be in the range defined for fSSC in Table 29. The modulation frequency deviation shall be in the prescribed range for SSCtol in Table 29. The instantaneous frequency (each period) of the Reference Clock shall fall within the prescribed TUI range. If the rate of change of the instantaneous frequency is excessive jitter is increased. Serial ATA Revision 3.0 Gold Revision page 258 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization The SSC modulation only moves the frequency below the nominal frequency. This technique is often called “down-spreading”. 7.3.3.1 Example SSC Profile (Informative) An example triangular frequency modulation profile is shown in Figure 138. The modulation profile in a modulation period is expressed as: (1 ) f nom + 2 f m f= (1 + ) f nom 2 f m f nom t f nom t when 0 < t < 1 2 fm ; when 1 2 fm 99.99% 99.95% 99.72% 98.97% 97.07% 93.29% 86.99% 77.98% 66.72% 54.21% 41.70% The sample size is taken as ten times the total number of frames transmitted for a given error rate. 1 8.2 ×10 8 ×10 = 1.22×108 Serial ATA Revision 3.0 Gold Revision page 262 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization When a test is conducted where 1.22*108 frames are passed, the maximum number of frame errors to declare a Frame Error Rate of 8.200*10-8 with confidence level of >95% is four. 7.4.1.4 Bit Error Rate Testing (Informative) There are two basic classes of errors that affect the bit-error rate performance: bit-errors, and burst-errors. In order to get a fair assessment of bit-error-rate performance, bit-errors, as well as burst errors, are considered separately. This is because a missing or an extra bit detected by the receiver translates into a series of errors that spans across multiple byte boundaries until re-alignment via an alignment sequence. This series of errors are defined as burst errors. Another type of byte-wise error exists when an entire byte is not received. As viewed by the higher-level protocol it appears as a loss of word synchronization. It causes a burst error whose span may be limited by higher-layer protocol transmission conventions at the next alignment sequence. Any of these errors may result in several related errors occurring closely together which in turn may result in multiple apparent bit-error events. For example, a character might have a single bit error in it that causes a code-violation error. A disparity error might occur on a following character, caused by the same single error. All of these events eventually are recognized during the decoding process and result in a frame error. NOTE: Burst Error Rate measurements shall not be used for Compliance testing. 7.4.1.4.1 Bit Error Rate Measurements The Bit Error Rate, if measured and computed, byte-wise, should be no greater than 10-12 biterrors when tested with the reference test patterns, cited in section 7.4.1.1. Frame Error Rate measurements constitute the basis for the applicable test requirements for this specification. See 7.4.1 for an explanation of the relationship between FER and BER. Serial ATA Revision 3.0 Gold Revision page 263 of 663 7.4.1.4.2 Amount of Data to Transfer to Achieve Target Error Rate As this is a statistical process, there are confidence levels associated to each sample size. For example, one should only declare that the interface Bit Error Rate performance has been achieved with a confidence level of 95% for that given sample size, and error thresholds as shown in Table 48. Table 48 – Bit Error Rate Confidence Levels Versus Sample Size Sample Size (Bits) Number of Bit-Error Events - Threshold 0 1 2 3 4 5 6 7 8 9 10 1.00*1012 63.21% 26.42% 8.03% 1.90% 0.37% 0.06% 0.01% <0.01% <0.01% <0.01% <0.01% 1.00*1013 >99.99% 99.95% 99.72% 98.97% 97.07% 93.29% 86.99% 77.98% 66.72% 54.21% 41.70% When a test is conducted where 1013 bits are passed, the maximum number of error events to declare a Bit Error Rate of 10-12 with confidence level of >95% is four. 7.4.2 Measurement of Differential Voltage Amplitudes (Gen1, Gen2) The differential voltage amplitude, VdiffTX, shall be measured for bits in representative data patterns. It is necessary to use patterns that are DC balanced for this testing (otherwise, an offset is introduced that shifts the measured mean values). The test setup shown in Figure 140 below shows the connections: TX Signals from UUT Host / Device Compliance Point SATA Adapter (Receptacle) Transmitter Under Test SATA Mated Connector Pair DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms 50 Ohms HBWS Laboratory Load (LL) Figure 140 – Differential Voltage Amplitude Measurement The transmitter under test sends the test pattern to a HBWS. The differential voltage waveform corresponding to one complete cycle of the N bit pattern has some unit intervals corresponding to zero bits and some unit intervals corresponding to ones bits. Figure 141 illustrates an example of a display on an equivalent time scope: Serial ATA Revision 3.0 Gold Revision page 264 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Bit 1 Bit 1 Bit 0 Bit 0 Unit Interval Boundaries Figure 141 – Differential Voltage Amplitude Measurement Pattern Example 7.4.2.1 Testing for Minimum Differential Voltage Amplitude There are two separate procedures for this testing. However, each of the two procedures requires a common set of steps to be performed. These are labeled below as “Common Steps”. Following these steps are those that describe the rest of the procedure for one of two options (labeled as “Option 1 or Option 2 Steps”). 7.4.2.1.1 Common Steps Common Step 1: Transmitting a HFTP pattern, for a unit interval (UI) corresponding to a 1 bit, construct a histogram based on n samples collected in the waveform epoch [0.45 UI, 0.55 UI] for the UI. The number of samples in a histogram (n) for the UI shall be greater than or equal to 100 and shall meet the requirement that: _ 1537(s / x)2 n where: x = the mean of the voltage samples in the histogram that may be read from the HBWS in histogram measurement mode s = the standard deviation of the voltage samples in the histogram which may also be read from the HBWS n = the number of samples that contribute to the histogram – this may also be read from the HBWS The inequality above is based on a requirement that enough samples are collected to define a confidence interval with at least 95% probability and with a width no greater than 10% of the sample mean. Serial ATA Revision 3.0 Gold Revision page 265 of 663 Compute the following value: UH = [x 1.96s ] n Common Step 2: Transmitting a HFTP pattern, for a unit interval (UI) corresponding to a 0 bit, construct a histogram based on n samples collected in the waveform epoch [0.45 UI, 0.55 UI] for the UI. The number of samples in a histogram (n) for the UI shall be greater than or equal to 100 and shall meet the requirement that: _ 1537(s / x)2 n where: x = the mean of the voltage samples in the histogram that may be read from the HBWS in histogram measurement mode s = the standard deviation of the voltage samples in the histogram which may also be read from the HBWS n = the number of samples that contribute to the histogram – this may also be read from the HBWS Compute the following value: LH = [x + 1.96s ] n Common Step 3: Transmitting a MFTP pattern, for a unit interval (UI) corresponding to the second 1 bit of a string of two consecutive 1 bits, construct a histogram based on n samples collected in the waveform epoch [0.45 UI, 0.55 UI] for the UI. The number of samples in a histogram (n) for the UI shall be greater than or equal to 100 and shall meet the requirement that: _ 1537(s / x)2 n where: x = the mean of the voltage samples in the histogram that may be read from the HBWS in histogram measurement mode s = the standard deviation of the voltage samples in the histogram which may also be read from the HBWS n = the number of samples that contribute to the histogram – this may also be read from the HBWS Serial ATA Revision 3.0 Gold Revision page 266 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Compute the following value: UM = [x 1.96s ] n Common Step 4: Transmitting a MFTP pattern, for a unit interval (UI) corresponding to the second 0 bit of a string of two consecutive 0 bits, construct a histogram based on n samples collected in the waveform epoch [0.45 UI, 0.55 UI] for the UI. The number of samples in a histogram (n) for the UI shall be greater than or equal to 100 and shall meet the requirement that: _ 1537(s / x)2 n where: x = the mean of the voltage samples in the histogram that may be read from the HBWS in histogram measurement mode s = the standard deviation of the voltage samples in the histogram which may also be read from the HBWS n = the number of samples that contribute to the histogram – this may also be read from the HBWS Compute the following value: LM = [x + 1.96s ] n Common Step 5: Compute the minimum of the following two differences: DH = UH – LH DM = UM – LM That is, compute DHM = min (DH, DM). This value is used in the final step of each of the following two options. 7.4.2.1.2 Lone Bit Pattern Measurements, Option 1 If the test environment allows for the creation of a pattern trigger, the LBP pattern is used to make the following measurements. Continue the procedure from Common Step 5 above with the following steps for Option 1. If the test environment does not allow for the creation of a pattern trigger, then continue the procedure from Common Step 5 above with the steps beginning with Option 2 Step 6 below. Option 1 Step 6: Transmitting a LBP pattern, for a unit interval (UI) corresponding to a lone 1 bit, construct a histogram based on n samples collected in the waveform epoch [0.45 UI, 0.55 UI] for Serial ATA Revision 3.0 Gold Revision page 267 of 663 the UI. The number of samples in a histogram (n) for the UI shall be greater than or equal to 100 and shall meet the requirement that: _ 1537(s / x)2 n where: x = the mean of the voltage samples in the histogram that may be read from the HBWS in histogram measurement mode s = the standard deviation of the voltage samples in the histogram which may also be read from the HBWS n = the number of samples that contribute to the histogram – this may also be read from the HBWS Compute the following value: A = [x 1.96s ] n Option 1 Step 7: Transmitting a LBP pattern, for a unit interval (UI) corresponding to a lone 0 bit, construct a histogram based on n samples collected in the waveform epoch [0.45 UI, 0.55 UI] for the UI. The number of samples in a histogram (n) for the UI shall be greater than or equal to 100 and shall meet the requirement that: _ 1537(s / x)2 n where: x = the mean of the voltage samples in the histogram that may be read from the HBWS in histogram measurement mode s = the standard deviation of the voltage samples in the histogram which may also be read from the HBWS n = the number of samples that contribute to the histogram – this may also be read from the HBWS Compute the following value: B = [x + 1.96s ] n Option 1 Step 8: From A and B obtained in steps 1 and 2, compute: VTestLBP = A – B Serial ATA Revision 3.0 Gold Revision page 268 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Then take the minimum of VTestLBP and the previously computed DHM (from Common Step 5), that is, VTest = min (VTestLBP, DHM) The test for minimum amplitude is passed if: VTest > VdiffTX(Min) See Table 31 section 1.1.1 for VdiffTX(Min). Otherwise, the test for minimum differential voltage amplitude has not been passed. If the test for minimum voltage amplitude is failed, the number of samples, n, is to be increased and the test shall be executed again for this larger number of samples. Failure to arrive at a value n, for which the test passes, means that the requirement of the specification, for minimum differential voltage amplitude, has not been met. 7.4.2.1.3 Approximation to Lone Bit Pattern Measurements, Option 2 To test for minimum differential voltage amplitude without the ability to create a pattern trigger, continue the procedure from Common Step 5 above with the following steps for option 2: Option 2 Step 6: Transmitting a LFTP pattern, construct a histogram based on n samples collected in the waveform epoch [0.45 UI, 0.55 UI] for the UI of the first 1 bit that follows either a string of three preceding 0 bits or a string of four preceding 0 bits. It is required that the histogram samples be the union of the samples collected for both cases. The number of samples in a histogram (n) for the UI shall be greater than or equal to 100 and shall meet the requirement that: _ 1537(s / x)2 n where: x = the mean of the voltage samples in the histogram that may be read from the HBWS in histogram measurement mode s = the standard deviation of the voltage samples in the histogram which may also be read from the HBWS n = the number of samples that contribute to the histogram – this may also be read from the HBWS Compute the following value: A = [x 1.96s ] n Option 2 Step 7: Transmitting a LFTP pattern, construct a histogram based on n samples collected in the waveform epoch [0.45 UI, 0.55 UI] for the UI of the first 0 bit that follows either a string of three preceding 1 bits or a string of four preceding 1 bits. It is required that the histogram samples be the union of the samples collected for both cases. The number of samples in a histogram (n) for the UI shall be greater than or equal to 100 and shall meet the requirement that: Serial ATA Revision 3.0 Gold Revision page 269 of 663 _ 1537(s / x)2 n where: x = the mean of the voltage samples in the histogram that may be read from the HBWS in histogram measurement mode s = the standard deviation of the voltage samples in the histogram which may also be read from the HBWS n = the number of samples that contribute to the histogram – this may also be read from the HBWS Compute the following value: B = [x + 1.96s ] n Option 2 Step 8: Transmitting a LFTP pattern, construct a histogram based on n samples collected in the waveform epoch [0.45 UI, 0.55 UI] for the UI of the last ‘1’ bit in a string of three or four ‘1’ bits. It is required that the histogram samples be the union of the samples collected for both cases. The number of samples in a histogram (n) for the UI shall be greater than or equal to 100 and shall meet the requirement that: _ 1537(s / x)2 n where: x = the mean of the voltage samples in the histogram that may be read from the HBWS in histogram measurement mode s = the standard deviation of the voltage samples in the histogram which may also be read from the HBWS n = the number of samples that contribute to the histogram – this may also be read from the HBWS Call the mean, x = C Option 2 Step 9: Transmitting a LFTP pattern, construct a histogram based on n samples collected in the waveform epoch [0.45 UI, 0.55 UI] for the UI of the last ‘0’ bit in a string of three or four ‘0’ bits. It is required that the histogram samples be the union of the samples collected for both cases. The number of samples in a histogram (n) for the UI shall be greater than or equal to 100 and shall meet the requirement that: _ 1537(s / x)2 n Serial ATA Revision 3.0 Gold Revision page 270 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization where: x = the mean of the voltage samples in the histogram that may be read from the HBWS in histogram measurement mode s = the standard deviation of the voltage samples in the histogram which may also be read from the HBWS n = the number of samples that contribute to the histogram – this may also be read from the HBWS Call the mean, x = D Option 2 Step 10: Transmitting a LFTP pattern, construct a histogram based on n samples collected in the waveform epoch [0.45 UI, 0.55 UI] for the UI of the last ‘1’ bit in a string of four ‘1’ bits. The number of samples in a histogram (n) for the UI shall be greater than or equal to 100 and shall meet the requirement that: _ 1537(s / x)2 n where: x = the mean of the voltage samples in the histogram that may be read from the HBWS in histogram measurement mode s = the standard deviation of the voltage samples in the histogram which may also be read from the HBWS n = the number of samples that contribute to the histogram – this may also be read from the HBWS Call the mean, x = E Option 2 Step 11: Transmitting a LFTP pattern, construct a histogram based on n samples collected in the waveform epoch [0.45 UI, 0.55 UI] for the UI of the last ‘0’ bit in a string of four ‘0’ bits. The number of samples in a histogram (n) for the UI shall be greater than or equal to 100 and shall meet the requirement that: _ 1537(s / x)2 n where: x = the mean of the voltage samples in the histogram that may be read from the HBWS in histogram measurement mode s = the standard deviation of the voltage samples in the histogram which may also be read from the HBWS Serial ATA Revision 3.0 Gold Revision page 271 of 663 n = the number of samples that contribute to the histogram – this may also be read from the HBWS Call the mean, x = F Option 2 Step 12: From A and B obtained in steps 1 and 2, compute: VTestAPP = (A + C + F) – (B + D + E) Then take the minimum of VTestAPP and the previously computed DHM, that is, VTest = min (VTestAPP, DHM) The test for minimum amplitude is passed if: VTest > VdiffTX(Min) See Table 31, section 1.1.1 for VdiffTX(Min). Otherwise, the test for minimum differential voltage amplitude has not been passed. If the test for minimum voltage amplitude is failed, the number of samples, n, is to be increased and the test shall be executed again for this larger number of samples. Failure to arrive at a value n, for which the test passes, means that the requirement of the specification for minimum differential voltage amplitude has not been met. Figure 142 illustrates the locations of the sections of the LFTP as displayed on a scope from which the measurements of the values for A, B, C, D, E, and F (see steps 1 through 6 above) are to be made. Serial ATA Revision 3.0 Gold Revision page 272 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization E C A B D F Figure 142 – LFTP Pattern on High BW Scope (HBWS) 7.4.2.2 Test for Maximum Differential Voltage Amplitudes To test for maximum differential voltage amplitude for a given data pattern, perform the following steps using the LFTP and the MFTP as the data patterns. The waveform sections to be examined are defined as: High Test UI: For the LFTP, use the fourth ‘1’ bit in a string of four ‘1’ bits. For the MFTP, use the first ‘1’ bit in a string of two ‘1’ bits. Low Test UI: For the LFTP, use the fourth ‘0’ bit in a string of four ‘0’ bits. For the MFTP, use the first ‘0’ bit in a string of two ‘0’ bits. Step 1: For the High Test UI, construct a histogram in the waveform epoch [0.0 UI, 1.0 UI] for the UI. Position the upper edge of the histogram window at VU mV where: VU = 1 2 VDIFFTX (max) Serial ATA Revision 3.0 Gold Revision page 273 of 663 See Table 31, Section 1.1.1 for VdiffTX(Max). Position the lower edge of the histogram window at 0mV. Let the histogram acquire hits for a fixed time duration, T, such that the number of hits acquired is at least 10000. Note the number of histogram hits as NU. This histogram may be based on data stored in the waveform database. For the same High Test UI, construct a histogram in the waveform epoch [0.0 UI, 1.0 UI]. Position the upper edge of the histogram window at VU + 300 mV. Position the lower edge of the histogram window at VU mV. Note the number of histogram hits as nu. Step 2: For the Low Test UI, construct a histogram in the waveform epoch [0.0 UI, 1.0 UI]. Position the upper edge of the histogram window at 0 mV. Position the lower edge of the histogram window at VL mV where: VL = 1 2 VDIFFTX (max) Let the histogram acquire hits for the same fixed time duration, T, as used in step 1. (In practice, using the same waveform database as that collected in Step 1 insures that the same time duration is examined.) Note the number of histogram hits as NL. For the same Low Test UI, construct a histogram in the waveform epoch [0.0 UI, 1.0 UI]. Position the lower edge of the histogram window at VL – 300 mV. Position the upper edge of the histogram window at VL mV. Note the number of histogram hits as nl. Step 3: Compute the values: pu = nu nu +NU pl = nl nl +NL (Note: There are two values of pu and pl computed; one for the use of the LFTP and one for the use of the MFTP). Step 4: The test for maximum amplitude is passed if: pu < 0.05 and pl < 0.05 (Note: Since there are two values of pl and pu, the test needs to be applied to each pair.) Otherwise, the test for maximum differential voltage amplitude has not been passed. Serial ATA Revision 3.0 Gold Revision page 274 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.4.3 Measurement of Differential Voltage Amplitudes (Gen3i) The amplitude measurement of differential signals for Gen3i uses different methods for the maximum amplitude and the minimum amplitude compliance tests. The maximum amplitude is a peak-to-peak value measured at the TX compliance point into a Lab Load. This limits the magnitude of signals present in the interface. The minimum amplitude is a measurement of the minimum eye opening, using the specified method, after the Gen3i CIC, into a Lab Load. This provides a minimum signal level for the receiver, measured in a manner that is representative of how a typical receiver would process the signal. Achieving both the maximum and minimum differential amplitude compliance limits as listed in Table 31 shall be required, using the same transmitter settings for both tests. The same methods and patterns are used for setting up the Lab-Sourced Signal for Receiver Tolerance Testing, with the compliance limits specified in Table 33. 7.4.3.1 Maximum Differential Voltage Amplitude (Gen3i) The maximum differential amplitude shall be measured at the TX Compliance point into a Lab Load. Figure 156 shows a drawing of this test connection. A Gen3 MFTP shall be used for this compliance measurement, although it is possible that with other patterns and signal path characteristics, additional peak-to-peak maximum amplitude values maybe present in the actual system. The MFTP will contain emphasis due to its run length, if the transmitter supports this signal conditioning, and allows for simple edge triggering for the signal capture. The maximum amplitude is defined as the peak to peak value of the average of 500 waveforms measured over a time span of 4 Gen3 UI, using the HBWS. 7.4.3.2 Minimum Differential Voltage Amplitude (Gen3i) The minimum TX differential amplitude shall be measured through the Gen3i CIC as specified in section 7.2.7 terminated into the Lab Load. Figure 157 shows a drawing of this test connection. A Gen3 LBP shall be used for this compliance measurement, although it is possible that with other patterns and signal path characteristics, lower amplitudes may be present in the actual system. The minimum amplitude is defined as the vertical eye opening of the 1E-12 BER contour at the 50% point of the UI, when the data is captured using the Gen3i Reference Clock JTF defined in section 7.3.2. The test equipment or JMDs typically used for this measurement include a BERT or a HBWS with appropriate hardware and software to measure or extrapolate a Vertical Bathtub Curve, Eye BER Contour plot, or statistical Eye Opening characteristics. Since some JMDs extrapolate the Eye Opening at the BER target from a smaller population size capture, that measurement is an approximation of the actual Eye Opening. If there are discrepancies between test equipment in the reported Eye Opening at the target BER, the value obtained from a full population vertical BERT scan shall be the standard for this measurement. This is analogous to the horizontal full population BERT scan as being the standard for TJ when measuring jitter. All test equipment requires a minimum signal amplitude to be able to measure the 1E-12 BER contour or equivalent data. This level varies with instrumentation type, hardware and software. This minimum required instrumentation amplitude introduces errors in the reported minimum amplitude measurement value. This error results in the minimum amplitude reported by the test equipment to be smaller than the actual signal minimum amplitude. This instrumentation error shall be corrected for, to determine the actual minimum amplitude value using recommended methods provided by the test equipment manufacturer. If no such recommended correction Serial ATA Revision 3.0 Gold Revision page 275 of 663 procedure is available for one piece of test equipment, alternate test equipment could be selected. An approximate correction method could be used in the case of unsupported test equipment. The amplitude of a low noise Lab Source Gen3 MFTP test pattern with the fastest allowed Gen3i rise and fall times is reduced in several steps using passive calibrated attenuators. If the reported amplitude is plotted on the y-axis and the ideal amplitude calculated using the calibrated attenuators and source is plotted on the x-axis, the y-axis intercept represents the theoretical reported amplitude for a zero amplitude input. A linear curve fit to the measured data can extrapolate the measured data to the y-axis intercept. (a negative value) The absolute value of this y-axis intercept is then added as a positive number to the instrument reported minimum Eye Opening values to correct for this error term. Since this is a statistical measurement and the test equipment may contain significant random amplitude variations. This correction method can be in error since it does not convolve the random amplitude variation sources, but it reduces the error magnitude below an uncorrected measurement. This may result in a possible over correction of the instrumentation error term. 7.4.4 Rise and Fall Times The rise and fall times of the waveform under test are defined over a 20%-80% output level change from the High and Low reference levels. High Reference level of the waveform under test is the “mode” of the top portion while the Low Reference level is the “mode” of the bottom portion. Mode is measured using Statistical Methods of the desired waveform and is the most common value of the probability density function. The minimum time span of the analysis zone for measuring the mode amplitude shall be 8 UI. Therefore, Rise Time = X2 - X1; where X2 is the mean horizontal time value corresponding to 80% of the distance between the Low and High value and X1 is the mean horizontal time value position corresponding to 20% of the distance between the Low and High value. And Fall Time = X1 - X2; where X1 is the mean horizontal time value corresponding to 20% of the distance between the Low and High value and X2 is the mean horizontal time value position corresponding to 80% of the distance between the Low and High value. Serial ATA Revision 3.0 Gold Revision page 276 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization TX(+) SINGLE-ENDED DATA LINES TX(-) 80% 20% Trise TX(+) SINGLE-ENDED DATA LINES TX(-) 80% 20% Tfall Figure 143 – Single Ended Rise and Fall Time Rise and Fall values are measured using the LFTP Pattern previously defined, for all Gen1 and Gen2 Electrical Specifications. The average rise time of all rising edges and the separate average fall time of all falling edges within the 8 UI analysis zone shall both meet the required rise and fall time compliance limits. For Gen3i, the Rise and Fall time values, between 20% and 80%, are measured using only the Gen3 LFTP. This minimizes errors in determining the 0% and 100% reference levels using the Mode Amplitude measurement method. The analysis zone of the measurement shall be made over a minimum time length of 8 UI. This is a Lab Load measurement. The Rise and Fall time compliance limits, for the differential TX test pattern are listed in Table 31. The average Rise time of all rising edges and the separate average Fall time of all falling edges within the analysis zone shall meet the Rise and Fall time compliance limits respectively. The Rise and Fall time compliance limits for the differential Data Signal Source (see Figure 162), for Receiver Tolerance testing, are also set with this method and pattern. The compliance limits for the Lab-Sourced Signal are listed in Table 33. The rise and fall times for transmitter differential buffer lines are measured with the load fixture shown in Figure 144. The rise and fall times shall be measured with an HBWS. Serial ATA Revision 3.0 Gold Revision page 277 of 663 7.4.5 Transmitter Amplitude The transmitter amplitude values specified in Table 31 refer to the output signal from the unit under test (UUT) at the mated connector into a Laboratory Load (LL) (for Gen1i, Gen2i, Gen1m, Gen2m, Gen1x, Gen2x, and Gen3i), or from the unit under test through a Compliance Interconnect Channel (CIC) into a Laboratory Load (for Gen1x, Gen2x, and Gen3i only). The signals are not specified when attached to a system cable or backplane. 7.4.5.1 Transmitter Amplitude (Gen1 and Gen2) Transmitter minimum amplitude is measured with each of three waveforms: HFTP, MFTP, and the Lone Bit Pattern (LBP). Amplitude specifications shall be met according to the measurement method outlined in section 7.4.2 The minimum amplitude value is measured during the TX minimum voltage measurement interval defined in Table 31. The Reference Clock (defined in section 7.3.2) defines the ideal (zero jitter) zero crossing times. The maximum amplitude is measured according to the measurement method outlined in section 7.4.2.2 using waveforms LFTP and MFTP. The transmit DC offset voltage (for Gen1i only) should be measured with the setup in Figure 144. The HBWS is measuring a DC voltage and the DC blocks shall not be present. Figure 144 and Figure 145 show test setups for measuring transmitter amplitude. The HBWS is the standard for measuring amplitude. The losses in the test connections may be significant so it is prudent to minimize and estimate these. Several methods may be used to estimate the cabling losses. The first is to use two cables of different lengths and compare the losses of each. The second is to rely on published data for the cables. The third is to obtain a separate means for measuring the cable loss such as characterization with a network analyzer or power meter. TX Signals from UUT Host / Device Transmitter Under Test Compliance Point SATA Adapter (Receptacle) SATA Mated Connector Pair DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms 50 Ohms HBWS Laboratory Load (LL) Figure 144 – Transmit Amplitude Test with Laboratory Load Serial ATA Revision 3.0 Gold Revision page 278 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization TX Signals from UUT SATA Adapter (Receptacle) SMA Connectors Compliance SATA Adapter Point (Plug) DC Block (As required) Host / Device Transmitter Under Test SATA Mated Connector Pair Compliance Interconnect Channel (With losses greater than TCTF and SATA Mated Connector Pair SATA Adapter (Receptacle) meeting ISI loss limit and SMA connectors.) Laboratory Load (LL) HBWS / JMD Figure 145 – Transmit Amplitude Test with Compliance Interconnect Channel This specification describes transmitter levels in terms of voltage when driving a test load of 100 Ohms differential (the Laboratory Load, LL) and 50 Ohms single ended to ground. To relate the specified maximum levels to the maximum values seen in a system requires a calculation. An example of this calculation is in section 7.4.6. 7.4.5.2 Transmitter Amplitude (Gen3i) Transmitter minimum amplitude is measured with the Lone Bit Pattern (LBP). Amplitude specifications shall be met according to the measurement method outlined in section 7.4.3. The minimum amplitude value is measured during the TX minimum voltage measurement interval defined in Table 31. The Reference Clock (defined in section 7.3.2) defines the ideal (zero jitter) zero crossing times. The maximum amplitude is measured according to the measurement method outlined in section 7.4.3 using the MFTP waveform. Figure 156 and Figure 157 show test setups for measuring transmitter amplitude. See section 7.4.5.1 for suggestions on compensating for losses in the test connections. 7.4.6 Receive Amplitude This section describes setting the receive amplitude, a test condition common to many tests. The proper operation of the receiver is its ability to receive a signal. An example of this testing is described in section 7.4.11. The values as specified in Table 33 refer to the input signal from any signal source as measured at the device under test using a Laboratory Load. Serial ATA Revision 3.0 Gold Revision page 279 of 663 50 Ohms 50 Ohms HBWS Compliance Point DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms 50 Ohms Data Signal Source Figure 146 – Receiver Amplitude Test--Setting Levels TX Signals from UUT Host / Device Receiver Under Test Compliance Point SATA Adapter (Receptacle) SATA Mated Connector Pair DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms 50 Ohms Data Signal Source Lab Sourced Signal Figure 147 – Receiver Amplitude Test Figure 146 shows an example to account for loss in the cabling and error in the signal source for receiver level testing. The loss in the SATA adapter is not accounted for here, but may be separately measured. The HBWS is used as the standard for amplitude when setting the levels for testing receivers. Equivalent methods to account for loss in the cabling are acceptable. This specification describes receiver levels in terms of voltage driven from a differential source of 100 Ohms impedance. A calculation is required to relate the specified maximum receiver level to the maximum receiver level in a system. The maximum receiver level is set at a HBWS by driving with a signal source impedance of 100 Ohms. With the signal generator level set, it is then applied to the receiver under test. The voltage actually seen at the receiver inputs depends on the input impedance of the receiver. The maximum voltage at the receiver occurs when the receiver input impedance is at its maximum value. Serial ATA Revision 3.0 Gold Revision page 280 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Rs Vsrc Vamp RL Figure 148 - Voltage at Receiver Input VAMP = VSRC 1+ RS RL VA = 1+ RS RLL 1+ RS RL The values of the receiver and transmitter resistor termination are set by the return loss specification at low frequency. Return loss is given by the following equation: RL = 20 log " "$ Z Z + Z0 Z0 ! # #% And solving this for the resistance, the real part of the impedance gives two solutions R = Z0 1 10 10 RL 20 RL 20 + 1 = (100) 1 10 10 1820 1820 +1 = 77.64 R = Z0 10 1 RL 20 +1 10 RL 20 = (100) 10 1 1820 +1 10 1820 = 128.8 R = Z0 1 10 10 RL 20 RL 20 +1 = (100) 1 10 10 1420 14 20 +1 = 66.73 R = Z0 10 1 RL 20 +1 10 RL 20 = (100) 10 1 14 20 +1 10 1420 = 149.9 The highest amplitude that may be seen at the receiver occurs when the receiver input resistance is highest. Serial ATA Revision 3.0 Gold Revision page 281 of 663 VAMP = 0.7 1 + 100 100 1 + 100 128.8 = 0.7881 The lowest amplitude at the receiver occurs when the receiver input resistance is lowest. VAMP = 0.4 1 + 100 100 1 + 100 77.64 = 0.3497 Serial ATA Revision 3.0 Gold Revision page 282 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.4.7 Long Term Frequency Accuracy There are several considerations for choosing instruments to measure long-term frequency accuracy. The long-term frequency accuracy of the instrument time base needs to be significantly better than the 350 ppm limit in this specification; many oscilloscopes do not have this frequency accuracy. A method to measure the long-term frequency accuracy is to use a frequency counter. The test setup shown in Figure 149 below shows the connections. The transmitter under test sends a HFTP (D10.2) signal to the frequency counter. The signal shall not have SSC modulation. The frequency counter should have a gating period set long enough to reduce the effects of noise; this may be done by setting the counter resolution to 10 Hz or better (350 ppm at 1.5 GHz is 525 kHz). The counter reads the long-term frequency of the transmitter; the accuracy is a percentage. When SSC is present, long term frequency accuracy specification is not applicable, instead the SSC profile is measured (see section 7.4.11) There are other instruments that contain a frequency counter with an accuracy significantly better than 350 ppm. For example some BERT equipment has a frequency counter on the clock input. TX Signals from UUT Host / Device Transmitter Under Test Compliance Point SATA Adapter (Receptacle) SATA Mated Connector Pair LL Laboratory Load DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms 50 Ohms Frequency Counter Figure 149 – TX Long Term Frequency Measurement Serial ATA Revision 3.0 Gold Revision page 283 of 663 7.4.8 Jitter Measurements Jitter is the difference in time between a data transition and the associated Reference Clock event, taken as the ideal point for a transition. The causes of jitter are categorized into random sources (RJ) and deterministic sources (DJ). Although the total jitter (TJ) is the convolution of the probability density functions for all the independent jitter sources, this specification defines the random jitter as Gaussian and the total jitter as the deterministic jitter plus 14 times the random jitter. The TJ specifications of Table 31 and Table 33 were chosen at a targeted BER of 10-12. The BERT scan method described in section 7.4.8.1 is the only method that measures the actual TJ and is used as the reference for all TJ estimation methods. The method for estimating TJ is unique to each measurement instrument. Serial Data Recovered Data Recovered Clock Clock Recovery Circuit Receiver Clock Recovery Circuitry Has Low-Pass Function HL Magnitude (dB) Frequency (f) Figure 150- Receiver Model for Jitter The jitter measurement methodology is defined as a clock to data jitter measurement. Figure 150 shows a block diagram of a deserializer input. The serial data is split into two paths. One path feeds clock recovery circuitry, which becomes the reference signal used to latch the data bits of the serial data stream. This clock recovery circuitry has a low pass transfer function HL. This low pass function is the CLTF of the PLL or clock recovery circuit. The jitter seen by the receiver is the time difference of the recovered clock edge to the data edge position. This time difference function is shown in Figure 151. The resulting jitter seen by the receiver has a high pass function HH shown in Figure 152. This high pass function is the JTF (Jitter Transfer Function) of the system. This defines the measurement function required by all jitter measurement methodologies. The required characteristics for the JTF (Gen1i, Gen1m, Gen2i, Gen2m) and the CLTF corner frequency fc (Gen1x, Gen2x) are provided in section 7.3.2. In the case of a JMD, the JTF may be simply viewed as the ratio of the reported jitter to the applied jitter, for a sinusoidal PJ input. Both the CLTF and the JTF are uniquely defined by the open loop transfer function G(s). Defining a CLTF does not uniquely define the G(s) and subsequently the JTF due to the level of cancellation of G(s) in the numerator and denominator of the CLTF especially when G(s) is much greater than 1, which is necessary for jitter tracking by the clock recovery circuit. This is the rationale for Gen1i, Gen1m, Gen2i and Gen2m directly specifying the JTF rather than the CLTF Serial ATA Revision 3.0 Gold Revision page 284 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization of the clock recovery circuit. When the JTF of a JMD meets the requirements specified, the JMD reported jitter levels will closer represent the jitter applied to the receiver in this reference design. + Clock Recovery Circuit - Time Difference Jitter Seen by the Receiver Figure 151 – Jitter at Receiver HL or CLTF from Clock Recovery Function 0 -3 HH = 1 - HL or JTF from Difference Function Magnitude (dB) JTF fC CLTF fC Frequency (f) Figure 152 – Jitter at Receiver, High Pass Function This JTF (HH in Figure 152) mimics the receiver’s ability to track lower frequency jitter components (wander, SSC) and not include them in the jitter measurement. This measurement methodology enables any measurement instrument to accurately measure the jitter seen by a receiver and produce measurements that correlate from measurement instrument to measurement instrument. It should be noted that the corner frequency of the JTF is not the corner frequency of the clock recovery CLTF. This may not be obvious until one considers the phase shift caused by the clock recovery circuit. In general the vector sum HL(f) + HH(f) = 1. All quantities consist of changing magnitude and phase as a function of frequency. This accounts for differences in corner frequencies and peaking in the two frequency dependant functions. Figure 153 shows more detail into how the JTF and CLTF relate to the jitter that would be applied to a receiver. The subfigure A) represents a generic control system block diagram for a feedback loop based clock recovery system. Subfigure B) translates the same complex variables to the combined system of the clock recovery circuit and the time difference function. It can be seen that E(s) is the jitter seen by the receiver, as well as being the error signal in the clock recovery circuit. Subfigure C) provides the defining equations for the clock recovery circuit CLTF and the combined system JTF function. Serial ATA Revision 3.0 Gold Revision page 285 of 663 Both the CLTF and the JTF are uniquely defined by the open loop transfer function G(s). Defining a CLTF does not uniquely define the G(s) and subsequently the JTF due to the level of cancellation of G(s) in the numerator and denominator of the CLTF especially when G(s) is much greater than 1, which is necessary for jitter tracking by the clock recovery circuit. This is the rational for Gen2i, Gen2m, and Gen3i: directly specifying the JTF rather than the CLTF of the clock recovery circuit. When the JTF of a JMD meets the requirements specified, the JMD reported jitter levels will closer represent the jitter applied to the receiver in this reference design. A) Generic Clock Recovery Circuit R(s) + E(s) C(s) Σ G(s) - H(s) = 1 B) Clock Recovery Circuit with Time Difference R(s) Clock Recovery Circuit Jitter seen by + the Receiver E(s) - C(s) Time Difference C) Defining Equations for the JTF and the CLTF E(s) 1 JTF = R(s) = 1 + G(s) CLTF = C(s) R(s) = 1 G(s) + G(s) Equations valid for unity gain feedback: H(s) = 1 All quantities consist of Magnitude and Phase Figure 153 – JTF and CLTF Definition 7.4.8.1 Jitter Measurements with a Bit Error Rate Tester (BERT) Most instruments used to measure jitter are unable to directly measure TJ at very low bit error rates like 10-12 due to the time it would take to capture sufficient transitions for a statistically significant direct measurement. Instead, these instruments capture a smaller sample size and extrapolate TJ using complex, and in some cases proprietary, algorithms. The determination of TJ through extrapolation may greatly reduce the amount of time required to measure jitter but experience has shown different extrapolation-based methods may produce different results. An alternate method to measure TJ is through the use of a BERT scan method. Since a BERT scan may directly measure jitter to 10-12 and even lower rates in a reasonable amount of time, it also provides a means of reconciling any differences in the extrapolated value of TJ. A BERT scan method utilizes the variable clock-to-data timing path available on a BERT. In addition to this, a PLL inside or outside the BERT that meets the requirements described in section 7.3.2 shall be used to generate the clock reference. The BERT scan systematically increases or decreases the clock-to-data timing and directly measures the BER performance at each increment of time. This is done until the time skew is found for the desired BER rate on each Serial ATA Revision 3.0 Gold Revision page 286 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization side of a Unit Interval. BER rates directly measured at each timing point on the left and right of a UI may be plotted to produce what is known as a bathtub curve. The time for one UI minus the time between the curves at the desired bit error rate is TJ. If those points on the bathtub curve are from directly measured data and not extrapolated, the TJ is a direct measure of TJ. Alternatively, the BERT scan is done to the left and right of the nominal zero crossing time relative to the Reference Clock to directly measure the tails of the Cumulative Distribution Function (CDF) histogram. The width of this histogram at the desired BER is TJ at that BER. Methods do exist to extrapolate TJ on a BERT from time scan values at higher rates. While such methods may be used to predict TJ at a desired BER, only a direct measure all the way to the desired BER shall be used when using the BERT as a jitter standard for comparison to extrapolation methods. The standard also requires a measure of DJ for compliance testing. All measures of DJ are statistically based including the estimations of DJ from a BERT. If a BERT is being used to measure TJ, the TJ values determined by that BERT may be used to estimate the DJ. Methods of estimating DJ from BERT TJ values are described in the public domain.5 These methods involve the measurements of TJ at different BER levels using the BERT scan. When measuring TJ and extracting the DJ and RJ components, it is common to encounter RJ measurements that are higher than actual random jitter. This is often encountered in systems where noise from the system causes jitter that is not correlated with the Serial ATA channel activity. For example, power supply noise from a system, which contaminates a transmitter’s bit clock generator, may cause variations in the bit clock which impact jitter directly. When making random jitter measurements, this non-correlated DJ is often included in the result which, when multiplied by 14 may lead to non-compliance to jitter specifications. This is inappropriate since non-correlated DJ is bounded, non-Gaussian and should not be multiplied by 14. Furthermore, non-correlated DJ is included in normal DJ measurements. Extracting non-correlated DJ from RJ measurement lies beyond the scope of this document since it usually requires in-depth knowledge of the characteristics of the non-correlated DJ and an appropriate algorithm for its measurement/extraction. Consequently, it is the readers’ responsibility to characterize and then extract non-correlated DJ from their RJ measurements. 7.4.9 Transmit Jitter (Gen1i, Gen2i, Gen1m, Gen2m, Gen1x, and Gen2x) The transmit jitter values specified in Table 31 refer to the output signal from the unit under test (UUT) at the mated connector into a Laboratory Load (LL) (for Gen1i, Gen2i, Gen1m, Gen2m, Gen1x, and Gen2x), or from the unit under test through a Compliance Interconnect Channel (CIC) into a Laboratory Load (for Gen1x and Gen2x). The signals are not specified when attached to a system cable or backplane. All the interconnect characteristics of the transmitter, package, printed circuit board traces, and mated connector pair are included in the measured transmitter jitter. Since the SATA adapter is also included as part of the measurement, good matching and low loss in the adapter are desirable to minimize its contributions to the measured transmitter jitter. Transmit jitter is measured with each of the specified patterns in section 7.2.4.1. The measurement of jitter is described in section 7.4.8. Transmit jitter is measured in one of the 5 “Estimation of Small Probabilities by Linearization of the Tail of a Probability Distribution Function” by S.B. Weinstein, IEEE Transactions on Communications Technology, Vol. COM-19, No. 6, December 1971. Serial ATA Revision 3.0 Gold Revision page 287 of 663 following two setups for Gen2i and both setups for Gen1x and Gen2x. For Gen1i, Gen2i, Gen1x, and Gen2x the transmitter is connected directly into the Laboratory Load (LL) shown in Figure 154. Additionally, for Gen1x and Gen2x the transmitter is connected through the Compliance Interconnect Channel (see section 7.2.7) into the Laboratory Load shown in Figure 155. TX Signals from UUT Host / Device Compliance Point SATA Adapter (Receptacle) Transmitter Under Test SATA Mated Connector Pair DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms 50 Ohms HBWS / JMD Laboratory Load (LL) Figure 154 – Transmitter Jitter Test (Gen1i, Gen2i) TX Signals from UUT SATA Adapter (Receptacle) SMA Connectors Compliance SATA Adapter Point (Plug) DC Block (As required) Host / Device Transmitter Under Test SATA Mated Connector Pair Compliance Interconnect Channel (With losses greater than TCTF and SATA Mated Connector Pair SATA Adapter (Receptacle) meeting ISI loss limit and SMA connectors.) Laboratory Load (LL) HBWS / JMD Figure 155 – Transmit Jitter Test with Compliance Interconnect Channel (Gen1x, Gen2x) Transmitter jitter is measured into the Laboratory Load (LL), or in conjunction with the Compliance Interconnect Channel; both have very good impedance matching. The jitter in an actual system is higher since load and interconnect mismatch results in reflections and additional data dependent jitter. It is generally not possible to remove the effects of the SATA adapter on jitter since jitter due to mismatch depends on the entire test setup. Serial ATA Revision 3.0 Gold Revision page 288 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.4.10 Transmit Jitter (Gen3i) The Transmit Jitter values specified in Table 31 refer to the output signal from the unit under test (UUT) at the mated connector into a Laboratory Load (LL) when measuring Random Jitter (RJ) or from the unit under test through a Compliance Interconnect Channel (CIC) into a Laboratory Load when measuring Total Jitter (TJ). The signals are not specified when attached to a system cable or backplane. All the interconnect characteristics of the transmitter, package, printed circuit board traces, and mated connector pair are included in the measured transmitter jitter. Since the SATA adapter is also included as part of the measurement, good matching and low loss in the adapter are desirable to minimize its contributions to the measured transmitter jitter. The Random Jitter is measured with a MFTP pattern and the Total Jitter is measured with each of the specified patterns in section 7.2.4.1 and section 7.2.4.3.4. The measurement of jitter is described in section 7.4.8. First, the Random Jitter of a Gen3 MFTP pattern is measured directly into the Laboratory Load as is shown in Figure 156. The measured value shall meet the Transmit Jitter level for Random Jitter (RJ) for Gen3i in Table 31. The actual measured value of Random Jitter during this test is referred to as the Measured Random Jitter (RJmeas) and is used to calculate the allowable TJ level for the second Transmitter Jitter Test, so this value needs to be recorded. Figure 156 – Transmitter Random Jitter Test (Gen3i) The second Transmit Jitter test measures the Total Jitter (TJ) through the Gen3i Compliance Interconnect Channel (see Section 7.2.7) into the Laboratory Load as is shown in Figure 157. The allowable Total Jitter (TJ) level is calculated based on the equation in Section 7.4.8 that defines Total Jitter as the sum of Deterministic Jitter (DJ) plus 14 times the standard deviation of the Random Jitter (RJ). The maximum DJ level to be added to the RJmeas value obtained in the first Transmit Jitter test is listed in Table 31. The sum of the RJmeas and the allowable DJ defines the maximum TJ level that the Transmit Jitter shall have. The measured RJ from a JMD is typically reported as a standard deviation value (one sigma). The RJ must be multiplied by 14 to convert it to a peak-to-peak value before adding it to the allowable DJ level, which is a peak-to-peak value. Serial ATA Revision 3.0 Gold Revision page 289 of 663 To clarify the maximum allowable TJ calculation for the second test, the following example is provided. The values in Table 31 provide the Gen3i TX Jitter compliance requirements. The following values are only an example. If the maximum allowable RJ is 0.18 UI p-p and the actual measured RJ (RJmeas) from the first Transmit Jitter test is 0.10 UI p-p (1.19 ps 1 sigma) and the allowable DJ addition is 0.34 UI p-p, then the maximum allowable TJ for the second Transmit Jitter test is: TJ (UI p-p) = DJ (UIp-p) + RJmeas (UI p-p) = 0.34 (UI p-p) + 0.10 (UI p-p) = 0.44 (UI p-p). This is the maximum allowed TJ for the transmitter under test. It can be seen that if the RJmeas from the first test is at the maximum limit of 0.18 (UI p-p) and the allowable DJ addition is 0.34 (UI p-p), then the maximum allowable TJ is 0.52 (UI p-p). TX signals from UUT Compliance Point Host / Device SATA Adapter (Receptacle) 50 Ohm Cables CIC M M 50 Ohms 50 Ohms Transmitter Under Test SATA Mated Connector Pair (Signal Flow ) JMD CIC - Laboratory Load (LL) Figure 157 – Transmitter Total Jitter Test (Gen3i) The Transmit Jitter shall meet both requirements as listed in Table 31 using the methods of the first test for RJ and the second test for TJ defined in this section. The methods used for Gen3i Transmit Jitter testing are intended to minimize RJ measurement error and allow for the TJ to be verified by a full population BERT scan as described in Section 7.4.8. This method also puts an upper limit on both DJ and RJ so neither may dominate the TJ. Transmitter jitter is measured into the Laboratory Load (LL), or in conjunction with the Compliance Interconnect Channel; both have very good impedance matching. The jitter in an actual system is higher since load and interconnects mismatch results in reflections and additional data dependent jitter. It is generally not possible to remove the effects of the SATA adapter on jitter since jitter due to mismatch depends on the entire test setup. 7.4.11 Receiver Tolerance (Gen1i, Gen2i, Gen1m, Gen2m, Gen1x, and Gen2x) The performance measure for receiver tolerance and common mode interference rejection is the correct detection of data by the receiver. When measuring receiver and Common Mode tolerance it is necessary to set the maximum allowable jitter and common mode interference on the signal sent to the receiver and monitor data errors. The data signal source provides a data signal with jitter, and a controlled rise/fall time, with matched output impedance. The sine wave source provides common mode interference with matched output impedance. The two sources are combined with resistive splitters into the receiver under test (see Figure 159). Equivalent signal generation methods that provide the data with jitter, common mode interference, and an impedance-matched output are allowed. All the Serial ATA Revision 3.0 Gold Revision page 290 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization interconnect characteristics of the receiver, mated connector pair, printed circuit board traces, and package are included in the measured receiver jitter tolerance. Figure 158 shows a setup to set the level of jitter and common mode signal at the compliance point, on the cable side of the mated pair connector. The JMD is used as the standard for measuring jitter, and the HBWS is used as the standard for measuring the common mode interference. Since the SATA adapter is not included when setting the level of jitter, good matching and low loss in the adapter are desirable to minimize contributions to the amount of receiver jitter used in testing. Unlike other measurements, it is generally not possible to remove the effects of the SATA adapter on jitter since jitter due to mismatch depends on the entire test setup. Figure 159 shows one example approach to generate the Lab-Sourced signal. The receiver tolerance test shall be conducted over variations in parameters SSC on and off, maximum and minimum rise and fall times, minimum and maximum amplitude, common mode interference over the specified frequency range, the test patterns LBP and the full payload COMP described in section 7.2.4.3, and jitter which includes random and deterministic jitter of various types: data dependent, periodic, duty cycle distortion. The receiver tolerance to the impairments is required over all signal variations. Compliance Point 50 Ohms 50 Ohms HBWS / JMD Common Mode Splitters Sine Wave Source DCB 50 Ohms 50 Ohm Cables Data Signal Source DCB DC Block (As required) 50 Ohms Figure 158 – Receiver Jitter and CM Tolerance Test—Setting Levels Serial ATA Revision 3.0 Gold Revision page 291 of 663 RX Signals from UUT Host / Device Compliance Point SATA Adapter (Receptacle) Receiver Under Test SATA Mated Connector Pair Common Mode Splitters Sine Wave Source DCB 50 Ohms 50 Ohm Cables Data Signal Source DCB DC Block (As required) 50 Ohms Lab Sourced Signal Figure 159 – Receiver Jitter and CM Tolerance Test 7.4.12 Receiver Tolerance (Gen3i) The performance measure for receiver tolerance and Common Mode interference rejection is the correct detection of data by the receiver. When measuring receiver and Common Mode tolerance it is necessary to set the maximum allowable jitter and Common Mode interference on the signal sent to the receiver and monitor data errors. The data signal source provides a data signal with jitter, and a controlled rise/fall time with a matched output impedance. Additional DJ (ISI) is added by the CIC. The sine wave source provides common mode interference with a matched output impedance. The two sources are combined with resistive splitters into the receiver under test (see Figure 162). Equivalent signal generation methods that provide the data with jitter, common mode interference, and an impedance-matched output are allowed. All the interconnect characteristics of the receiver, mated connector pair, printed circuit board traces, and package are included in the measured receiver jitter tolerance. To calibrate the test signal for Receiver Tolerance testing, the Data Signal Source is measured using two procedures, one for Random Jitter (RJ) and a second for Total Jitter (TJ) and the common mode signal content. The rise time and fall time of the Data Signal Source in the following figures shall meet the requirements listed in Table 33 for the Gen3i Lab Sourced Signal. This defines the signal rise time and fall time characteristics in the signal path before the CIC. This requirement shall be met using the rise time and fall time methods described in Section 7.4.4 Figure 160 show the test configuration for setting the Random Jitter (RJ) level as is defined in Table 33 for the Gen3i Lab Sourced Signal. The RJ level is set using a Gen3i MFTP pattern. This method minimizes the measurement errors of RJ, compared to the case when other signal degradations are present, and shall be done before adding additional jitter components and common mode signals. This second procedure is performed after the RJ level of the Data Signal Source is set, as described above. Figure 161 shows one example approach for setting the Total Jitter (TJ) and the common mode signal level. The actual calibration plane is at the SMA connectors that will be applied to the SATA to SMA adaptor during the Receiver Tolerance test. This is shown in Figure Serial ATA Revision 3.0 Gold Revision page 292 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 161 as a dotted vertical line. The JMD is used as the standard for measuring jitter, and the HBWS is used as the standard for measuring the common mode interference and signal amplitude. Since the SATA adapter is not included when setting the level of jitter, good matching and low loss in the adapter are desirable to minimize contributions to the amount of receiver jitter used in testing. Unlike other measurements, it is generally not possible to remove the effects of the SATA adapter on jitter since jitter due to mismatch depends on the entire test setup. The measurement of the minimum and maximum amplitude levels of the test signal at the calibration plane, are performed in the same method used for these parameters for the TX amplitude tests. (see Section 7.4.3 for required method) In general the maximum peak-to-peak amplitude of a Gen3 MFTP pattern is the maximum limit, and the minimum eye opening of a Gen3 LBP at a BER of 1E-12 is the minimum limit. Figure 162 shows the calibrated Lab Sourced Signal applied to the Receiver Under Test. The receiver tolerance test shall be conducted over variations in parameters SSC on and off, minimum and maximum amplitude, common mode interference over the specified frequency range, the test patterns LBP and the full payload COMP described in section 7.2.4.3, and jitter which includes the maximum random and deterministic jitter of various types: data dependent, periodic, duty cycle distortion. The receiver tolerance to the impairments is required over all signal variations. Figure 160 – Receiver Jitter and CM Tolerance Test – Setting RJ Level (Gen3i) Serial ATA Revision 3.0 Gold Revision page 293 of 663 Figure 161 – Receiver Jitter and CM Tolerance Test – Setting TJ and CM Levels (Gen3i) Figure 162 – Receiver Jitter and CM Tolerance Test (Gen3i) 7.4.13 Return Loss and Impedance Balance The purpose of the return loss and impedance balance specifications (for rates above Gen1) is to bound the additional data dependent jitter incurred when attaching a host/device into a system. The test setup for hosts and devices is impedance matched in both differential and common modes and has good impedance balance whereas the system environment may not. Additional data dependent jitter occurs in a system from these imperfections. The return loss of a host/device quantifies the effect on the level of reflections in the system and the impedance balance controls the conversion between differential and common modes. Serial ATA Revision 3.0 Gold Revision page 294 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization The differential return loss is defined as the magnitude of the differential mode reflection given a differential mode excitation, expressed in decibels. The common mode return loss is defined as the magnitude of the common mode reflection given a common mode excitation. The impedance balance is defined as the magnitude of the differential mode reflection given a common mode excitation. Each of these contributes to additional data dependent jitter in a system beyond that in a test setup. The differential mode signal is defined by vdm = v2 v1 idm = i2 i1 The common mode signal is defined by vcm = v2 + v1 2 icm = i2 + i1 2 The return loss is defined by the magnitude of the reflection coefficient RL = 20 log & This specification describes transmitter output impedance and receiver input impedance in terms of the magnitude of a reflection of a sine wave. In a lossless line, the return loss remains constant over position. Attenuation loss in the test setup causes the measured return loss to appear higher (better matched) than actual. Figure 163 shows a setup to compensate for the loss in the cables. The short and load are assumed standards with RF connectors, for example SMA type connectors. Load Load Short Short DCB 50 Ohm Cables DCB DC Block (As required) DCB 50 Ohm Cables DCB 50 Ohm VNA / TDR 50 Ohm 50 Ohm VNA / TDR 50 Ohm Figure 163 – Return Loss Test-Calibration Serial ATA Revision 3.0 Gold Revision page 295 of 663 A reflection test set allows the measurement of reflections in the differential mode, or in the common mode. It may consist of a TDR with processing software, a multiport vector network analyzer, hybrid couplers and directional bridges, or a 2-port vector network analyzer and processing software. Differential return loss, common mode return loss, and impedance balance may be measured with a 2-port vector network analyzer. The VNA is connected to the host/device and the S parameters are measured (with a 50 Ohm reference impedance). The differential return loss in terms of the mixed mode S parameters as well as the 2-port S parameters is given by RLDD11 = 20 log SDD11 = 20 log s11 + s22 s12 2 s21 The common mode return loss is given by RLCC11 = 20 log SCC11 = 20 log s11 + s22 + s12 + s21 2 The impedance balance is given by RLDC11 = 20 log S DC11 = 20 log s11 s22 + s12 2 s 21 where the mixed mode S parameters are measured with a 4-port VNA, or alternatively the 2-port S parameters are measured with a 2-port VNA. For the above equations, the mapping from single-ended to differential s-parameters assumes 50 Ohm single ended reference sources to 100 Ohm differential reference sources and 25 Ohm common-mode reference sources. Figure 164 shows a test setup for measuring differential return loss. Since the SATA adapter is not included, good matching and low loss in the adapter are desirable to minimize its contributions to the measured return loss. If measurements and SATA adapter are characterized with S parameters, it is possible to remove adapter and test setup effects through a deembedding process. Test adapter imperfections affect the measurement of the unit under test; they introduce measurement uncertainty. For example, the attenuation loss in the test adapter reduces the reflection from the unit under test making the measured return loss higher than actual. An attenuation loss of 0.5 dB (about 1 inch of PCB trace on FR4 at 5 GHz) causes the measured return loss to increase by 1 dB over actual. The return loss of the adapter may affect the measured return loss higher or lower as the reflection from the adapter either adds or subtracts from the reflection from the unit under test. A well-matched adapter with 20 dB return loss may affect the measurements of a unit under test with return loss of 5 dB by ± 1 dB. These effects are most pronounced at higher frequencies. The adapter affects the measured reflection by the following measurement uncertainty equation ( ) s11m = '00 + ' '01 10s11a + ' ' ' 01 10 11 s11a 2 Serial ATA Revision 3.0 Gold Revision page 296 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization where '10 and '01 are the attenuation loss, '00 is the input reflection, and '11 is the output reflection of the adapter. s11m is the measured reflection, and s11a is the actual reflection from the unit under test. The return loss is related to the reflection amplitude. For the most accurate measurements, the adapter effects should be characterized or calibrated, and then de-embedded or removed from the measurements. Signals to UUT Host / Device Receiver Transmitt Under Compliance Point SATA Adapter (Receptacle) SATA Mated Connector Pair DCB 50 Ohm Cables DCB 50 Ohms VNA/TDR 50 Ohms DC Block (As required) Figure 164 – Return Loss Test When measuring output impedance of transmitters the operating condition shall be during transmission of MFTP. This is to assure the measurement is performed during a mode of operation that represents normal operation. The amplitude of external excitation applied shall not exceed -13.2 dBm 50 Ohms (139 mVpp) single ended on each differential port of the transmitter. This number is derived from the maximum reflected signal that may be present at a transmitter. A maximum transmitted signal of 700mVppd (-5.14 dBm 50 Ohms, each differential side, HFTP maximum rise/fall time); reflecting off a receiver with a differential return loss of 8 dB and direct attach. When measuring input impedance of receivers the operating condition shall be during a PHYRDY Interface Power State (see section 8.1). The amplitude of external excitation applied shall not exceed –6.48 dBm 50 Ohms (300 mVpp) on each differential port of the receiver. This number is derived from the maximum signal that may be present at a receiver, 600 mVppd (Gen1i, -6.48 dBm 50 Ohms, each differential side). Serial ATA Revision 3.0 Gold Revision page 297 of 663 7.4.14 SSC Profile Spread Spectrum Clocking is intentional low frequency modulation of the bit clock. The SSC profile is the modulation on the bit clock. To measure the SSC profile, a frequency demodulator and low pass filter are necessary. There are many possible realizations of this, in hardware and software. The low pass filter is necessary to reject undesired post-demodulation frequency components from bit patterns and jitter. To minimize these undesired signals the HFTP bit pattern shall be used. This may be produced using the BIST Activate FIS to invoke the TransmitOnly option. The SSC Profile measurement is also used to determine the Unit Interval values. The Reference Clock as defined in section 7.3.2 should be used with an additional low pass filter in the phase detector output to measure the SSC profile. The output is DC coupled and should be calibrated with a signal source with sufficient long-term frequency accuracy. A single shot capture oscilloscope should be used to measure the times of zero crossings (through interpolation) and perform the FM demodulator and low pass filter function. The memory record of the oscilloscope shall be long enough to achieve the low pass filter cutoff frequency. The long term frequency accuracy of the oscilloscope time base should be significantly better than the 350 ppm limit in this specification; oscilloscopes that do not have this frequency accuracy may be calibrated using a separate signal source of sufficient accuracy into a separate channel. Modulation analysis tools with sufficient bandwidth provide alternative methods of measuring the SSC profile. These exist in some spectrum analyzers, modulation analyzers, or could be implemented as a separate frequency modulation receiver. Calibration is easier when the FM receiver has a DC coupled modulation path. The low pass filter 3 dB cutoff frequency shall be 60 times the modulation rate. The filter stopband rejection shall be greater or equal to a second order low-pass of 20 dB per decade. 7.4.15 Intra-Pair Skew Intra-pair skew measurements are important measurements of transmitters and receivers. For transmitters they are a measure of the symmetry of the SATA transmitter silicon (see Table 31). For receivers, they are a measure of the ability to handle signal degradation due to the interconnect. At a receiver, intra-pair skew adversely affects jitter levels. In a system, intra-pair skew has a direct impact on radiated emission levels. As the measurement values are typically just a few picoseconds, care should be taken to minimize measurement error. Figure 165 illustrates a test setup for a measurement method using a HBWS and its built-in processing. Each single-ended channel of a transmitter is measured into a Laboratory Load with DC blocks. Use HFTP and MFTP as the test patterns when measuring transmitter skew. A new displayed signal is formed by mathematically changing the polarity (arithmetic sign) and displayed with the original signal. This creates crossover points for each single ended signal, one displayed on the upper and the other on the lower part of the display. The example shown in Figure 168 of a transmitter, Ch5 and Ch6 are the two single-ended signals of the differential pair, the M5-trace is the inverted Ch5 (-Ch5), and M6 is the inverted Ch6 (-Ch6). Vertical cursors are used to measure the time between crossovers as the intra-pair skew. Receivers shall be tested to show required performance with the RX Differential Skew set to maximum as specified in Table 33. Skew may be created using test cables of differing propagation delay or active control by the data signal source within the Lab-Sourced Signal generator. Receiver skew may be setup at the same time as receiver amplitude as seen in Figure 166. Use the HFTP as the pattern when setting the skew. The skew measurement is performed as described above for the transmitter. Serial ATA Revision 3.0 Gold Revision page 298 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization TX Signals from UUT Host / Device Compliance Point SATA Adapter (Receptacle) Transmitter Under Test SATA Mated Connector Pair DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms 50 Ohms HBWS Laboratory Load (LL) Figure 165 – Intra-Pair Skew Test for a Transmitter 50 Ohms 50 Ohms HBWS Compliance Point DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms 50 Ohms Data Signal Source Figure 166 – Receiver Intra-Pair Skew Test—Setting Levels Signals to UUT Host / Device Compliance Point SATA Adapter (Receptacle) Receiver Under Test SATA Mated Connector Pair DCB 50 Ohm Cables DCB 50 Ohms Data Signal Source 50 Ohms DC Block (As required) Lab Sourced Signal Figure 167 – Receiver Intra-Pair Skew Test Serial ATA Revision 3.0 Gold Revision page 299 of 663 Figure 168 – Example Intra-Pair Skew test for Transmitter (10.8 pS) 7.4.16 Sequencing Transient Voltage Figure 169 shows the connections to the receiver or transmitter under test. Each RX or TX line is terminated to ground with a minimum impedance of 10 megohms that includes the probe and any external load. The value of the voltage transients during power on or power off sequencing, or power state changes seen at Vp or Vn, shall remain in the voltage range specified. Compliance Point Host / Device Transmitt or Under SATA Adapter (Receptacle) SATA Mated Connector Pair 50 Ohm Cables Vp 10 megohms min. 10 megohms min. Vn Figure 169 – TX/RX Sequencing Transient Voltage Measurement Serial ATA Revision 3.0 Gold Revision page 300 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.4.17 AC Coupling Capacitor This measurement is only applicable to AC coupled transmitters and receivers. The AC coupling capacitor value is not directly observable at the SATA connector. In order to measure this capacitance, each signal shall be probed on both sides of the AC coupling capacitor. The unit under test is powered off and nothing is plugged into the SATA connector. In the case of coupling within the IC or where there is no access to the signals between the IC and external coupling capacitors, this parameter is not measurable as shown. Figure 170 shows the connections to each coupling capacitor. Each coupling capacitor shall be lower than the specified maximum. IC Host / Device Receiver or Transmitter Under Test Compliance Point SATA Connector Coupling Capacitor Capacitance Meter Figure 170 – AC Coupled Capacitance Measurement 7.4.18 TX Amplitude Imbalance This parameter is a measure of the match in the single-ended amplitudes of the TX+ and TXsignals. The test setup shown Figure 144 shall be used for this measurement. This parameter shall be measured and met with both the HFTP and MFTP patterns. Clock-like patterns are used here to enable the use of standard mode-based amplitude measurements for the sole purpose of determining imbalance. The measurement of differential amplitude uses a different method. In order to determine the amplitude imbalance, single ended mode high and mode low based amplitudes of both TX+ and TX- over 10 to 20 cycles of the clock-like pattern being used shall be determined. The amplitude imbalance value for that pattern is then determined by the equation: absolute value(TX+ amplitude - TX- amplitude)/average where average is (TX+ amplitude + TX- amplitude)/2 The amplitude imbalance value for each pattern shall be less than the maximum listed in Table 31. 7.4.19 TX Rise/Fall Imbalance This parameter is a measure of the match in the simultaneous single-ended rise/fall or fall/rise times of the Transmitter. The test setup shown in Figure 144 shall be used for this measurement. This parameter shall be measured and met with both the HFTP and MFTP patterns. Serial ATA Revision 3.0 Gold Revision page 301 of 663 In order to determine the imbalance, the single ended 20-80% rise and fall times of both TX+ and TX- shall be determined for a given pattern. Two imbalance values for that pattern are then determined by the two equations: absolute value(TX+,rise – TX-,fall)/average, where average is (TX+,rise + TX-,fall)/2 absolute value(TX+,fall – TX-,rise)/average, where average is (TX+,fall + TX-,rise)/2 Both values for each pattern shall be less than the maximum listed in Table 31. 7.4.20 TX AC Common Mode Voltage (Gen2i, Gen2m) This parameter is a measure of common mode noise other than the CM spikes during transitions due to TX+/TX- mismatch and skews which are limited by the rise/fall mismatch and other requirements. Measurement of this parameter is achieved by transmitting through a mated connector into a Lab Load as shown in Figure 144. The transmitter shall use an MFTP (midfrequency test pattern). The measurement instrument may be a HBWS or other instrument with analog bandwidth of at least 3 * bitrate / 2. Separate channels shall be used for TX+ and TX- and the common mode is (TX+ + TX-) / 2. This raw common mode shall be filtered with a first order filter having a cutoff equal to the bitrate / 2 to remove the noise contribution from the edge mismatches. The peak-to-peak voltage of the filter output is the AC Common Mode Voltage and shall remain below the specified limit. 7.4.21 Tx AC Common Mode Voltage (Gen3i) A method to measure the common mode voltage is attaching a metrology-grade power combiner between the Tx+ and Tx- outputs of the transmitter; at the Device or Host transmit connector. Both outputs shall be joined to the combiner with phase matched cables having <= +/- 3 ps of mismatch, diminishing phase distortion during the measurement. The power combiner’s output is connected to a spectrum analyzer having sufficient bandwidth to measure the fundamental and 2nd harmonic frequencies of the data speed. (Example: 6.0 Gbps, fundamental = 3 GHz.) The measurement shall be made using a 1 MHz resolution bandwidth. The transmitter shall output the HFTP (D10.2) pattern during the test. Equivalent methods may be used. The dBmV level is understood to be: 0 dBmV = 1mV into 50 ohms. 7.4.22 OOB Common Mode Delta This parameter is a measure of the offset between the common mode voltage of idle times during OOB generation and the common mode voltage during the OOB bursts. The test setup shown in Figure 144 shall be used for this measurement. A HBWS or single-shot scope may be used for this measurement, the DUT shall be configured to send an OOB sequence or multiple OOB sequences, and the instrument shall be configured so that at least 40 Gen 1 UI worth of idle time before the first OOB burst in a sequence and at least 40 Gen 1 UI worth of burst activity in the first OOB burst of a sequence are observed. The common mode signal is (TX+ + TX-)/2 and the common mode voltage during idle for this parameter is determined by averaging the common mode voltage of a 40 Gen1 UI span of idle time within the last 60 Gen1 UI worth of time prior to the first OOB burst in a sequence. The average common mode voltage during active time for this parameter is determined by averaging the common mode voltage of a 40 Gen1 UI span of time within the first 60 Gen1 UI of the first burst in a sequence. The reason that the active span is taken within the first 60 Gen1 UI of the Serial ATA Revision 3.0 Gold Revision page 302 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization first burst in a sequence is to minimize the affect of AC coupling RC time constant on the resulting common mode offset if one exists. 7.4.23 OOB Differential Delta This parameter is a measure of the offset between the differential voltage of idle times during OOB generation and the average differential voltage during the OOB bursts. The test setup shown in Figure 144 shall be used for this measurement. A HBWS or single-shot scope may be used for this measurement, the DUT shall be configured to send an OOB sequence or multiple OOB sequences, and the instrument shall be configured so that at least 40 Gen 1 UI worth of idle time before the first OOB burst in a sequence and at least 40 Gen 1 UI worth of burst activity in the first OOB burst of a sequence are observed. The differential signal is TX+ - TX- and the differential voltage during idle for this parameter is determined by averaging the differential voltage of a 40 Gen1 UI span of idle time within the last 60 Gen1 UI worth of time prior to the first OOB burst in a sequence. The average differential voltage during active time for this parameter is determined by averaging the differential voltage of a 40 Gen1 UI span of time within the first 60 Gen1 UI of the first burst in a sequence. The use of a span of 40 Gen1 UI ensures that no matter what the starting time within the burst, the signal is DC balanced and the average represents the differential mean. The reason that the active span is taken within the first 60 Gen1 UI of the first burst in a sequence is to minimize the affect of AC coupling RC time constant on the resulting differential offset if one exists. 7.4.24 Squelch Detector Tests The squelch detector is an essential function in receiving OOB signaling. There are two conditions to test: when above the maximum threshold the detector shall detect, and when below the minimum threshold the detector shall not detect. Figure 171 shows the test setup to set the proper level of the OOB signal. Note the same method is used to calibrate the Lab-Sourced signal amplitude as in section 7.4.6. To ensure the proper detection, multiple tests shall be done and the statistics of the results presented to show compliance. Note: the pattern content in the OOB may affect the detection. The timing of the gaps in the OOB bursts shall be varied to ensure compliance to the OOB timing specification (see Table 34). 50 Ohm 50 Ohm HBWS Compliance Point DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms Data Signal Source with OOB Generation 50 Ohms Figure 171 – Squelch Detector Threshold Test—Setting Levels Serial ATA Revision 3.0 Gold Revision page 303 of 663 RX Signals to UUT Compliance Point Host / Device SATA Adapter (Receptacle) Receiver Under Test SATA Mated Connector Pair DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms Data Signal Source with OOB Generation 50 Ohms Figure 172 – Squelch Detector Threshold Test 7.4.25 OOB Signaling Tests OOB signaling is used to signal specific actions during conditions where the receiving interface is in an active mode, a low interface power state, or a test mode. This section specifies the set of test requirements to ensure that the OOB detector circuits comply with the OOB signaling sequences under various conditions. 7.4.25.1 Power-On Sequence 7.4.25.1.1 Calibration When the host controller performs impedance calibration, it shall adjust its own impedance such that the electrical requirements of section 7.2 are satisfied. 7.4.25.1.2 Speed Negotiation Speed negotiation and transition to lower serial interface data rates shall be implemented for higher data speed compatible interfaces, negotiating and transitioning down to lower data speed, as required. There is no requirement for speed negotiation and transition to lower speeds than Gen1. 7.4.25.1.3 Interface Power Management Sequences 7.4.25.1.4 Partial The interface shall detect the OOB signaling sequence COMWAKE and COMRESET when in the Partial Interface power management state. While in the Partial state, the interface shall be subjected to the low-transition density bit pattern (LTDP) sequences of section 7.2.4.3; the interface shall remain in the Partial state until receipt of a valid COMWAKE (or COMRESET) OOB signaling sequence. Power dissipation in this Partial state shall be measured or calculated to be less than the Phy Active state, but more than the Slumber state defined in section 8.1. The requirement for a "not-to-exceed" power dissipation limit in the Partial interface power management state is classified as vendor specific, and should be documented as part of the implementation performance specifications. Serial ATA Revision 3.0 Gold Revision page 304 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.4.25.1.5 Slumber The interface shall detect the OOB signaling sequence COMWAKE and COMRESET when in the Slumber Interface power management state. While in the Slumber state, the interface shall be subjected to the low-transition density bit pattern (LTDP) sequences of section 7.2.4.3; the interface shall remain in the Slumber state until receipt of a valid COMWAKE (or COMRESET) OOB signaling sequence. Power dissipation in this Slumber state shall be measured or calculated to be less than the Phy Ready state, and less than the Partial state defined in section 8.1. The requirement for a "not-to-exceed" power dissipation limit in the Slumber interface power management state is classified as vendor specific, and should be documented as part of the implementation performance specifications. 7.4.26 TDR Differential Impedance (Gen1i / Gen1m) This specification describes transmitter output impedance and receiver input impedance in terms of both the peak value of a reflection given an incident step of known risetime and also in terms of return loss. The return loss measurement shall be sufficient to verify compliance with Gen1 and Gen2 requirements. In order to ensure replacement of the test outlined below does not invalidate Gen1 designs passing the TDR differential impedance, that method shall be sufficient to verify compliance with Gen 1 requirements. Verification of compliance by both methods shall not be required. To achieve consistent measurements it is important to control the test conditions at the compliance point. These conditions include the signal launch (see section 7.2.6), the source match looking back into the test setup and TDR, the risetime and shape of the TDR edge, and the attenuation loss on the reflection return path to the TDR. There are various methods to control and remove the test setup effects. When measuring output impedance of transmitters the operating condition shall be during transmission of MFTP. This is to assure the measurement is performed during a mode of operation that represents normal operation. The amplitude of a TDR pulse or excitation applied to an active transmitter shall not exceed 139 mVpp (-13.2 dBm 50 ohms) single ended. This number is derived from the maximum reflected signal that may be present at a transmitter. A maximum transmitted signal of 700 mVppd reflecting off a receiver with a differential return loss of 8 dB and direct attach. Source match is a constant 100 Ohms differential impedance level on the TDR trace preceding the compliance point. This may be achieved by impedance controlled test setup or a calibration procedure. Figure 173 shows the setup to set the risetime at the device under test. The risetime shall be set accurately at the compliance point. The shape of the TDR edge at the compliance point is affected by the edge shape of the TDR generator, the attenuation loss in the test setup, and averaging done on the received signal at the TDR. Serial ATA Revision 3.0 Gold Revision page 305 of 663 50 Ohm 50 Ohm HBWS Compliance Point DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms TDR 50 Ohms Figure 173 – TDR Differential Impedance Test—Setting Risetime Since the SATA adapter is not included when setting risetime, good matching and low loss are necessary in the adapter to minimize errors in the measured TDR impedance. Signals to UUT Host / Device Compliance Point SATA Adapter (Receptacle) Receiver or Transmitter Under Test SATA Mated Connector Pair DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms TDR 50 Ohms Figure 174 – TDR Impedance Test 7.4.27 TDR Single-Ended Impedance (Gen1i / Gen1m) This specification describes transmitter single-ended output impedance and receiver single-ended input impedance in terms of the peak value of a reflection given an incident step of known risetime. To achieve consistent measurements it is important to control the test conditions at the compliance point. These conditions include the signal launch (see section 7.2.6), the source match looking back into the test setup and TDR, the risetime and shape of the TDR edge, and the attenuation loss on the reflection return path to the TDR. There are various methods to control and remove the test setup effects. Source match is a constant 50 Ohms single-ended impedance level on the TDR trace preceding the compliance point. This may be achieved by impedance controlled test setup or a calibration procedure. Figure 175 shows the setup to set the risetime at the device under test. The risetime shall be set accurately at the compliance point. The shape of the TDR edge at the compliance point is affected by the edge shape of the TDR generator, the attenuation loss in the test setup, and averaging done on the received signal at the TDR. Serial ATA Revision 3.0 Gold Revision page 306 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 50 Ohm 50 Ohm HBWS Compliance Point DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms TDR 50 Ohms Figure 175 – TDR Single-Ended Impedance Test—Setting Risetime Since the SATA adapter is not included when setting risetime, good matching and low loss are necessary in the adapter to minimize errors in the measured TDR impedance. Figure 178 shows the connections to the receiver or transmitter under test. For single-ended measurements, the TDR shall be set to produce simultaneous positive pulses on both signals of the pair. Single-ended impedance is the resulting (even mode) impedance of each signal observed independently. Both signals shall meet the single-ended impedance requirement. 7.4.28 DC Coupled Common Mode Voltage (Gen1i / Gen1m) This measurement is only applicable to DC coupled transmitters and receivers. The following measurement on an AC coupled signal or with AC coupled probing results in a value near or at 0 V. Figure 176 shows the connections to the receiver or transmitter under test. Each RX or TX line is terminated to ground with a minimum impedance of 10 megohms that includes the probe and any external load. The common mode is (Vp + Vn)/2 and this term shall be in the range specified. Compliance Point Vp 10 megohms min. Host / Device SATA Adapter (Receptacle) 50 Ohm Cables Transmitter or Receiver Under Test SATA Mated Connector Pair 10 megohms min. Vn Figure 176 – DC Coupled Common Mode Voltage Measurement Serial ATA Revision 3.0 Gold Revision page 307 of 663 7.4.29 AC Coupled Common Mode Voltage (Gen1i / Gen1m) This measurement is only applicable to AC coupled transmitters and receivers. The AC coupled common mode voltage is not directly observable at the SATA connector. In order to measure this voltage, each RX or TX signal shall be probed between the IC and AC coupling capacitor. In the case of coupling within the IC or where there is no access to the signals between the IC and external coupling capacitors, it is not measurable. Figure 177 shows the connections to the receiver or transmitter under test. Each RX or TX line is terminated to ground with a minimum impedance of 10 megohms that includes the probe and any external load. The common mode is (Vp + Vn)/2 and this term shall be in the range specified. Coupling Capacitor IC Host / Device Receiver or Transmitter Under Test SATA Connector Pair Compliance Point Vp 10 megohms min. 10 megohms min. Vn Figure 177 – AC Coupled Common Mode Voltage Measurement Signals to UUT Host / Device Compliance Point SATA Adapter (Receptacle) Receiver or Transmitter Under Test SATA Mated Connector Pair DCB 50 Ohm Cables DCB DC Block (As required) 50 Ohms TDR 50 Ohms Figure 178 – TDR Impedance Test Serial ATA Revision 3.0 Gold Revision page 308 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 7.4.30 Sequencing Transient Voltage - Laboratory Load (Gen3i) Error! Reference source not found. shows the connections to the receiver or transmitter under test. Each RX or TX line is terminated to ground using a laboratory load (see 7.2.2.4 for lab load definition). The value of the voltage transients during power on or power off sequencing, or power state changes seen at Vp or Vn, shall remain in the voltage range specified. In some laboratory load configurations additional DC blocking components are added. For this measurement there shall not be any additional DC blocking components added in the laboratory load. TX or RX Signals from UUT Host / Device Transmitter or Receiver Under Test Compliance Point SATA Adapter (Receptacle) SATA Mated Connector Pair Vp 50 Ohms 50 Ohm Cables 50 Ohms Vn HBWS Laboratory Load (LL) Figure 179 - Sequencing Transient Voltage Laboratory Load 7.5 Interface States 7.5.1 Out Of Band Signaling There shall be three Out Of Band (OOB) signals used/detected by the Phy: COMRESET, COMINIT, and COMWAKE. COMINIT, COMRESET and COMWAKE OOB signaling shall be achieved by transmission of either a burst of four Gen1 ALIGNP primitives or a burst composed of four Gen1 Dwords with each Dword composed of four D24.3 characters, each burst having a duration of 160 UIOOB. Each burst is followed by idle periods (at common-mode levels), having durations as depicted in Figure 180 and Table 49. Previous versions of Serial ATA allow only for the ALIGN sequence as legitimate OOB signal content. The alternate OOB sequence defined in this section has different characteristics than the ALIGN sequence in both the time and frequency domains. The use of alternate OOB signal content may lead to backwards incompatibility with Gen1 Phys designed to previous Serial ATA specification versions. Interoperability issues with Gen1 Phys designed to the earlier SATA specification arising from the use of alternate OOB signal content are the sole responsibility of the Phy transmitting this alternate content. During OOB signaling transmissions, the differential and common mode levels of the signal lines shall comply with the same electrical specifications as for normal data transmission, specified in section 7.2. In Figure 180 below, COMRESET, COMINIT, and COMWAKE are shown. OOB signals are observed by detecting the temporal spacing between adjacent bursts of activity, on the differential pair. It is not required for a receiver to check the duration of an OOB burst. Serial ATA Revision 3.0 Gold Revision page 309 of 663 Even though they are transmitted with apparent Gen1 timings, the OOB burst transmissions may be transmitted using Gen2 rise / fall times. Any spacing less than or greater than the COMWAKE detector off threshold in Table 34 shall negate the COMWAKE detector output. The COMWAKE OOB signaling is used to bring the Phy out of a power-down state (Partial or Slumber) as described in section 8.4.3.2. The interface shall be held inactive for at least the maximum COMWAKE detector off threshold in Table 34 after the last burst to ensure far-end detector detects the negation properly. The device shall hold the interface inactive no more than the maximum COMWAKE detector off threshold plus two Gen1 Dwords (approximately 228.3 ns) at the end of a COMWAKE to prevent susceptibility to crosstalk. COMRESET/COMINIT T1 T2 COMWAKE T1 T1 Figure 180 – OOB Signals Table 49 – OOB Signal Times Time T1 T2 Value 160 UIoob (106.7 ns nominal) 480 UIoob (320 ns nominal) 7.5.1.1 Idle Bus Status During the idle bus condition, the differential signal diminishes to zero while the common mode level remains. Common-mode transients, shall not exceed the maximum amplitude levels (Vcm,ac) cited in section 7.2, and shall settle to within 25 mV of the previous state common mode voltage within Tsettle,cm, cited in section 7.2. The following figure shows several transmitter examples, and how the transition to and from the idle state may be implemented. Serial ATA Revision 3.0 Gold Revision page 310 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Idle 10mA TX+ TX- 50 50 100 50 50 NOTE: Pass gate impedance plus resistor should be set to 50 total. TX+ Idle TX- 500mV 250mV 250mV <50 <50 <50 100 50 50 50 Figure 181 – Transmitter Examples Serial ATA Revision 3.0 Gold Revision page 311 of 663 5mA 50 50 100 50 Idle + - 50 250mV TX+ TX5mA 5mA 50 50 100 50 Idle + - 50 Undef. TX+ TX5mA Figure 182 – Transmitter Examples (Concluded) 7.5.1.2 COMRESET COMRESET always originates from the host controller, and forces a hardware reset in the device. It is indicated by transmitting bursts of data separated by an idle bus condition. The OOB COMRESET signal shall consist of no less than six data bursts, including inter-burst temporal spacing. The COMRESET signal shall be: 1) Sustained/continued uninterrupted as long as the system hard reset is asserted, or Serial ATA Revision 3.0 Gold Revision page 312 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 2) Started during the system hardware reset and ended some time after the negation of system hardware reset, or 3) Transmitted immediately following the negation of the system hardware reset signal. The host controller shall ignore any signal received from the device from the assertion of the hardware reset signal until the COMRESET signal is transmitted. Each burst shall be 160 Gen1 UI’s long (106.7 ns) and each inter-burst idle state shall be 480 Gen1 UI’s long (320 ns). A COMRESET detector looksfor four consecutive bursts with 320 ns spacing (nominal). Any spacing less than 175 ns or greater than 525 ns shall invalidate the COMRESET detector output. The COMRESET interface signal to the Phy layer shall initiate the Reset sequence shown in Figure 183 below. The interface shall be held inactive for at least 525 ns after the last burst to ensure far-end detector detects the negation properly. Host / Device On Host Releases COMRESET Host COMWAKE Host COMRESET Host Calibrate Host Releases COMWAKE Host Align Host D10.2 Host Data Host TX (Device RX) Device TX (Host RX) Device COMINIT Device Releases COMINIT Device Calibrate Device Align Device COMWAKE Device Data Figure 183 – COMRESET Sequence Description: 1. Host/device are powered and operating normally with some form of active communication. 2. Some condition in the host causes the host to issue COMRESET 3. Host releases COMRESET. Once the condition causing the COMRESET is released, the host releases the COMRESET signal and puts the bus in a quiescent condition. 4. Device issues COMINIT – When the device detects the release of COMRESET, it responds with a COMINIT. This is also the entry point if the device is late starting. The device may initiate communications at any time by issuing a COMINIT. 5. Host calibrates and issues a COMWAKE. 6. Device responds – The device detects the COMWAKE sequence on its RX pair and calibrates its transmitter (optional). Following calibration the device sends a six burst COMWAKE sequence and then sends a continuous stream of the ALIGN sequence starting at the device's highest supported speed. After ALIGNP Dwords have been sent Serial ATA Revision 3.0 Gold Revision page 313 of 663 for 54.6us (2048 nominal Gen1 Dword times) without a response from the host as determined by detection of ALIGNP primitives received from the host, the device assumes that the host cannot communicate at that speed. If additional speeds are available the device tries the next lower supported speed by sending ALIGNP Dwords at that speed for 54.6 us (2048 nominal Gen1 Dword times.) This step is repeated for as many slower speeds as are supported. Once the lowest speed has been reached without response from the host, the device enters an error state. 7. Host locks – after detecting the COMWAKE, the host starts transmitting D10.2 characters (see 7.6) at its lowest supported speed. Meanwhile, the host receiver locks to the ALIGN sequence and, when ready, returns the ALIGN sequence to the device at the same speed as received. A host shall be designed such that it acquires lock in 54.6us (2048 nominal Gen1 Dword times) at any given speed. The host should allow for at least 873.8 us (32768 nominal Gen1 Dword times) after detecting the release of COMWAKE to receive the first ALIGNP. This ensures interoperability with multi-generational and synchronous designs. If no ALIGNP is received within 873.8 us (32768 nominal Gen1 Dword times) the host restarts the power-on sequence – repeating indefinitely until told to stop by the Application layer. 8. Device locks – the device locks to the ALIGN sequence and, when ready, sends SYNCP indicating it is ready to start normal operation. 9. Upon receipt of three back-to-back non-ALIGNP primitives, the communication link is established and normal operation may begin. 7.5.1.3 COMINIT COMINIT always originates from the device and requests a communication initialization. It is electrically identical to the COMRESET signal except that it originates from the device and is sent to the host. It is used by the device to request a reset from the host in accordance to the sequence shown in Figure 184, below. Host / Device On Host TX (Device RX) Device TX (Host RX) Host COMWAKE Host Calibrate Host Releases COMWAKE Host Align Host D10.2 Host Data Device COMINIT Device Releases COMINIT Device Calibrate Device Align Device COMWAKE Device Data Figure 184 – COMINIT Sequence Serial ATA Revision 3.0 Gold Revision page 314 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Description: 1. Host/device are powered and operating normally with some form of active communication. 2. Some condition in the device causes the device to issues a COMINIT 3. Host calibrates and issues a COMWAKE. 4. Device responds – The device detects the COMWAKE sequence on its RX pair and calibrates its transmitter (optional). Following calibration the device sends a six burst COMWAKE sequence and then sends a continuous stream of the ALIGN sequence starting at the device's highest supported speed. After ALIGNP Dwords have been sent for 54.6 us (2048 nominal Gen1 Dword times) without a response from the host as determined by detection of ALIGNP primitives received from the host, the device assumes that the host cannot communicate at that speed. If additional speeds are available the device tries the next lower supported speed by sending ALIGNP Dwords at that speed for 54.6 us (2048 nominal Gen1 Dword times.) This step is repeated for as many slower speeds as are supported. Once the lowest speed has been reached without response from the host, the device enters an error state. 5. Host locks – after detecting the COMWAKE, the host starts transmitting D10.2 characters (see section 7.6) at its lowest supported speed. Meanwhile, the host receiver locks to the ALIGN sequence and, when ready, returns the ALIGN sequence to the device at the same speed as received. A host shall be designed such that it acquires lock in 54.6 us (2048 nominal Gen1 Dword times) at any given speed. The host should allow for at least 873.8 us (32768 nominal Gen1 Dword times) after detecting the release of COMWAKE to receive the first ALIGNP. This ensures interoperability with multi-generational and synchronous designs. If no ALIGNP is received within 873.8 us (32768 nominal Gen1 Dword times) the host restarts the power-on sequence – repeating indefinitely until told to stop by the Application layer. 6. Device locks – the device locks to the ALIGN sequence and, when ready, sends SYNCP indicating it is ready to start normal operation. 7. Upon receipt of three back-to-back non-ALIGNP primitives, the communication link is established and normal operation may begin. 7.5.1.4 COMWAKE COMWAKE may originate from either the host controller or the device. It is signaled by transmitting six bursts of data separated by an idle bus condition. The OOB COMWAKE signaling shall consist of no less than six data bursts, including inter-burst temporal spacing. Each burst shall be 160 Gen1 UI long and each inter-burst idle state shall be 160 Gen1 UI long. A COMWAKE detector looks for four consecutive burst with a 106.7 ns spacing (nominal). Any spacing less than 35 ns or greater than 175 ns shall invalidate the COMWAKE detector output. The COMWAKE OOB signaling is used to bring the Phy out of a power-down state (Partial or Slumber) as described in section 8.1. The interface shall be held inactive for at least 175 ns after the last burst to ensure far-end detector detects the negation properly. The device shall hold the interface inactive no more then 228.3 ns (175 ns + two Gen1 Dwords) at the end of a COMWAKE to prevent susceptibility to crosstalk. 7.5.1.5 Design Example (Informative) This section includes one possible design example for detecting COMRESET/COMINIT and COMWAKE. Other design implementations are possible as long as they adhere to the requirements listed in this specification. Serial ATA Revision 3.0 Gold Revision page 315 of 663 The output of the squelch detector is fed into four frequency comparators. When the period is within the window determined by the RC time constants for three consecutive cycles, the appropriate signal is asserted. Squelch I tdelay >= 143 ns ± 20% tdelay = 500 ns ±20% ( tdelay = 431 ns ±20% tdelay = 253 ns ±20% • tdelay = 143 ns ±20% tdelay = 84.4 ns ±20% Burst Width ( (Not Too Long Spacing Width Not Too Long (( reset dq dq dq dq ( Spacing Width Not Too Short COMINIT O Spacing Width ( (Not Too Long reset dq dq dq dq ( Spacing Width Not Too Short COMWAKE O Figure 185 – OOB Signal Detector The Squelch detector example below makes use of a receiver with built-in hysteresis to filter out any signal not meeting the minimum amplitude. The squelch detector receiver shall be true differential to ensure common-mode noise is rejected. The full-swing output is fed into a pulse generator that charges up the capacitor through the diode. In the absence of signal, a resistor discharges the capacitor to ground. The circuit outputs a true signal when the capacitor voltage is below the turn-on threshold of the Schmitt trigger buffer – indicating insufficient signal level. This circuit shall be enabled in all power management states and should, therefore, be implemented with a small power budget. Serial ATA Revision 3.0 Gold Revision page 316 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Figure 186, like the OOB Signal Detector figure shown in Figure 185, is intended to show functionality (informative) only, and other solutions may be used to improve power consumption as long as they comply to the electrical specifications of section 7.2, for the worst case noise environment (common-mode) conditions. RX+ I + RX- I ( Squelch O Figure 186 – Squelch Detector 7.5.2 Idle Bus Condition During power management states (Partial and Slumber), the electrical interface shall maintain the proper common-mode levels, as cited in section 7.2, with zero differential on both signal pairs (all four conductors at 250 mV) for all interface scenarios, except for the case where both, the device and the host-controller, are AC-coupled and the conductor pairs are allowed to float. All transmitter designs shall ensure that transition to and from the idle bus condition does not result in a disturbance in the differential baseline on the conductors. To accomplish this, an ACcoupled transmitter shall hold its outputs at zero differential with the same common-mode level as normal operation when in the Partial power management mode. When operating in the Slumber power management mode, the common mode level of the AC coupled transmitter is allowed to float (while maintaining zero differential) as long as it remains within the limits cited in section 7.2. It is unacceptable to hold the TX outputs at a logical zero or one state during the idle bus condition since this results in a baseline shift when communications are resumed. 7.6 Elasticity Buffer Management For non-tracking implementations elasticity buffer circuitry may be required to absorb the slight differences in frequencies between the host and device. The greatest frequency difference results from a SSC compliant device talking to a non-SSC device. The average frequency difference is just over 0.25% with excursions as much as 0.5%. The Serial ATA specification is written to support both tracking and non-tracking architectures. A non-tracking architecture shall contain the elasticity buffer within the Phy layer. Note that since this elasticity buffer is designed to have finite length, there needs to be a mechanism at the Phy layer protocol level that allows this receiver buffer to be reset without dropping or adding any bits to the data stream. This is especially important during reception of long continuous streams of data. This Phy layer protocol not only supports oversampling architectures but also accommodates unlimited frame sizes (the frame size is limited by the CRC polynomial). The Link layer shall keep track of a resettable counter that rolls over at most every 1024 transmitted characters (256 Dwords). Prior to, or at the pre-roll-over point (all 1's), the Link layer shall trigger the issuance of dual, consecutive ALIGNP primitives which shall be included in the Dword count. Serial ATA Revision 3.0 Gold Revision page 317 of 663 After communications have been established, the first and second words out of the Link layer shall be the dual-ALIGNP primitive sequence, followed by at most 254 non-ALIGNP Dwords. The cycle repeats starting with another dual-consecutive ALIGNP primitive sequence. The Link may issue more than one dual ALIGNP primitive sequence but shall not send an unpaired ALIGNP primitive (i.e. ALIGNP primitives are always sent in pairs) except as noted for retimed loopback. ALIGNP consists of the following four characters: (rd+) 1100000101 0101010101 0101010101 1101100011 (rd-) 0011111010 0101010101 0101010101 0010011100 Align1 (K28.5) Align2 (D10.2) Align3 (D10.2) Align4 (D27.3) Serial ATA Revision 3.0 Gold Revision page 318 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 8 OOB and Phy Power States 8.1 Interface Power States Serial ATA interface power states are controlled by the device and host controller. The interface power states are defined as described in Table 50. State PHYRDY Partial Slumber Table 50 – Interface Power States Description The Phy logic and main PLL are both on and active. The interface is synchronized and capable of receiving and sending data. The Phy logic is powered, but is in a reduced power state. Both signal lines on the interface are at a neutral logic state (common mode voltage). The exit latency from this state shall be no longer than 10 us unless when Automatic Partial to Slumber transitions is supported. When Automatic Partial to Slumber Transitions are enabled the exit latency from this state shall be no longer than the maximum Slumber exit latency. The Phy logic is powered but is in a reduced power state. The common mode level of the AC coupled transmitter is allowed to float (while maintaining zero differential) as long as it remains within the limits cited in Table 29 entry AC coupled common mode voltage. The exit latency from this state shall be no longer than 10 ms. 8.2 Asynchronous Signal Recovery (Optional) Phys may support asynchronous signal recovery for those applications where the usage model of device insertion into a receptacle (power applied at time of insertion) does not apply. When signal is lost, both the host and the device may attempt to recover the signal. A host or device shall determine loss of signal as represented by a transition from PHYRDY to PHYRDYn, which is associated with entry into states LSI: NoCommErr or LS2:NoComm within the Link layer. Note that negation of PHYRDY does not always constitute a loss of signal (e.g., Phy transition to Partial/Slumber). Recovery of the signal is associated with exit from state LS2:NoComm. If the device attempts to recover the signal before the host by issuing a COMINIT, the device shall return its signature following completion of the OOB sequence which included COMINIT. If a host supports asynchronous signal recovery, when the host receives an unsolicited COMINIT, the host shall issue a COMRESET to the device. An unsolicited COMINIT is a COMINIT that was not in response to a preceding COMRESET, as defined by the host not being in the HP2:HR_AwaitCOMINIT state when the COMINIT signal is first received. When a COMRESET is sent to the device in response to an unsolicited COMINIT, the host shall set the Status register to 7Fh and shall set all other Shadow Command Block Registers to FFh. When the COMINIT is received in response to the COMRESET which is associated with entry into state HP2B:HR_AwaitNoCOMINIT, the Shadow Status register value shall be updated to either FFh or 80h to reflect that a device is attached. 8.2.1 Unsolicited COMINIT Usage (Informative) Issuing a COMRESET to the device causes the device to lose software settings, other than the cases where software settings preservation is supported as described in section 13.5. If the COMRESET was due to asynchronous signal recovery and legacy mode (see section 4.1.72) software is in use, software does not replace the lost software settings. Issuing a non- Serial ATA Revision 3.0 Gold Revision page 319 of 663 commanded COMRESET to the device should be minimized in order to ensure robust operation with legacy mode software and avoid inadvertent loss of critical software settings. The use of unsolicited COMINIT was originally intended to only be used when the signal is lost between host and device. Based on the Host Phy Initialization state machine, the host shall assume that when receiving an unsolicited COMINIT that either a new device was connected or that the cable was unplugged and communication was lost to the device. The proper host response to an unsolicited COMINIT is to issue a COMRESET, putting the device into a known state. The device issuing an unsolicited COMINIT leads to a COMRESET from the host which could change the software settings of the device in such a way that legacy mode software cannot recover. To minimize potential for exposure to such indeterminate behavior, the device should only issue an unsolicited COMINIT when the Phy voltage threshold falls below the minimum value or as a last resort in error recovery. 8.3 OOB and Signature FIS return (Informative) After an OOB sequence, some devices compliant to older revisions of the Serial ATA specification may send a Register – Device to Host FIS with the device signature only if the device recognized COMRESET during the OOB. To ensure a robust host solution for compatibility with these older devices, the host may ensure at a system power-on event that the device always receives a valid COMRESET after power is determined good at the device. Hot plug aware software shall ensure that the device always receives a COMRESET on a hot plug event. One mechanism as a host workaround is to implement the following software procedure when determining device presence: 1. Wait for SError.DIAG.X to be set to one. 2. Clear SError.DIAG.X to zero by writing a one to that bit location. 3. Issue a COMRESET to the device (a valid COMINIT was received to set the X bit to one, thus power at the device is known to be good). 4. Wait up to 10 milliseconds for SError.DIAG.X to be set to one. 5. If SError.DIAG.X is not set after 10 milliseconds, go back to step 3 or exit if number of retries is exceeded. 6. At this point, the device is now required to transmit a Register FIS with the device signature. Other methods for ensuring that the device receives a COMRESET in these conditions are possible. 8.4 Power-On Sequence State Machine The following state diagrams specify the expected behavior of the host and device Phy from power-on to the establishment of an active communication channel. In those states where the Phy relies on detection of received ALIGNP primitives or comma sequences for state transitions, the Phy shall ensure accurate detection of the ALIGNP primitives at the compatible signaling speed, with adequate implementation safeguards to ensure that there is no misdetection of ALIGNP in the HP6:HR_AwaitAlign state in light of aliasing effects given the different data rates of ALIGNP primitives and D10.2’s in the incoming data streams. 8.4.1 Host Phy Initialization State Machine As described in section 7.5.1.3, reception of a COMINIT signal shall cause the host to reinitialize communications with the device. Implementations that do not support asynchronous signal recovery shall unconditionally force the Host Phy Initialization state machine to transition to the HP2B:HR_AwaitNoCOMINIT state when a COMINIT is received regardless of other conditions. Implementations that do support asynchronous signal recovery shall unconditionally force the Serial ATA Revision 3.0 Gold Revision page 320 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Host Phy Initialization state machine to transition to the HP1:HR_Reset state when an unsolicited COMINIT is received regardless of other conditions; if the COMINIT is not unsolicited the implementation shall force the Host Phy Initialization state machine to transition to the HP2B:HR_AwaitNoCOMINIT state regardless of other conditions. Reception of COMINIT is effectively an additional transition into the HP2B:HR_AwaitNoCOMINIT or HP1:HR_Reset state that appears in every Host Phy state. For the sake of brevity, this implied transition has been omitted from all the states. A state variable called ResumePending is used to track whether the Host Phy has been to a power management state such that re-establishing communications is as a result of a resume from a low power state. If a COMWAKE signal is not received when resuming from a low power state, the Host Phy shall allow the device to retransmit COMWAKE and shall not transmit a COMRESET to the device unless a COMRESET is explicitly triggered from a higher layer. If a COMWAKE signal is not received from the device when resuming from a low power state, the host may retransmit COMWAKE to the device. Designs that support asynchronous signal recovery have a state variable referred to as RetryInterval that determines the speed at which optional signal recovery polling is attempted. The value for RetryInterval shall be no shorter than 10 ms. Implementations that do not implement optional retry polling may consider the RetryInterval value to be infinite. Table 51 – State Diagram Host Phy Initialization State Machine HP1: HR_Reset Transmit COMRESET2,3,4. If asynchronous signal recovery is supported then clear ResumePending to 0. 1. Power-on reset and explicit reset request negated. HR_AwaitCOMINIT 2. Power-on reset or explicit reset request asserted. HR_Reset NOTES: 1. This state is entered asynchronously any time in response to power-on reset or an explicit reset request. For hosts supporting asynchronous signal recovery, this state is entered in response to receipt of a COMINIT signal from any state other than the HP2:HR_AwaitCOMINITor the HP2B:HR_AwaitNoCOMINIT state. 2. Shall transmit COMRESET for a minimum of 6 bursts (and a multiple of 6) 3. As described in section 7.5.1.2, COMRESET may be transmitted for the duration of this state, or it may be transmitted starting in this state and cease transmission after departure of this state, or it may be transmitted upon departure of this state. 4. Hosts that support asynchronous signal recovery shall complete transmission of COMRESET in response to a received COMINIT that causes a transition to this state within 10 ms of the de-qualification of the received COMINIT signal. HP2: HR_AwaitCOMINIT Interface quiescent. 1. COMINIT detected from device. 2. COMINIT not detected from device and (asynchronous signal recovery not supported or RetryInterval not elapsed since entry into the HP2:HR_AwaitCOMINIT state) . 3. COMINIT not detected from device and asynchronous signal recovery supported and RetryInterval elapsed since entry into the HP2:HR_AwaitCOMINIT state. HR_AwaitNoCOMINIT HR_AwaitCOMINIT HR_Reset Serial ATA Revision 3.0 Gold Revision page 321 of 663 HP2B: HR_AwaitNoCOMINIT Interface quiescent. 1. COMINIT not detected from device. HR_Calibrate 2. COMINIT detected from device. HR_AwaitNoCOMINIT NOTES: 1. For hosts that do not support asynchronous signal recovery, this state is entered asynchronously any time in response to COMINIT unless during a power-on reset or an explicit reset request (in which case HP1 is entered). HP3: HR_Calibrate Perform calibration1. 1. Calibration complete or bypass not implemented. HR_COMWAKE 2. Calibration not complete. HR_Calibrate NOTES: 1. Calibration is optional. If bypassed or not implemented, proceed directly to HR_COMWAKE. HP4: HR_COMWAKE Transmit COMWAKE. 1. COMWAKE not detected from device. 2. COMWAKE detected from device. HR_AwaitCOMWAKE HR_AwaitNoCOMWAKE HP5: HR_AwaitCOMWAKE Interface quiescent. 1. COMWAKE detected from device. 2. COMWAKE not detected from device and (asynchronous signal recovery not supported or RetryInterval not elapsed since entry into the HP5:HR_AwaitCOMWAKE state). 3. COMWAKE not detected from device and asynchronous signal recovery supported and RetryInterval elapsed since entry into the HP5:HR_AwaitCOMWAKE state and ResumePending = 0. 4. COMWAKE not detected from device and asynchronous signal recovery supported and RetryInterval elapsed since entry into the HP5:HR_AwaitCOMWAKE state and ResumePending = 1. HR_AwaitNoCOMWAKE HR_AwaitCOMWAKE HR_Reset HR_COMWAKE HP5B: HR_AwaitNoCOMWAKE Interface quiescent 1. COMWAKE not detected from device. 2. COMWAKE detected from device. HR_AwaitAlign HR_AwaitNoCOMWAKE Serial ATA Revision 3.0 Gold Revision page 322 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization HP6: HR_AwaitAlign Host transmits D10.2 characters at lowest supported rate2 1. AspLeIGedN)P3.detected from device (at any supported HR_AdjustSpeed 2. ALIGNP not detected from device and 873.8 us (32768 Gen1 Dwords) has elapsed since entry to HR_AwaitAlign. HR_Reset1,4 3. ALIGNP not detected from device and less than 873.8 us (32768 Gen1 Dwords) has elapsed since entry to HR_AwaitAlign. HR_AwaitAlign NOTES: 1. Host retries the power-on sequence indefinitely unless explicitly turned off by the Application layer. 2. Host shall start transmitting D10.2 characters no later than 533 ns (20 Gen1 Dwords) after COMWAKE is negated as specified in the OOB signaling section. 3. Host designers should be aware that the device is allowed 53.3 ns (2 Gen1 Dwords) after releasing COMWAKE (by holding the idle condition for more than 175 ns) to start sending characters. Until this occurs, the bus is at an idle condition and may be susceptible to crosstalk from other devices. Care should be taken so that crosstalk during this window doesn’t result in a false detection of an ALIGNP. For example: a compliant host may detect the negation of COMWAKE in as little as 112 ns, such a host should wait at least 116.3 ns (175+53.3-112) after detecting the release of COMWAKE to start looking for ALIGNP primitives. 4. The Host Phy Initialization state machine may use the transition to HR_Reset as a method of speed negotiation. HP7: HR_SendAlign Transmit ALIGNP at speed detected 1. Three back-to-back non-ALIGNP primitives2 detected from device. HR_Ready 2. Three back-to-back non-ALIGNP primitives not detected from device. HR_SendAlign1 NOTES: 1. Host retries indefinitely unless explicitly turned off by the Application layer 2. Non-ALIGNP primitives may be detected by the presence of the K28.3 control character in the Byte 0 position. Serial ATA Revision 3.0 Gold Revision page 323 of 663 HP8: HR_Ready Transmit word from Link1. 1. Partial signal from Link asserted. HR_Partial 2. Slumber signal from Link asserted. HR_Slumber 3. No power management request received and (asynchronous signal recovery not supported or signal recovery poll not initiated2 or received signal detected). HR_Ready 4. No power management request received and asynchronous signal recovery supported and received signal not detected and signal recovery poll initiated2. HR_Reset NOTES: 1. PHYRDY asserted only when in the HR_Ready state and the Phy is maintaining synchronization with the incoming signal to its receiver and is transmitting a valid signal on its transmitter. 2. The latency at which a host elects to initiate an optional signal recovery poll is implementation specific but shall be greater than the ALIGNP transmit interval. HP9: HR_Partial Interface quiescent. If asynchronous signal recovery is supported then set ResumePending = 1. 1. Partial signal from Link negated and no COMWAKE detected from device1,2. HR_COMWAKE 2. Partial signal from Link negated and COMWAKE detected from device1,2. HR_AwaitNoCOMWAKE 3. Slumber signal from the Link asserted and host Automatic Partial to Slumber transitions are supported3 HR_Slumber 4. Partial signal from Link asserted. HR_Partial NOTES: 1. Host Phy shall remember if COMWAKE was detected during Partial to determine if the wakeup request originated from the host or the Phy. 2. The host Phy may take this transition only after it has recovered from Partial mode and the Phy is prepared to initiate communications. If Phy has not yet recovered from the Partial mode it shall remain in this state. 3. The host Phy may transition to HR_Slumber if host Automatic Partial to Slumber transitions are supported by the host and device. Please refer to 13.16 for more information regarding Automatic Partial to Slumber transitions. Serial ATA Revision 3.0 Gold Revision page 324 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization HP10: HR_Slumber Interface quiescent. If asynchronous signal recovery is supported then set ResumePending = 1. 1. Slumber signal from Link negated and no COMWAKE detected from device1,2. HR_COMWAKE 2. Slumber signal from Link negated and COMWAKE detected from device1,2. HR_AwaitNoCOMWAKE 3. Slumber signal from Link asserted. HR_Slumber NOTES: 1. Host Phy shall remember if COMWAKE was detected during Slumber to determine if the wakeup request originated from the host or the Phy. 2. The host Phy may take this transition only after it has recovered from Slumber mode and the Phy is prepared to initiate communications. If Phy has not yet recovered from the Slumber mode it shall remain in this state. HP11: HR_AdjustSpeed Interface undefined but not quiescent1 1 Transition to appropriate speed completed. HR_SendAlign 2 Transition to appropriate speed not completed. HR_AdjustSpeed NOTES: 1. Some implementations may undergo a transient condition where invalid signals are transmitted during the change in their internal transmission/reception speed. The host may transmit invalid signals for a period of up to 53 ns (two Gen1 Dwords) during the speed transition. Transmit jitter and unit interval timing requirements may not be met during this period but shall be met for all other bits transmitted in this state. A phase shift may occur across the speed transition time. 8.4.2 Device Phy Initialization State Machine As described in section 7.5.1.2, reception of a COMRESET signal shall be treated by the device as a hardware reset signal and shall unconditionally force the Device Phy Initialization state machine to transition to the DP1:DR_Reset initial state regardless of other conditions. Reception of COMRESET is effectively an additional transition into the DP1:DR_Reset state that appears in every Device Phy state. For the sake of brevity, this implied transition has been omitted from all the states. Table 52 – State Diagram Device Phy Initialization State Machine DP1: DR_Reset1 Interface quiescent 1. COMRESET not detected and power-on reset negated. DR_COMINIT 2. COMRESET detected or power-on reset asserted. DR_Reset NOTES: 1. This state is entered asynchronously any time in response to power-on reset or receipt of a COMRESET signal from the host. DP2: DR_COMINIT Transmit COMINIT1, 2 1. Unconditional DR_AwaitCOMWAKE NOTES: 1. COMINIT transmitted for a 6 bursts duration 2. As indicated in section 13.1, devices shall respond with a COMINIT signal within 10 ms of Serial ATA Revision 3.0 Gold Revision page 325 of 663 DP2: DR_COMINIT Transmit COMINIT1, 2 the negation of power-on reset or de-qualification of a received COMRESET signal. DP3: DR_AwaitCOMWAKE Interface quiescent 1. COMWAKE detected from host 2. COMWAKE not detected from host and (asynchronous signal recovery not implemented or RetryInterval not elapsed since entry into the DP3:DR_AwaitCOMWAKE state). 3. COMWAKE not detected from host and asynchronous signal recovery implemented and RetryInterval elapsed since entry into the DP3:DR_AwaitCOMWAKE state. DR_AwaitNoCOMWAKE DR_AwaitCOMWAKE DR_Reset DP3B: DR_AwaitNoCOMWAKE Interface quiescent 1. COMWAKE not detected from host and part of power-on reset sequence1. DR_Calibrate 2. COMWAKE not detected from host and part of Partial/Slumber awake sequence1. DR_COMWAKE 3. COMWAKE detected from host. DR_AwaitNoCOMWAKE NOTES: 1. Device shall remember if it was sent to Partial or Slumber mode for proper wakeup action. DP4: DR_Calibrate Perform calibration1 1. Calibration complete or bypass not implemented. DR_COMWAKE 2. Calibration not complete. DR_Calibrate NOTES: 1. Calibration is optional. If bypassed or not implemented, proceed directly to DR_COMWAKE. DP5: DR_COMWAKE 1. Unconditional Transmit COMWAKE DR_SendAlign Serial ATA Revision 3.0 Gold Revision page 326 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization DP6: DR_SendAlign Transmit ALIGNP1,2,3,5 1. AinLcIoGmNinPgdedtaetcat)e4.d from host (device locked to DR_Ready 2. AprLimIGitNivPensotrtadnestmecittteeddffroorm54h.o6stuasn(2d0A4L8I5GGNePn1 ALIGNP primitives) at speed other than lowest6. DR_ReduceSpeed 3. AprLimIGitNivPensotrtadnestmecittteeddffroorm54h.o6stuasn(2d0A4L8I5GGNePn1 ALIGNP primitives) at lowest speed6. DR_Error 4. ALIGNP not detected from host and ALIGNP primitives transmitted for less than 54.6 us (2048 DR_SendAlign Gen1 ALIGNP primitives). NOTES: 1. If this is part of a recovery from a Slumber or Partial power management state, the device shall send ALIGNP at the previously negotiated speed. For all other cases, ALIGNP should be sent at the device's fastest supported speed. 2. ALIGNP primitives should be sent only at valid frequencies (if PLL not locked, send D10.2). 3. After COMWAKE is released as specified in the OOB signaling section, the device shall ensure the interface is active (not quiescent). 4. Device designers should be aware that the host is allowed 533 ns (20 Gen1 Dwords) after detecting the negation of COMWAKE to start sending D10.2 characters. Until this occurs, the bus is in an idle condition and may be susceptible to crosstalk from other devices. Care should be taken so that crosstalk during this window doesn’t result in a false detection of an ALIGNP. Devices may extend this timeout up to an additional 54.6 us (2048 Gen1 Dwords) (for a max total of 109.2 us), as necessary to allow their receiver time to lock to the host ALIGNP. 5. Device shall not leave the bus idle more than 53.3 ns (2 Gen1 Dwords) longer than the required 175 ns to negate COMWAKE. 6. If this is part of a recovery from the Slumber or Partial power management state, the device Phy shall not reduce its speed in response to failure to establish communications. Upon failing to establish communications it should instead transition directly to the DR_Error state to initiate a retry of the COMWAKE sequence. DP7: DR_Ready1 Transmit word from Link 1. Partial signal from Link asserted. DR_Partial 2. Slumber signal from Link asserted. DR_Slumber 3. No power management request received and (asynchronous signal recovery not supported or received signal detected). DR_Ready 4. No power management request received and asynchronous signal recovery supported and received signal not detected. DR_Error NOTES: 1. PHYRDY asserted only when in the DR_Ready state and the Phy is maintaining synchronization with the incoming signal to its receiver and is transmitting a valid signal on its transmitter. Serial ATA Revision 3.0 Gold Revision page 327 of 663 DP8: DR_Partial Interface quiescent 1. Partial signal from Link negated1 DR_COMWAKE 2. Partial signal from Link negated and COMWAKE detected from host1 DR_AwaitNoCOMWAKE 3. Slumber signal from Link asserted and device Automatic Partial to Slumber transitions enabled2 DR_Slumber 4. Partial signal from Link asserted DR_Partial NOTES: 1. The device Phy may take this transition only after it has recovered from Partial mode and the Phy is prepared to initiate communications. If Phy has not yet recovered from the Partial mode it shall remain in this state. 2. The device Phy may transition to DR_Slumber if device Automatic Partial to Slumber transitions are enabled. Please refer to 13.16 for more information regarding Automatic Partial to Slumber transitions. DP9: DR_Slumber Interface quiescent 1. Slumber signal from Link negated1 DR_COMWAKE 2. Slumber signal from Link negated and COMWAKE detected from host1 DR_AwaitNoCOMWAKE 3. Slumber signal from Link asserted DR_Slumber NOTES: 1. The device Phy may take this transition only after it has recovered from Slumber mode and the Phy is prepared to initiate communications. If Phy has not yet recovered from the Slumber mode it shall remain in this state. DP10: DR_ReduceSpeed Interface quiescent 1. Transition toa slower speed complete DR_SendAlign1 2. Transition to a slower speed not complete DR_ReduceSpeed NOTES: 1. Transition to a new speed is defined as being complete when the device is accurately transmitting a valid signal within the defined signaling tolerances for that speed. DP11: DR_Error Interface quiescent 1. Error not due to failure to resume and ((asynchronous signal recovery not supported) or (asynchronous signal recovery supported and RetryInterval not elapsed since entry into the DP11:DR_Error state)) 2. Resume from Slumber or Partial failed 3. Error not due to failure to resume and asynchronous signal recovery supported and RetryInterval elapsed since entry into the DP11:DR_Error state. DR_Error DR_COMWAKE DR_Reset Serial ATA Revision 3.0 Gold Revision page 328 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 8.4.3 Speed Negotiation In state HP6:HR_AwaitAlign, it is possible for the host to receive a signal at a speed different than what the host is awaiting (i.e. a Gen1 host may receive a Gen2 signal from the device or a Gen2 host may receive a Gen1 signal from the device). Some data recovery circuits may return unpredictable recovered data when presented with an incoming signaling speed higher than supported. Conversely, signal aliasing effects may impact the accuracy of decoded signals when a lower signaling speed than expected is received. Because the recovered data may be invalid, implementations shall insure that ALIGNP primitives are accurately decoded in the HP6:HR_AwaitAlign state in light of the possibility of recovered data in this state being the result of falsely decoding a signal at a speed different than the host is anticipating. To reduce susceptibility to false ALIGNP detection/handshake, receivers should fully qualify the entire received ALIGN sequence instead of relying on qualifying only a portion of it (such as just the comma sequence). Additional means for ensuring that the transition from the HP6:HR_AwaitAlign is accurately traversed and not traversed in response to a spurious signal from the data recovery circuit is to ensure that a series of contiguous ALIGNP primitives are successfully decoded. Other possible means for ensuring accuracy of the ALIGNP detection are also possible. It is the responsibility of the designs to ensure that the conditions and state transitions associated with the Phy initialization state machines are accurately performed and are not susceptible to false decoding/transition as a result of receiving a signal at a speed different than currently selected or at a speed that is not supported. Devices shall not rely on the host transmission of D10.2 as a means for determining host communication speed since the D10.2 transmission is done at the lowest supported communication speed and not necessarily at the highest mutually supported data speed being negotiated. The D10.2 transmission is only for the purpose of crosstalk suppression and for providing a reference clock; there is no protocol interlock on the D10.2 reception in the Device Phy Initialization state machine. 8.4.3.1 Power-On Sequence Timing Diagram The following timing diagrams and descriptions are provided for clarity and are informative. The state diagrams provided in section 8.4 comprise the normative behavior specification and is the ultimate reference. Serial ATA Revision 3.0 Gold Revision page 329 of 663 Host Power On Host Releases COMRESET Host COMWAKE Host Power Off Host COMRESET Host Calibrate Host Releases COMWAKE Host Align Host D10.2 Host Data Host TX (Device RX) Device TX (Host RX) Device Power Off Device COMINIT Device Power On Device Releases COMINIT Device Calibrate Device Align Device COMWAKE Figure 187 – Power-On Sequence Device Data Serial ATA Revision 3.0 Gold Revision page 330 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Description: 1. Host/device power-off - Host and device power-off. 2. Power is applied - Host side signal conditioning pulls TX and RX pairs to neutral state (common mode voltage). 3. Host issues COMRESET 4. Host releases COMRESET. Once the power-on reset is released, the host releases the COMRESET signal and puts the bus in a quiescent condition. 5. Device issues COMINIT – When the device detects the release of COMRESET, it responds with a COMINIT. This is also the entry point if the device is late starting. The device may initiate communications at any time by issuing a COMINIT. 6. Host calibrates and issues a COMWAKE. 7. Device responds – The device detects the COMWAKE sequence on its RX pair and calibrates its transmitter (optional). Following calibration the device sends a six burst COMWAKE sequence and then sends a continuous stream of the ALIGN sequence starting at the device's highest supported speed. After ALIGNP primitives have been sent for 54.6 us (2048 nominal Gen1 Dword times) without a response from the host as determined by detection of ALIGNP primitives received from the host, the device assumes that the host cannot communicate at that speed. If additional speeds are available the device tries the next lower supported speed by sending ALIGNP primitives at that speed for 54.6 us (2048 nominal Gen1 Dword times.) This step is repeated for as many slower speeds as are supported. Once the lowest speed has been reached without response from the host, the device shall enter an error state. 8. Host locks – after detecting the COMWAKE, the host starts transmitting D10.2 characters (see 7.6) at its lowest supported speed. Meanwhile, the host receiver locks to the ALIGN sequence and, when ready, returns the ALIGN sequence to the device at the same speed as received. A host shall be designed such that it acquires lock in 54.6 us (2048 nominal Gen1 Dword times) at any given speed. The host should allow for at least 873.8 us (32768 nominal Gen1 Dword times) after detecting the release of COMWAKE to receive the first ALIGNP. This insures interoperability with multi-generational and synchronous designs. If no ALIGNP is received within 873.8 us (32768 nominal Gen1 Dword times) the host restarts the power-on sequence – repeating indefinitely until told to stop by the Application layer. 9. Device locks – the device locks to the ALIGN sequence and, when ready, sends the SYNCP primitive indicating it is ready to start normal operation. 10. Upon receipt of three back-to-back non-ALIGNP primitives, the communication link is established and normal operation may begin. 8.4.3.2 Partial/Slumber to PHYRDY 8.4.3.2.1 Host Initiated The host may initiate a wakeup from the Partial or Slumber states by entering the power-on sequence at the “Host COMWAKE” point in the state machine. Calibration and speed negotiation is bypassed since it has already been performed at power-on and system performance depends on quick resume latency. The device, therefore, shall transmit ALIGNP primitives at the speed determined at power-on. 8.4.3.2.2 Device Initiated The device may initiate a wakeup from the Partial or Slumber states by entering the power-on sequence at the “Device COMWAKE” point in the state machine. Calibration and speed negotiation is bypassed since it has already been performed at power-on and system performance depends on quick resume latency. The device, therefore, shall transmit ALIGNP primitives at the speed determined at power-on. Serial ATA Revision 3.0 Gold Revision page 331 of 663 8.4.3.3 PHYRDY to Partial/Slumber 8.4.3.3.1 Host Initiated Host PMREQ_PP Host to Partial Partial Mode Host TX (Device RX) Device TX (Host RX) Device PMACK P Device to Partial Figure 188 – PHYRDY to Partial—Host Initiated Note: For Slumber, the same sequence applies except PMREQ_PP is replaced with PMREQ_SP and Partial is replaced with Slumber. Detailed Sequence: 1. Host Application layer sends request to host Transport layer. 2. Host Transport layer transmits request to host Link layer. 3. Host Link layer encodes request as PMREQ_PP primitive and transmits it to the host Phy layer. 4. Host Phy layer serializes PMREQ_PP primitives and transmits them to device Phy layer. 5. Device Phy de-serializes PMREQ_PP primitives and transmits them to device Link layer. 6. Device Link layer decodes PMREQ_PP primitives and transmits request to device Transport layer. 7. Device Transport layer transmits request to device Application layer. 8. Device Application layer processes and accepts request. Issues accept to device Transport layer. 9. Device Transport layer transmits acceptance to device Link layer. 10. Device Link layer encodes acceptance as PMACKP primitive and transmits it four times to device Phy layer. 11. Device Phy layer transmits between four and sixteen PMACKP primitives to host Phy layer. 12. Device Link layer places device Phy layer in Partial state. 13. Host Phy layer de-serializes PMACKP primitives and transmits them to host Link layer. 14. Host Link layer decodes PMACKP primitives and transmits acceptance to host Transport layer. 15. Host Link layer places host Phy layer in Partial State. Serial ATA Revision 3.0 Gold Revision page 332 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 16. Host Transport layer transmits acceptance to host Application layer. 8.4.3.3.2 Device Initiated Host to Partial Host PMACK P Host TX (Device RX) Device TX (Host RX) Device PMREQ_PP Partial Mode Device to Partial Figure 189 – PHYRDY to Partial—Device Initiated Detailed Sequence: 1. Device Application layer sends request to device Transport layer. 2. Device Transport layer transmits request to device Link layer. 3. Device Link layer encodes request as PMREQ_PP primitive and transmits it to device Phy layer. 4. Device Phy layer serializes PMREQ_PP primitives and transmits them to host Phy layer. 5. Host Phy de-serializes PMREQ_PP primitives and transmits them to host Link layer. 6. Host Link layer decodes PMREQ_PP primitives and transmits request to host Transport layer. 7. Host Transport layer transmits request to host Application layer. NOTE In this context, the host Application layer does not necessarily imply BIOS or other host CPU programming. Rather, the Application layer is the intelligent control section of the chipset logic. 8. Host Application layer processes and accepts request. Issues accept to host Transport layer. 9. Host Transport layer transmits acceptance to host Link layer. 10. Host link layer encodes acceptance as PMACKP and transmits it four times to host Phy layer. 11. Host Phy layer transmits between four and sixteen PMACKP primitives to device Phy layer. 12. Host Link layer asserts Partial signal and places host Phy layer in Partial state. 13. Host Phy layer negates PHYRDY signal. 14. Device Phy layer de-serializes PMACKP primitives and transmits them to device Link layer. Serial ATA Revision 3.0 Gold Revision page 333 of 663 15. Device Link layer decodes PMACKP primitives and transmits acceptance to device Transport layer. 16. Device Link layer asserts Partial signal and places device Phy layer in Partial State. 17. Device Phy layer negates PHYRDY signal. 18. Device Transport layer transmits acceptance to device Application layer. Serial ATA Revision 3.0 Gold Revision page 334 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 9 Link Layer 9.1 Overview The Link layer transmits and receives frames, transmits primitives based on control signals from the Transport layer, and receives primitives from the Phy layer which are converted to control signals to the Transport layer. The Link layer need not be cognizant of the content of frames. Host and device Link layer state machines are similar, however the device is given precedence when both the host and device request ownership for transmission. 9.1.1 Frame Transmission When requested by the Transport layer to transmit a frame, the Link layer provides the following services: Negotiates with its peer Link layer to transmit a frame, resolves arbitration conflicts if both host and device request transmission Inserts frame envelope around Transport layer data (i.e., SOFP, CRC, EOFP, etc.). Receives data in the form of Dwords from the Transport layer. Calculates CRC on Transport layer data. Transmits frame. Provides frame flow control in response to requests from the FIFO or the peer Link layer. Receives frame receipt acknowledge from peer Link layer. Reports good transmission or Link/Phy layer errors to Transport layer. Performs 8b/10b encoding Scrambles data Dwords in such a way to distribute the potential EMI emissions over a broader range 9.1.2 Frame Reception When data is received from the Phy layer, the Link layer provides the following services: Acknowledges to the peer Link layer readiness to receive a frame. Receives data in the form of encoded characters from the Phy layer. Decodes the encoded 8b/10b character stream into aligned Dwords of data. Removes the envelope around frames (i.e., SOFP, CRC, EOFP). Calculates CRC on the received Dwords. Provides frame flow control in response to requests from the FIFO or the peer Link layer. Compares the calculated CRC to the received CRC. Reports good reception or Link/Phy layer errors to Transport layer and the peer Link layer. Descrambles data Dwords received from a peer Link layer. 9.2 Encoding Method Information to be transmitted over Serial ATA shall be encoded a byte (eight bits) at a time along with a data or control character indicator into a 10-bit encoded character and then sent serially bit by bit. Information received over Serial ATA shall be collected ten bits at a time, assembled into an encoded character, and decoded into the correct data characters and control characters. The 8b/10b code allows for the encoding of all 256 combinations of eight-bit data. A subset of the control character set is utilized by Serial ATA. Serial ATA Revision 3.0 Gold Revision page 335 of 663 9.2.1 Notation and Conventions Serial ATA uses a letter notation for describing data bits and control variables. A description of the translation process between these notations follows. This section also describes a convention used to differentiate data characters from control characters. Finally, translation examples for both a data character and a control character are presented. An unencoded byte of data is composed of eight bits A,B,C,D,E,F,G,H and the control variable Z. The encoding process results in a 10 bit character a,b,c,d,e,i,f,g,h,j. A bit is either a binary zero or binary one. The control variable, Z, has a value of D or K. When the control variable associated with a byte has the value D, the byte is referred to as a data character. When the control variable associated with a byte has the value K, the byte is referred to as a control character. If a data byte is not accompanied with a specific control variable value the control variable Z is assumed to be Z = D and the data byte shall be encoded as a data character. Table 53 below illustrates the association between the numbered unencoded bits in a byte, the control variable, and the letter-labeled bits in the encoding scheme: Table 53 – Bit Designations Data Byte Notation Unencoded bit notation 7 6 5 4 3 2 1 0 Control Variable HGF E DCB A Z Each character is given a name Zxx.y where Z is the value of the control variable (D for a data character, K for a control character), xx is the decimal value of the binary number composed of the bits E, D, C, B and A in that order, and y is the decimal value of the binary number composed of the bits H, G and F. Figure 190 below, shows the relationship between the various representations. Byte + Control 7 65 4 3 2 1 0 Z Input to encode function 8 + control H GF E D C B A Z Encode function 8B/10B encoder Output from encode function abcdei f ghj 10 Phy transmission 0123456789 Bit 0 is transmitted first 76543210 Z Byte + Control 8 + control HGF E DCB A Output from Z decode function 8B/10B decoder Decode function abcdei f ghj 10 Input to decode function 0123456789 Phy reception Bit 0 is received first Figure 190 – Nomenclature Reference Serial ATA Revision 3.0 Gold Revision page 336 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Table 54 below shows conversions from byte notation to character notation for a control and data byte. The examples chosen have special significance and are also used during the conversion from data notation to the 8b/10b code values. Table 54 – Conversion Examples Byte Notation Bit notation Unencoded bit notation Bit notation reordered to conform with Zxx.y convention Character name BCh, Control Character 76543210 Control variable 10111100 K HGF EDCBA Z 101 11100 K Z EDCBA HGF K 11100 101 K 28 .5 4Ah, Data Character 76543210 Control variable 01001010 D HGF EDCBA Z 010 01010 D Z EDCBA HGF D 01010 010 D 10 .2 9.2.2 Character Code The coding scheme used by Serial ATA translates unencoded data and control bytes to characters. The encoded characters are then transmitted by the Phy layer over the serial line where they are received from the Phy layer and decoded into the corresponding byte and control value. Serial ATA uses a subset of the 8b/10b coding method described by Widmer and Franaszek (see references). The Serial ATA code uses all 256 data byte encodings while only two of the control codes are used. The reception of any unused code is a class of reception error referred to as a code violation. 9.2.2.1 Code Construction The 8b/10b coding process is defined in two stages. The first stage encodes the first five bits of the unencoded input byte into a six bit sub-block using a 5B/6B encoder. The input to this stage includes the current running disparity value. The second stage uses a 3B/4B encoder to encode the remaining three bits of the data byte and the running disparity as modified by the 5B/6B encoder into a four bit value. In the derivations that follow, the control variable (Z) is assumed to have a value of D, and thus is an implicit input. 9.2.2.2 The Concept of Running Disparity Running Disparity is a binary parameter with either the value negative (-) or the value positive (+). After transmitting any encoded character, the transmitter shall calculate a new value for its Running Disparity based on the value of the transmitted character. After a COMRESET, initial power-up, exiting any power management state, or exiting any diagnostic mode, the receiver shall assume either the positive or negative value for its initial Running Disparity. Upon reception of an encoded character the receiver shall determine whether the encoded character is valid according to the following rules and tables and shall calculate a new value for its Running Disparity based on the contents of the received character. Serial ATA Revision 3.0 Gold Revision page 337 of 663 The following rules shall be used to calculate a new Running Disparity value for the transmitter after it sends an encoded character (transmitter’s new Running Disparity) and for the receiver upon reception of an encoded character (receiver’s new Running Disparity). Running Disparity for an encoded character shall be calculated on two sub-blocks where the first six bits (abcdei) form one sub-block – the six-bit sub-block. The last four bits (fghj) form the second sub-block – the four-bit sub-block. Running Disparity at the beginning of the six-bit subblock is the Running Disparity at the end of the last encoded character or the initial conditions described above for the first encoded character transmitted or received. Running Disparity at the beginning of the four-bit sub-block is the resulting Running Disparity from the six-bit sub-block. Running Disparity at the end of the encoded character – and the initial Running Disparity for the next encoded character – is the Running Disparity at the end of the four-bit sub-block. Running Disparity for each of the sub-blocks shall be calculated as follows: Running Disparity at the end of any sub-block is positive if the sub-block contains more ones than zeros. It is also positive at the end of the six-bit sub-block if the value of the sixbit sub-block is 000111, and is positive at the end of the four-bit sub-block if the value of the four-bit sub-block is 0011. Running Disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones. It is also negative at the end of the six-bit sub-block if the value of the six-bit sub-block is 111000, and is negative at the end of the four-bit sub-block if the value of the four-bit sub-block is 1100. Otherwise, for any sub-block with an equal number of zeros and ones, the Running Disparity at the end of the sub-block is the same as at the beginning of the sub-block. Sub-blocks with an equal number of zeros and ones are said to have neutral disparity. The 8b/10b code restricts the generation of the 000111, 111000, 0011 and 1100 sub-blocks in order to limit the run length of zeros and ones between sub-blocks. Sub-blocks containing 000111 or 0011 are generated only when the running disparity at the beginning of the sub-block is positive, resulting in positive Running Disparity at the end of the sub-block. Similarly, subblocks containing 111000 or 1100 are generated only when the running disparity at the beginning of the sub-block is negative and the resulting Running Disparity will also be negative. The rules for Running Disparity will result in generation of a character with disparity that is either the opposite of the previous character or neutral. Sub-blocks with non-zero (non-neutral) disparity are of alternating disparity. 9.2.2.3 Data Encoding Table 55 and Table 56 describe the code and running disparity generation rules for each of the sub-blocks. The results may be used to generate the data in the data character tables. The digital logic which is used to generate the results may be found in Franaszek and Widmer [2] (see references). The generation of control characters is also covered in the patent but not here. In the tables which follow rd+ or rd- represent the current (incoming) running disparity and rd’ represents the resulting Running Disparity. The resulting Running Disparity columns use –rd to indicate a change in Running Disparity polarity while rd indicates the resulting sub-block has neutral disparity. Serial ATA Revision 3.0 Gold Revision page 338 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Table 55 – 5B/6B Coding Inputs abcdei Outputs rd’ Dx EDCBA rd+ rd- D0 00000 011000 100111 D1 00001 100010 011101 -rd D2 00010 010010 101101 D3 00011 110001 rd D4 00100 001010 110101 -rd D5 00101 101001 D6 00110 011001 rd D7 00111 000111 111000 D8 01000 000110 111001 -rd D9 01001 100101 D10 01010 010101 D11 01011 110100 rd D12 01100 001101 D13 01101 101100 D14 01110 011100 D15 01111 101000 010111 -rd Inputs abcdei Outputs rd’ Dx EDCBA rd+ rd- D16 10000 100100 011011 -rd D17 10001 100011 D18 10010 010011 D19 10011 110010 rd D20 10100 001011 D21 10101 101010 D22 10110 011010 D23 10111 000101 111010 -rd D24 11000 001100 110011 D25 11001 100110 rd D26 11010 010110 D27 11011 001001 110110 -rd D28 11100 001110 rd D29 11101 010001 101110 D30 11110 100001 011110 -rd D31 11111 010100 101011 Table 56 – 3B/4B Coding Inputs fghj Outputs rd’ Dx.y HGF rd+ rd- Dx.0 000 0100 1011 -rd Dx.1 001 1001 Dx.2 010 0101 rd Dx.3 011 0011 1100 Dx.4 100 0010 1101 -rd Dx.5 101 1010 rd Dx.6 110 0110 Dx.P7 111 0001 Dx.A7 111 1000 1110 -rd 0111 NOTES: A7 replaces P7 if[(rd>0) and (e=i=0)] or [(rd<0) and (e=i=1)] 9.2.2.4 Encoding Examples The encoding examples in Table 57 below illustrate how the running disparity calculations are done. The first conversion example completes the translation of data byte value 4Ah (which is the character name of D10.2) into an encoded character value of “abcdei fghj” = “010101 0101”. This value has special significance because (1) it is of neutral disparity, and also contains an alternating zero/one pattern that represents the highest data frequency which may be generated. Serial ATA Revision 3.0 Gold Revision page 339 of 663 In the second example the 8b/10b character named D11.7 is encoded. Assuming a positive value for the incoming Running Disparity, this example shows the Dx.P7/Dx.A7 substitution. With an initial rd+ value, D10 translates to an abcdei value of 110100b, with a resulting Running Disparity of positive for the 6-bit sub-block. Encoding the 4-bit sub-block triggers the substitution clause of Dx.A7 for Dx.P7 since [(rd>0) AND (e=i=0)]. Table 57 – Encoding Examples Initial rd - + Character Name D10.2 D11.7 abcdei Output 010101 110100 6-Bit SubBlock rd - + fghj Output 0101 1000 4-bit Subblock rd - - Encoded Character 010101 0101 110100 1000 Ending rd - - 9.2.2.5 8b/10b Valid Encoded Characters The following tables define the valid data characters and valid control characters. These tables shall be used for generating encoded characters (encoding) for transmission. In the reception process, the table is used to look up and verify the validity of received characters (decoding). In the tables, each data character and control character has two columns that represent two encoded characters. One column represents the output if the current Running Disparity is negative and the other is the output if the current Running Disparity is positive. Serial ATA Revision 3.0 Gold Revision page 340 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 9.2.2.5.1 Data Characters Table 58 – Valid Data Characters Name Byte D0.0 00h D1.0 01h D2.0 02h D3.0 03h D4.0 04h D5.0 05h D6.0 06h D7.0 07h D8.0 08h D9.0 09h D10.0 0Ah D11.0 0Bh D12.0 0Ch D13.0 0Dh D14.0 0Eh D15.0 0Fh D16.0 10h D17.0 11h D18.0 12h D19.0 13h D20.0 14h D21.0 15h D22.0 16h D23.0 17h D24.0 18h D25.0 19h D26.0 1Ah D27.0 1Bh D28.0 1Ch D29.0 1Dh D30.0 1Eh D31.0 1Fh abcdei fghj Output Current rd- Current rd+ 100111 0100 011000 1011 011101 0100 100010 1011 101101 0100 010010 1011 110001 1011 110001 0100 110101 0100 001010 1011 101001 1011 101001 0100 011001 1011 011001 0100 111000 1011 000111 0100 111001 0100 000110 1011 100101 1011 100101 0100 010101 1011 010101 0100 110100 1011 110100 0100 001101 1011 001101 0100 101100 1011 101100 0100 011100 1011 011100 0100 010111 0100 101000 1011 011011 0100 100100 1011 100011 1011 100011 0100 010011 1011 010011 0100 110010 1011 110010 0100 001011 1011 001011 0100 101010 1011 101010 0100 011010 1011 011010 0100 111010 0100 000101 1011 110011 0100 001100 1011 100110 1011 100110 0100 010110 1011 010110 0100 110110 0100 001001 1011 001110 1011 001110 0100 101110 0100 010001 1011 011110 0100 100001 1011 101011 0100 010100 1011 Name Byte D0.1 20h D1.1 21h D2.1 22h D3.1 23h D4.1 24h D5.1 25h D6.1 26h D7.1 27h D8.1 28h D9.1 29h D10.1 2Ah D11.1 2Bh D12.1 2Ch D13.1 2Dh D14.1 2Eh D15.1 2Fh D16.1 30h D17.1 31h D18.1 32h D19.1 33h D20.1 34h D21.1 35h D22.1 36h D23.1 37h D24.1 38h D25.1 39h D26.1 3Ah D27.1 3Bh D28.1 3Ch D29.1 3Dh D30.1 3Eh D31.1 3Fh abcdei fghj Output Current rd- Current rd+ 100111 1001 011000 1001 011101 1001 100010 1001 101101 1001 010010 1001 110001 1001 110001 1001 110101 1001 001010 1001 101001 1001 101001 1001 011001 1001 011001 1001 111000 1001 000111 1001 111001 1001 000110 1001 100101 1001 100101 1001 010101 1001 010101 1001 110100 1001 110100 1001 001101 1001 001101 1001 101100 1001 101100 1001 011100 1001 011100 1001 010111 1001 101000 1001 011011 1001 100100 1001 100011 1001 100011 1001 010011 1001 010011 1001 110010 1001 110010 1001 001011 1001 001011 1001 101010 1001 101010 1001 011010 1001 011010 1001 111010 1001 000101 1001 110011 1001 001100 1001 100110 1001 100110 1001 010110 1001 010110 1001 110110 1001 001001 1001 001110 1001 001110 1001 101110 1001 010001 1001 011110 1001 100001 1001 101011 1001 010100 1001 (continued) Serial ATA Revision 3.0 Gold Revision page 341 of 663 Table 58 – Valid Data Characters (continued) Name Byte D0.2 40h D1.2 41h D2.2 42h D3.2 43h D4.2 44h D5.2 45h D6.2 46h D7.2 47h D8.2 48h D9.2 49h D10.2 4Ah D11.2 4Bh D12.2 4Ch D13.2 4Dh D14.2 4Eh D15.2 4Fh D16.2 50h D17.2 51h D18.2 52h D19.2 53h D20.2 54h D21.2 55h D22.2 56h D23.2 57h D24.2 58h D25.2 59h D26.2 5Ah D27.2 5Bh D28.2 5Ch D29.2 5Dh D30.2 5Eh D31.2 5Fh abcdei fghj Output Current rd- Current rd+ 100111 0101 011000 0101 011101 0101 100010 0101 101101 0101 010010 0101 110001 0101 110001 0101 110101 0101 001010 0101 101001 0101 101001 0101 011001 0101 011001 0101 111000 0101 000111 0101 111001 0101 000110 0101 100101 0101 100101 0101 010101 0101 010101 0101 110100 0101 110100 0101 001101 0101 001101 0101 101100 0101 101100 0101 011100 0101 011100 0101 010111 0101 101000 0101 011011 0101 100100 0101 100011 0101 100011 0101 010011 0101 010011 0101 110010 0101 110010 0101 001011 0101 001011 0101 101010 0101 101010 0101 011010 0101 011010 0101 111010 0101 000101 0101 110011 0101 001100 0101 100110 0101 100110 0101 010110 0101 010110 0101 110110 0101 001001 0101 001110 0101 001110 0101 101110 0101 010001 0101 011110 0101 100001 0101 101011 0101 010100 0101 Name Byte D0.3 60h D1.3 61h D2.3 62h D3.3 63h D4.3 64h D5.3 65h D6.3 66h D7.3 67h D8.3 68h D9.3 69h D10.3 6Ah D11.3 6Bh D12.3 6Ch D13.3 6Dh D14.3 6Eh D15.3 6Fh D16.3 70h D17.3 71h D18.3 72h D19.3 73h D20.3 74h D21.3 75h D22.3 76h D23.3 77h D24.3 78h D25.3 79h D26.3 7Ah D27.3 7Bh D28.3 7Ch D29.3 7Dh D30.3 7Eh D31.3 7Fh abcdei fghj Output Current rd- Current rd+ 100111 0011 011000 1100 011101 0011 100010 1100 101101 0011 010010 1100 110001 1100 110001 0011 110101 0011 001010 1100 101001 1100 101001 0011 011001 1100 011001 0011 111000 1100 000111 0011 111001 0011 000110 1100 100101 1100 100101 0011 010101 1100 010101 0011 110100 1100 110100 0011 001101 1100 001101 0011 101100 1100 101100 0011 011100 1100 011100 0011 010111 0011 101000 1100 011011 0011 100100 1100 100011 1100 100011 0011 010011 1100 010011 0011 110010 1100 110010 0011 001011 1100 001011 0011 101010 1100 101010 0011 011010 1100 011010 0011 111010 0011 000101 1100 110011 0011 001100 1100 100110 1100 100110 0011 010110 1100 010110 0011 110110 0011 001001 1100 001110 1100 001110 0011 101110 0011 010001 1100 011110 0011 100001 1100 101011 0011 010100 1100 (continued) Serial ATA Revision 3.0 Gold Revision page 342 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Table 58 – Valid Data Characters (continued) Name Byte D0.4 80h D1.4 81h D2.4 82h D3.4 83h D4.4 84h D5.4 85h D6.4 86h D7.4 87h D8.4 88h D9.4 89h D10.4 8Ah D11.4 8Bh D12.4 8Ch D13.4 8Dh D14.4 8Eh D15.4 8Fh D16.4 90h D17.4 91h D18.4 92h D19.4 93h D20.4 94h D21.4 95h D22.4 96h D23.4 97h D24.4 98h D25.4 99h D26.4 9Ah D27.4 9Bh D28.4 9Ch D29.4 9Dh D30.4 9Eh D31.4 9Fh abcdei fghj Output Current rd- Current rd+ 100111 0010 011000 1101 011101 0010 100010 1101 101101 0010 010010 1101 110001 1101 110001 0010 110101 0010 001010 1101 101001 1101 101001 0010 011001 1101 011001 0010 111000 1101 000111 0010 111001 0010 000110 1101 100101 1101 100101 0010 010101 1101 010101 0010 110100 1101 110100 0010 001101 1101 001101 0010 101100 1101 101100 0010 011100 1101 011100 0010 010111 0010 101000 1101 011011 0010 100100 1101 100011 1101 100011 0010 010011 1101 010011 0010 110010 1101 110010 0010 001011 1101 001011 0010 101010 1101 101010 0010 011010 1101 011010 0010 111010 0010 000101 1101 110011 0010 001100 1101 100110 1101 100110 0010 010110 1101 010110 0010 110110 0010 001001 1101 001110 1101 001110 0010 101110 0010 010001 1101 011110 0010 100001 1101 101011 0010 010100 1101 Name Byte D0.5 A0h D1.5 A1h D2.5 A2h D3.5 A3h D4.5 A4h D5.5 A5h D6.5 A6h D7.5 A7h D8.5 A8h D9.5 A9h D10.5 AAh D11.5 ABh D12.5 ACh D13.5 ADh D14.5 AEh D15.5 AFh D16.5 B0h D17.5 B1h D18.5 B2h D19.5 B3h D20.5 B4h D21.5 B5h D22.5 B6h D23.5 B7h D24.5 B8h D25.5 B9h D26.5 BAh D27.5 BBh D28.5 BCh D29.5 BDh D30.5 BEh D31.5 BFh abcdei fghj Output Current rd- Current rd+ 100111 1010 011000 1010 011101 1010 100010 1010 101101 1010 010010 1010 110001 1010 110001 1010 110101 1010 001010 1010 101001 1010 101001 1010 011001 1010 011001 1010 111000 1010 000111 1010 111001 1010 000110 1010 100101 1010 100101 1010 010101 1010 010101 1010 110100 1010 110100 1010 001101 1010 001101 1010 101100 1010 101100 1010 011100 1010 011100 1010 010111 1010 101000 1010 011011 1010 100100 1010 100011 1010 100011 1010 010011 1010 010011 1010 110010 1010 110010 1010 001011 1010 001011 1010 101010 1010 101010 1010 011010 1010 011010 1010 111010 1010 000101 1010 110011 1010 001100 1010 100110 1010 100110 1010 010110 1010 010110 1010 110110 1010 001001 1010 001110 1010 001110 1010 101110 1010 010001 1010 011110 1010 100001 1010 101011 1010 010100 1010 (continued) Serial ATA Revision 3.0 Gold Revision page 343 of 663 Table 58 – Valid Data Characters (continued) Name Byte D0.6 D1.6 D2.6 D3.6 D4.6 D5.6 D6.6 D7.6 D8.6 D9.6 D10.6 D11.6 D12.6 D13.6 D14.6 D15.6 D16.6 D17.6 D18.6 D19.6 D20.6 D21.6 D22.6 D23.6 D24.6 D25.6 D26.6 D27.6 D28.6 D29.6 D30.6 D31.6 C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh abcdei fghj Output Current rd- Current rd+ 100111 0110 011000 0110 011101 0110 100010 0110 101101 0110 010010 0110 110001 0110 110001 0110 110101 0110 001010 0110 101001 0110 101001 0110 011001 0110 011001 0110 111000 0110 000111 0110 111001 0110 000110 0110 100101 0110 100101 0110 010101 0110 010101 0110 110100 0110 110100 0110 001101 0110 001101 0110 101100 0110 101100 0110 011100 0110 011100 0110 010111 0110 101000 0110 011011 0110 100100 0110 100011 0110 100011 0110 010011 0110 010011 0110 110010 0110 110010 0110 001011 0110 001011 0110 101010 0110 101010 0110 011010 0110 011010 0110 111010 0110 000101 0110 110011 0110 001100 0110 100110 0110 100110 0110 010110 0110 010110 0110 110110 0110 001001 0110 001110 0110 001110 0110 101110 0110 010001 0110 011110 0110 100001 0110 101011 0110 010100 0110 Name Byte D0.7 E0h D1.7 E1h D2.7 E2h D3.7 E3h D4.7 E4h D5.7 E5h D6.7 E6h D7.7 E7h D8.7 E8h D9.7 E9h D10.7 EAh D11.7 EBh D12.7 ECh D13.7 EDh D14.7 EEh D15.7 EFh D16.7 F0h D17.7 F1h D18.7 F2h D19.7 F3h D20.7 F4h D21.7 F5h D22.7 F6h D23.7 F7h D24.7 F8h D25.7 F9h D26.7 FAh D27.7 FBh D28.7 FCh D29.7 FDh D30.7 FEh D31.7 FFh abcdei fghj Output Current rd- Current rd+ 100111 0001 011000 1110 011101 0001 100010 1110 101101 0001 010010 1110 110001 1110 110001 0001 110101 0001 001010 1110 101001 1110 101001 0001 011001 1110 011001 0001 111000 1110 000111 0001 111001 0001 000110 1110 100101 1110 100101 0001 010101 1110 010101 0001 110100 1110 110100 1000 001101 1110 001101 0001 101100 1110 101100 1000 011100 1110 011100 1000 010111 0001 101000 1110 011011 0001 100100 1110 100011 0111 100011 0001 010011 0111 010011 0001 110010 1110 110010 0001 001011 0111 001011 0001 101010 1110 101010 0001 011010 1110 011010 0001 111010 0001 000101 1110 110011 0001 001100 1110 100110 1110 100110 0001 010110 1110 010110 0001 110110 0001 001001 1110 001110 1110 001110 0001 101110 0001 010001 1110 011110 0001 100001 1110 101011 0001 010100 1110 (concluded) 9.2.2.5.2 Control Characters Serial ATA Revision 3.0 Gold Revision page 344 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Table 59 – Valid Control Characters Name K28.3 K28.5 Byte 7Ch BCh abcdei fghj Output Current rd- Current rd+ 001111 0011 110000 1100 001111 1010 110000 0101 Description Occurs only at Byte 0 of all primitives except for ALIGNP Occurs only at Byte 0 of ALIGNP In Serial ATA only the K28.3 and K28.5 control characters are valid and are always used as the first byte in a four-byte primitive. The K28.3 control character is used to prefix all primitives other than ALIGNP, while the K28.5 control character is used to prefix ALIGNP. The encoding of characters within primitives follow the same rules as that applied to non-primitives, when calculating the running disparity between characters and between subblocks of each character within the primitive. The control characters K28.3 and K28.5 invert the current running disparity. ALIGNP primitives are of neutral disparity, that is the running disparity at the end of ALIGNP is the same as the running disparity at the beginning of ALIGNP. 9.2.3 Transmission Summary 9.2.3.1 Transmission Order 9.2.3.1.1 Bits Within a Byte The bits within an encoded character are labeled a,b,c,d,e,i,f,g,h,j. Bit “a” shall be transmitted first, followed in order by “b”, “c”, “d”, “e”, “i”, “f”, “g”, “h” and “j”. Note that bit “i” is transmitted between bits “e” and “f”, and that bit “j” is transmitted last, and not in the order that would be indicated by the letters of the alphabet. 9.2.3.1.2 Bytes Within a Dword For all transmissions and receptions, Serial ATA organizes all values as Dwords. Even when representing a 32-bit value, the Dword shall be considered a set of four bytes. The transmission order of the bytes within the Dword shall be from the least-significant byte (byte 0) to the mostsignificant byte (byte 3). This right-to-left transmission order differs from Fibre Channel. Figure 191 illustrates how the bytes are arranged in a Dword and the order in which bits are sent. Serial ATA Revision 3.0 Gold Revision page 345 of 663 31 • • • 24 23 8b Dword Input • • • 16 15 ••• 876543210 8b to 10b conversion First a a a a bit b b b b sent c c c c d d d d e e e e Bits i i i i shifted f f f f g g g g h h h h j j j j Four 10b Encoded Characters Figure 191 – Bit Ordering and Significance 9.2.3.1.3 Dwords Within a Frame A frame (as described in section 10.2.1) shall be transmitted sequentially in ascending Dword order starting with the SOFP delimiter, followed by the Dwords of the frame contents, followed by the CRC, and ending with the EOFP delimiter. NOTE While this specification discusses a strict hierarchy of Dword transmission as an ordered series of bytes, it is not the intent to restrict implementations from implementing a wider data path. It is possible, and even desirable, to perform transmission in word-sized fields. 8b/10b encoders with a 16(unencoded)/20(encoded) data path do exist. The only restriction is the transmission order of each byte and running disparity for each sub-block shall be preserved. 9.2.4 Reception Summary Upon reception of an encoded character the column corresponding to the receiver’s current Running Disparity shall be searched for the encoded character value. If the encoded character value is found in the table the received encoded character shall be considered a legal character and decoded, and the decoded character value is made available to the Link layer. If the received encoded character is not found in that column, then the encoded character shall be marked as code violation and reported to the Link layer. 9.2.4.1 Disparity and the Detection of a Code Violation Due to the propagation characteristics of the 8b/10b code, it is possible that although most errors are detected, a single bit error might not be detected until several characters after the error occurred. The following examples illustrate this effect. The first example shows a bit error being propagated two characters before being detected. The second shows a single character of propagation. Serial ATA Revision 3.0 Gold Revision page 346 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization It is important to note that Serial ATA sends data in Dword increments, but the transmitter and receiver operate in units of a byte (character). The examples don’t show Dword boundaries, so it is possible that an error in either of these cases could be deferred one full Dword. The frequency of disparity errors and code violations is an indicator of channel quality and corresponds directly to the bit error rate of the physical serial link between a host and device. Implementations may elect to count such events and make them available to external firmware or software. Initial Running Disparity and the Running Disparity for each character is shown. In order to discover the errors note that Running Disparity is actually computed at the end of each sub-block and subsequently forwarded to the next sub-block. Footnotes indicate where the disparity error is detected. The error bit is underlined. Table 60 – Single Bit Error with Two Character Delay rd Character rd Character rd Character rd Transmitted character stream. - D21.1 - D10.2 - D23.5 + Transmitted bit stream. - 101010 1001 - 010101 0101 - 111010 1010 + Received bit stream. - 101010 1011a + 010101 0101 + 111010b 1010 + Decoded character stream. - D21.0 + D10.2 + Code violationb +c NOTES: a Bit error introduced: 1001b => 1011b b Sub-blocks with non-neutral disparity alternate polarity (i.e., + => -). In this case, rd does not alternate (it stays positive for two sub-blocks in a row). The resulting encoded character does not exist in the rd+ column in the data or control code table, and so an invalid encoded character is recognized. c Running disparity shall be computed on the received character regardless of the validity of the encoded character. Table 61 – Single Bit Error with One Character Delay rd Character rd Character rd Character rd Transmitted character stream - D21.1 - D23.4 - D23.5 + Transmitted bit stream Received bit stream - 101010 1001 - 111010 0010 - 111010 1010 + - 101010 1011a + 111010b 0010 - 111010 1010 + Decoded character stream - D21.0 + Code violationb - D23.5 +c NOTES: a Bit error introduced: 1001b => 1011b b Sub-blocks with non-neutral disparity alternate polarity (i.e., + => -). In this case, rd does not alternate (it stays positive for two sub-blocks in a row). The resulting encoded character does not exist in the rd+ column in the data or control code table, and so an invalid encoded character is recognized. c Running disparity shall be computed on the received character regardless of the validity of the encoded character. Serial ATA Revision 3.0 Gold Revision page 347 of 663 9.3 Transmission Overview The information on the serial line is a sequence of 8b/10b encoded characters. The smallest unit of communication is a Dword. The contents of each Dword are grouped to provide low-level control information or to transfer information between a host and an attached device. The two types of structures are primitives and frames. A primitive consists of a single Dword and is the simplest unit of information that may be exchanged between a host and a device. When the bytes of a primitive are encoded the resulting pattern is difficult to misinterpret as any other primitive or random pattern. Primitives are used primarily to convey real-time state information, to control the transfer of information and coordinate host / device communication. All bytes in a primitive are constants and the first byte is always a special character. Since all of the bytes are constants, a primitive cannot be used to convey variable information. Later sections describe the exact contents of the primitives used by Serial ATA. A frame consists of multiple Dwords, and always starts with SOFP, followed by a user payload called a Frame Information Structure (FIS), a CRC, and ends with EOFP. The CRC is defined to be the last non-primitive Dword immediately preceding EOFP. Some number of flow control primitives (HOLDP or HOLDAP, or a CONTP stream to sustain a HOLDP or HOLDAP state) are allowed between the SOFP and EOFP primitives to throttle data flow for speed matching purposes. Figure 192 shows an example of a sequence of transmissions. Primitive A Primitive B Frame X Primitive C Frame Y Primitive D SOF Primitive FIS Contents HOLDP Primitive FIS Contents (continued) HOLDAP Primitive CRC EOFP Primitive Figure 192 – Transmission Structures 9.4 Primitives 9.4.1 Overview Primitives are Dword entities that are used to control and provide status of the serial line. Primitives always begin with a control character; all primitives use the K28.3 control character to signify the beginning of a primitive except for ALIGNP which begins with the K28.5 control character. ALIGNP thus represents the only primitive that contains the comma character. Following the control character, three additional characters are encoded to complete the Dword. Table 62 is a summary of the character combinations that make up each primitive. Serial ATA Revision 3.0 Gold Revision page 348 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 9.4.1.1 Primitive Disparity Primitives may begin with either positive or negative disparity and end in either positive or negative disparity. Normal 8b/10b encoding disparity rules are applied when encoding primitives. ALIGNP is chosen to have neutral disparity so that it may be inserted into the stream without affecting the disparity of previously encoded characters. Disparity at the end of ALIGNP is the same as the ending disparity of the last character transmitted before ALIGNP. Each primitive is described and the encoding defined in the following sections. 9.4.1.2 Primitive Handshakes Some primitives are transmitted in response to receipt of other primitives to acknowledge receipt. For example, HOLDAP is transmitted in response to the receipt of HOLDP primitives and R_OKP or R_ERRP is transmitted in response to WTRMP. Due to the different clock domains between to two ends of the cable, the number of response primitives may not match the number of primitives to which they are responding. For example, a device may send five HOLDP primitives but receive six HOLDAP primitives in response. Neither the transmitter nor receiver of these primitives need count the number of primitives or match the number sent and received. There are boundary cases where a zero number of response primitives such as HOLDAP may be sent. 9.4.2 Primitive Descriptions The following table contains the primitive mnemonics and a brief description of each. Table 62 – Description of Primitives Primitive Name ALIGNP Phy layer control. CONTP Continue repeating previous primitive. DMATP DMA terminate. EOFP HOLDP HOLDAP PMACKP PMNAKP End of frame. Hold data transmission. Hold acknowledge. Power management acknowledge. Power management denial. Description Upon receipt of an ALIGNP, the Phy layer re-adjusts internal operations as necessary to perform its functions correctly. This primitive is always sent in pairs - there is no condition where an odd number of ALIGNP primitives shall be sent (except as noted for retimed loopback). CONTP allows long strings of repeated primitives to be eliminated. CONTP implies that the previously received primitive be repeated as long as another primitive is not received. This primitive is sent as a request to the transmitter to terminate a DMA data transmission early by computing a CRC on the data sent and ending with EOFP. The transmitter context is assumed to remain stable after EOFP has been sent. EOFP marks the end of a frame. The previous non-primitive Dword is the CRC for the frame. HOLDP is transmitted in place of payload data within a frame when the transmitter does not have the next payload data ready for transmission. HOLDP is also transmitted by the receiver when a receiver is not ready to receive additional payload data. This primitive is sent while HOLDP is received. Sent in response to a PMREQ_SP or PMREQ_PP when a receiving node is prepared to enter a power mode state. Sent in response to a PMREQ_SP or PMREQ_PP when a receiving node is not prepared to enter a power mode state or when power management is not supported. Serial ATA Revision 3.0 Gold Revision page 349 of 663 Primitive PMREQ_PP PMREQ_SP R_ERRP R_IPP R_OKP R_RDYP SOFP SYNCP WTRMP X_RDYP Name Power management request to Partial. Power management request to Slumber Reception error. Reception in Progress. Reception with no error. Receiver ready. Start of frame. Synchronization Wait for frame termination Transmission data ready. Description This primitive is sent continuously until PMACKP or PMNAKP is received. When PMACKP is received, the current node (host or device) stops transmitting PMREQ_PP and enters the Partial power management state. This primitive is sent continuously until PMACKP or PMNAKP is received. When PMACKP is received, the current node (host or device) stops transmitting PMREQ_SP and enters the Slumber power management state. Current node (host or device) detected error in received payload. Current node (host or device) is receiving payload. Current node (host or device) detected no error in received payload. Current node (host or device) is ready to receive payload. Start of a frame. Payload and CRC follow until EOFP. Synchronizing primitive. After transmission of an EOFP, the transmitter sends WTRMP while waiting for reception status from receiver. Current node (host or device) has payload ready for transmission. 9.4.3 Primitive Encoding The following table defines the encoding for each primitive. Table 63 – Primitive Encoding Primitive Name ALIGNP CONTP DMATP EOFP HOLDP HOLDAP PMACKP PMNAKP PMREQ_PP PMREQ_SP R_ERRP R_IPP R_OKP R_RDYP SOFP SYNCP WTRMP X_RDYP Byte 3 Contents D27.3 D25.4 D22.1 D21.6 D21.6 D21.4 D21.4 D21.7 D23.0 D21.3 D22.2 D21.2 D21.1 D10.2 D23.1 D21.5 D24.2 D23.2 Byte 2 Contents D10.2 D25.4 D22.1 D21.6 D21.6 D21.4 D21.4 D21.7 D23.0 D21.3 D22.2 D21.2 D21.1 D10.2 D23.1 D21.5 D24.2 D23.2 Byte 1 Contents D10.2. D10.5 D21.5 D21.5 D10.5 D10.5 D21.4 D21.4 D21.5 D21.4 D21.5 D21.5 D21.5 D21.4 D21.5 D21.4 D21.5 D21.5 Byte 0 Contents K28.5 K28.3 K28.3 K28.3 K28.3 K28.3 K28.3 K28.3 K28.3 K28.3 K28.3 K28.3 K28.3 K28.3 K28.3 K28.3 K28.3 K28.3 Serial ATA Revision 3.0 Gold Revision page 350 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 9.4.4 DMATP Primitive No consistent use of the DMATP facility is defined, and its use may impact software compatibility. Implementations should tolerate reception of DMATP as defined in this specification but should avoid transmission of DMATP in order to minimize potential interaction problems. One valid response to reception of DMATP is to treat the DMATP as R_IPP and complete the transfer. For example, in the case of a DMA read from device, a Serial ATA device may terminate the transfer with an EOFP, and send a Register Device to Host FIS to the host, with Error and Status registers updated appropriately. In the case of a DMA write to device, the device sends a DMA Activate FIS to the host, and then after receiving an SOFP, has to accept all data until receiving an EOFP from the host. Since the device cannot terminate such a transfer once started, a special abort primitive is used. The DMA Terminate (DMATP) primitive may be sent on the back channel during reception of a Data FIS to signal the transmitter to terminate the transfer in progress. It may be used for both host to device transfers and for device to host transfers. Reception of the DMATP signal shall cause the recipient to close the current frame by inserting the CRC and EOFP, and return to the idle state. For host to device data transfers, upon receiving the DMATP signal the host shall terminate the transfer in progress by deactivating its DMA engine and closing the frame with valid CRC and EOFP. The host DMA engine shall preserve its state at the point it was deactivated so that the device may resume the transmission at a later time by transmitting another DMA Activate FIS to re-activate the DMA engine. The device is responsible for either subsequently resuming the terminated transfer by transmitting another DMA Activate FIS or closing the affected command with appropriate status. For device to host transfers, receipt of DMATP signal by the device results in permanent termination of the transfer and is not resumable. The device shall terminate the transmission in progress and close the frame with a valid CRC and EOFP, and shall thereafter clean up the affected command by indicating appropriate status for that command. No facility for resuming a device to host transfer terminated with the DMATP signal is provided. Some implementations may have an implementation-dependent latency associated with closing the affected Data FIS in response to the DMATP signal. For example, a host controller may have a small transmit FIFO, and in order for the DMA engine to accurately reflect a resumable state, the data already transferred by the DMA engine to the transmit FIFO may have to be transmitted prior to closing the affected Data FIS. Conservative designs should minimize the DMATP response latency while being tolerant of other devices having a long latency. 9.4.5 CONTP Primitive In order to accommodate EMI reductions, scrambling of data is incorporated in Serial ATA as described in section 9.5. The scrambling of data is simple, with a linear feedback shift register (LFSR) used in generating the scrambling pattern being reset at each SOFP. However, the scrambling of primitives is not as effective or simple because of the small number of control characters available. In order to accommodate EMI reductions, repeated primitives are suppressed through the use of CONTP. Any repetitive primitive may be implied to continue repeating through the use of CONTP. The recipient of CONTP shall ignore all data received after CONTP until the reception of any primitive, excluding ALIGNP. After transmitting CONTP, the transmitter may send any sequence of data characters to the recipient provided that no primitives are included. The reception of CONTP shall cause the last valid primitive to be implied as repeated until the reception of the next valid primitive. Serial ATA Revision 3.0 Gold Revision page 351 of 663 To improve overall protocol robustness and avoid potential timeout situations caused by a reception error in a primitive, all repeated primitives shall be transmitted a minimum of twice before CONTP is transmitted. The first primitive correctly received is the initiator of any action within the receiver. This avoids scenarios, for example, where X_RDYP is sent from the host, followed by a CONTP, and the X_RDYP is received improperly resulting in the device not returning an R_RDYP and causing the system to deadlock until a timeout/reset condition occurs. The transmission of CONTP is optional, but the ability to receive and properly process CONTP is required. The insertion of a single, or two repetitive primitives not followed by CONTP is valid (i.e. data, data, HOLDP, data). The following primitives may be followed by a CONTP: HOLDP, HOLDAP, PMREQ_PP, PMREQ_SP, R_ERRP, R_IPP, R_OKP, R_RDYP, SYNCP, WTRMP and X_RDYP. The host Phy initialization state machine consumes the first few received primitives before communications between the host and device have been established (see state HP7:HR_SendAlign in section 8.4.1). In order to ensure proper synchronization between the host and device after entry into the L1:L_IDLE state from the LS3:L_SendAlign state or the LPM8:L_WakeUp2 state (see section 9.6.2 and section 9.6.5), the use of CONTP is not allowed after a transition from the LS3:L_SendAlign state or the LPM8:L_WakeUp2 state to the L1:L_IDLE state until either a minimum of 10 non-ALIGNP primitives have been transmitted or until receipt of a primitive other than SYNCP or ALIGNP has been detected. Table 64 illustrates use of CONTP in the transmission of a FIS. Table 64 – CONTP Usage Example Transmitter XXXX XXXX X_RDYP X_RDYP CONTP XXXX XXXX XXXX XXXX SOFP DATA (FIS Type) DATA DATA DATA DATA HOLDP HOLDP CONTP XXXX XXXX XXXX Receiver XXXX XXXX XXXX XXXX XXXX XXXX R_RDYP R_RDYP CONTP XXXX XXXX XXXX R_IPP R_IPP CONTP XXXX XXXX XXXX XXXX HOLDAP HOLDAP Serial ATA Revision 3.0 Gold Revision page 352 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transmitter Receiver HOLDP DATA CONTP XXXX DATA XXXX DATA XXXX CRC XXXX EOFP WTRMP WTRMP WTRMP CONTP XXXX XXXX XXXX XXXX R_IPP R_IPP CONTP XXXX XXXX R_OKP R_OKP CONTP XXXX SYNCP SYNCP CONTP XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX SYNCP SYNCP CONTP XXXX XXXX XXXX NOTES: XXXX Scrambled data values (non-primitives) DATA FIS payload data. 9.4.5.1 Scrambling of Data Following the CONTP Primitive The data following the CONTP shall be the output of an LFSR which implements the same polynomial as is used to scramble FIS contents. That polynomial is defined in section 9.5. The resulting LFSR value shall be encoded using the 8b/10b rules for encoding data characters before transmission by the Link layer. The LFSR used to supply data after CONTP shall be reset to the initial value upon detection of a COMINIT or COMRESET event. Since the data following CONTP is discarded by the Link layer, the value of the LFSR is undefined between CONTP primitives. That is, the LFSR result used for CONTP sequence N is not required to be continuous from the last LFSR result of CONTP sequence N-1. The sequence of LFSR values used to scramble the payload contents of a FIS shall not be affected by the scrambling of data used during repeated primitive suppression. That is, the data payload LFSR shall not be advanced during repeated primitive suppression and shall only be advanced for each data payload character that is scrambled using the data payload LFSR. See section 7.5 for additional information on scrambling and repeated primitive suppression. Serial ATA Revision 3.0 Gold Revision page 353 of 663 9.4.5.2 Periodic Retransmission of Sustained Primitives (Informative) In order to be able to determine the state that a bus is in, it is recommended that a sustained primitive periodically be retransmitted. The only requirement is that the interval at which the retransmit occurs is large enough that EMI is not substantially affected. Since the ALIGN sequence is required to be sent at an interval of at most 256 Dwords, one solution to providing visibility to a suppressed primitive stream is to retransmit the suppressed primitive sequence immediately after the ALIGNP primitives are inserted. For example, if the original sequence was PRIM / PRIM / CONTP / junk. . . ALIGNP / ALIGNP / junk. . . the new sequence could look like: PRIM / PRIM / CONTP / junk . . . ALIGNP / ALIGNP / PRIM / PRIM / CONTP / junk. The actual interval chosen by an implementation could be longer. The goal is to make visible the primitive stream being sustained within the normal depth of a logic analyzer. 9.4.6 ALIGNP Primitive The Link layer shall ignore reception of ALIGNP primitives. The Phy layer is free to consume received ALIGNP primitives. Implementations where the Phy does not consume received ALIGNP primitives shall effectively drop received ALIGNP primitives at the input to the Link layer or shall include Link layer processing that yields behavior equivalent to the behavior produced if all received ALIGNP primitives are consumed by the Phy and not presented to the Link. 9.4.7 Flow Control Signaling Latency There is a finite pipeline latency in a round-trip handshake across the Serial ATA interface. In order to avoid buffer overflow in flow control situations, the maximum tolerable latency from when a receiver issues a HOLDP signal until it receives the HOLDAP signal from the transmitter is specified. This allows the high-water mark to be set in the receive FIFO so as to avoid buffer overflow while avoiding excessive buffering/FIFO space. In the case where the receiver wants to flow control the incoming data, it transmits HOLDP characters on the back channel. Some number of received Dwords later, valid data ceases, and HOLDAP characters are received. The larger the latency between transmitting HOLDP until receiving HOLDAP, the larger the receive FIFO needs to be. Within a single HOLDP/ HOLDAP sequence, the maximum allowed latency from the time the MSB of the initial HOLDP is on the wire, until the MSB of the initial HOLDAP is on the wire shall be no more than 20 Dword times. The LSB is transmitted first. A receiver shall be able to accommodate reception of 20 Dwords of additional data after the time it transmits the HOLDP flow control character to the transmitter, and the transmitter shall respond with a HOLDAP in response to receiving a HOLDP within 20 Dword times. The 20 Dword latency specification is not applicable to any subsequent transmissions of the HOLDP flow control character within the same sequence. Upon each new instantiation of a HOLDP/ HOLDAP sequence, the receiver and transmitter shall meet the 20 Dword latency specification. There is no reference design in this specification. The specified maximum latency figure is based on the layers and states described throughout this document. It is recognized that the Link layer may have two separate clock domains -- transmit clock domain, and the receive clock domain. It is also recognized that a Link state machine could run at the Dword clock rate, implying synchronizers between three potential clock domains. In practice more efficient implementations would be pursued and the actual latencies may be less than indicated here. The figures represent an almost literal interpretation of the spec into logic design. A synchronizer is assumed to be a worst case of 2.99 clocks of any clock domain and is rounded to three whole clocks. The Serial ATA cable contains less than half of a Dword of content at Gen1i and Gen2i speeds with 1m internal cables, and is therefore negligible. For longer cable lengths, the effect of the cable should not be ignored. Two Dwords of pipeline delay are assumed for the Phy, and the FIFO is assumed to run at the Link state machine rate. No synchronization is needed between the two. Serial ATA Revision 3.0 Gold Revision page 354 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization The following figure outlines the origin of the 20 Dword latency specification. The example illustrates the components of a round trip delay when the receiver transmits HOLDP on the link until reception of the HOLDAP from the transmitter. This corresponds to the number of Dwords that the receiver shall be able to accept after transmitting a HOLDP. Table 65 – Example of Components of a Round Trip Delay 1 Dword Receiver Sends HOLDP Convert to 40 bit data. 1 Dword 10b/8b conversion. 1 Dword De-scrambling. 3 Dwords Synchronization between receive clock, and Link state machine clock. 1 Dword Link state machine is notified that primitive has been received. 1 Dword Link state machine takes action. 1 Dword FIFO is notified of primitive reception. 1 Dword FIFO stops sending data to Link layer. 1 Dword 1 Dword 1 Dword Link is notified to insert HOLDAP. Link acts on notification and inserts HOLDAP into data stream. Scrambling. 1 Dword 8b/10b conversion. 1 Dword Synchronize to transmit clock (3 transmit clocks, which are four times the Link state machine rate) 1 Dword Convert to 10 bit data 2 Dwords Phy, transmit side HOLDAP on the Cable 9.4.7.1 Cable Length and Flow Control Latency (Informative) For hosts and devices which are designed for use in data center applications in which cables longer than 1 meter are used, it is advised that these designs accommodate potential increased effects on overflow latencies. When operating at 3.0 Gbps with a 1 meter cable, the cable contains less than half a Dword of content at any point in time and thus the latency effect from the cable is ignored in flow control calculations. However, when operating at 3.0 Gbps with an 8 meter cable as an example, the cable contains almost 3 Dwords of content. When cables longer than 1 meter are used, the effect of the cable on flow control latency should be accounted for in the system design. A system design may account for these effects in a multitude of ways. Some examples include: • Hosts and/or devices may be selected that meet more stringent flow control requirements. • Hosts and/or devices may be selected that have a larger flow control buffer and absorb more than 20 Dwords of latency. • Do not select excessive cables lengths over what is required for the environment as it impacts flow control latencies. Serial ATA Revision 3.0 Gold Revision page 355 of 663 9.4.8 Examples of Primitive Usage (Informative) Table 66, Table 67, and Table 68 are examples that illustrate basic primitive usage. They do not show detailed lengthy sequences which invoke the use of CONTP. Table 66 – SRST Write from Host to Device Transmission Breaking Through a Device to Host Data FIS Host … R_IPP R_IPP R_IPP R_IPP HOLDAP HOLDAP … HOLDAP SYNCP SYNCP SYNCP SYNCP X_RDYP X_RDYP X_RDYP X_RDYP SOFP etc Device … DATA n DATA n+1 HOLDP HOLDP HOLDP HOLDP … HOLDP HOLDP HOLDP SYNCP SYNCP SYNCP SYNCP R_RDYP R_RDYP R_RDYP etc Description Previous activity abbreviated for clarity. Device transmitting data. Device transmit FIFO empty, and flow control applied. Host receives and decodes HOLDP flow control. Host acknowledges flow control. Device internally deadlocked and no more data forthcoming (device hung) . System in this state until host decides to reset device. Host detects SRST write to Device Control register, needs to break deadlock. Host transmits SYNCP to abort current transmission. Device receives and decodes SYNCP, abandons transmission in progress. Host sends SYNCP / Device sends SYNCP (both returned to idle state) Host receives and decodes SYNCP, may now initiate new FIS transmission Host ready to send Shadow register block registers for SRST write Device decodes X_RDYP Device indicates ready to receive Host decodes R_RDYP Host starts a frame etc Table 67 – Command Shadow Register Block Register Transmission Example Host SYNCP SYNCP X_RDYP X_RDYP X_RDYP X_RDYP SOFP DATA 0 DATA 1 Device SYNCP SYNCP SYNCP SYNCP R_RDYP R_RDYP R_RDYP R_RDYP R_IPP Description Idle condition. Idle condition. Host ready to send Shadow register block registers. Device decodes X_RDYPc. Device indicates ready to receive. Host decodes R_RDYP. Host starts a frame. Host sends Register FIS Dword 0 / device decodes SOFP. Host sends Register FIS Dword 1 / device stores DATA Dword 0. Serial ATA Revision 3.0 Gold Revision page 356 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Host Device Description … … … DATA n CRC EOFP WTRMP WTRMP WTRMP WTRMP SYNCP SYNCP SYNCP R_IPP R_IPP R_IPP R_IPP R_IPP R_OKP R_OKP R_OKP R_OKP SYNCP Host sends Register FIS Dword n / device stores DATA Dword n-1. Host sends CRC / device stores DATA Dword n. Host sends EOFP / device stores CRC. Device decodes EOFP. Device computes good CRC and releases TF contents. Device sends good end. Host decodes R_OKP as good results. Host releases interface. Device decodes release by host - is allowed to release. Idle condition. Table 68 – Data from Host to Device Transmission Example Host SYNCP SYNCP X_RDYP X_RDYP X_RDYP X_RDYP SOFP DATA 0 DATA 1 ... DATA x HOLDP HOLDP HOLDP DATA(n-2) DATA(n-1) DATA(n) CRC EOFP WTRMP WTRMP WTRMP WTRMP SYNCP SYNCP SYNCP Device SYNCP SYNCP SYNCP SYNCP R_RDYP R_RDYP R_RDYP R_RDYP R_IPP .. R_IPP R_IPP HOLDAP HOLDAP HOLDAP R_IPP R_IPP R_IPP R_IPP R_IPP R_IPP R_OKP R_OKP R_OKP R_OKP SYNCP Description Idle condition. Idle condition. Host ready to send Shadow register block registers. Device decodes X_RDYP. Device indicates ready to receive. Host decodes R_RDYP. Host starts a frame. Host sends DATA Dword 0 / device decodes SOFP. Host sends DATA Dword 1 / device stores DATA Dword 0. ... Host sends DATA Dword x / device stores DATA Dword (x-1) . Host sends HOLD / device stores DATA Dword (x) and decodes HOLDP. Device acknowledges HOLDP. Host decodes HOLDAP – host may release HOLDP at any time. Host sends (n-2)th DATA Dword / device decodes DATA Dword. Host sends (n-1)th data Dword / device stores (n-2)th DATA Dword. Host sends nth data Dword / device stores (n-1)th DATA Dword. Host sends CRC / device stores nth DATA Dword. Host sends EOFP / device stores CRC. Device decodes EOFP. Device computes good CRC and releases data contents. Device sends good end. Host decodes R_OKP as good results. Host releases interface. Device decodes release by host - is allowed to release. Idle condition. Serial ATA Revision 3.0 Gold Revision page 357 of 663 9.5 CRC and Scrambling The CRC (Cyclic Redundancy Check) of a frame is a Dword (32-bit) field that shall follow the last Dword of the contents of a FIS and precede EOFP. The CRC calculation covers all of the FIS transport data between the SOFP and EOFP primitives, and excludes any intervening primitives and CONTP stream contents. The CRC value shall be computed on the contents of the FIS before encoding for transmission (scrambling) and after decoding upon reception. The CRC shall be calculated on Dword quantities. If a FIS contains an odd number of words the last word of the FIS shall be padded with zeros to a full Dword before the Dword is used in the calculation of the CRC. The CRC shall be aligned on a Dword boundary. The CRC shall be calculated using the following 32-bit generator polynomial: G(X) = X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 +X2 +X + 1 The CRC value shall be initialized with a value of 52325032h before the calculation begins. The maximum number of Dwords between SOFP to EOFP shall not exceed 2064 Dwords including the FIS type and CRC.. The contents of a frame shall be scrambled before transmission by the Phy layer. Scrambling shall be performed on Dword quantities by XORing the data to be transmitted with the output of a linear feedback shift register (LFSR). The shift register shall implement the following polynomial: G(X) = X16 + X15 + X13 + X4 + 1 The serial shift register shall be initialized with the seed value of FFFFh before the first shift of the LFSR. The shift register shall be initialized to the seed value before SOFP is transmitted. All data words between the SOFP and EOFP shall be scrambled, including the CRC. 9.5.1 Relationship Between Scrambling of FIS Data and Repeated Primitives There are two separate scramblers used in Serial ATA. One scrambler is used for the data payload encoding and a separate scrambler is used for repeated primitive suppression. The scrambler used for data payload encoding shall maintain consistent and contiguous context over the scrambled payload characters of a frame (between SOFP and EOFP), and shall not have its context affected by the scrambling of data used for repeated primitive suppression. Scrambling is applied to all data (non-primitive) Dwords. Primitives, including ALIGNP, do not get scrambled and shall not advance the data payload LFSR register. Similarly, the data payload LFSR shall not be advanced during transmission of Dwords during repeated primitive suppression (i.e. after a CONTP primitive). Since it is possible for a repeated primitive stream to occur in the middle of a data frame – multiple HOLDP/HOLDAP primitives are likely – care should be taken to insure that the data payload LFSR is only advanced for each data payload character that it scrambles and that it is not advanced for primitives or for data characters transmitted as part of repeated primitive suppression which uses a separate scrambler. 9.5.2 Relationship Between Scrambling and CRC The order of application of scrambling shall be as follows. For a Dword of data following SOFP the Dword shall be used in the calculation of the CRC. The same Dword value shall be XORed Serial ATA Revision 3.0 Gold Revision page 358 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization with the scrambler output, and the resulting Dword submitted to the 8b/10b encoder for transmission. Similarly, on reception, the Dword shall be decoded using a 10b/8b decoder, the scrambler output shall be XORed with the resulting Dword, and the resulting Dword presented to the Link layer and subsequently used in calculating the CRC. The CRC Dword shall be scrambled according to the same rules. 9.5.3 Scrambling Disable (Informative) Hosts and devices should provide a vendor-specific means of disabling the transmission/reception of scrambled data. Three independent controls are recommended – one to disable the scrambling of transmitted FIS payload data, the second to disable the CONTP/junk method of repeated primitive suppression, and the third to disable the unscrambling of received FIS payload data. Using the scrambling disable capabilities is intended for testability and design debug, and not recommended as an end-user feature. It is the responsibility of the engineer/operator to ensure that both ends of the cable are configured in such a way that the host and device may communicate (i.e. if scrambled transmission is disabled on the device then scrambled reception shall be disabled on the host). Devices that disable payload scrambling may not interoperate with other devices that do not implement this recommendation. Systems that disable scrambling may not meet EMI regulatory requirements. 9.6 Link Layer State Machine 9.6.1 Terms Used in Link Layer Transition Tables 1. LRESET: Link layer COMRESET or COMINIT signal 2. PHYRDYn: The negation of the PHYRDY signal. 3. PHYRDY: Phy status as defined in section 7.1.2. 4. DecErr: Bad decode of a 32 bit Dword transferred from Phy to Link • Invalid 10b pattern • Disparity error • Primitive with a control character in the first byte but not an allowed control character • Any control character in other than the first byte of the Dword 5. DatDword: A 32 bit pattern that is formed correctly, but does not have the primitive leading 10b pattern (K28.5 or K28.3). 6. COMWAKE: Signal from the OOB detector in the Phy indicating that the COMWAKE OOB signal is being detected. 7. AnyDword: A 32 bit pattern of any type - even one with DecErr received from Phy Serial ATA Revision 3.0 Gold Revision page 359 of 663 9.6.2 Link Idle State Diagram Table 69 – State Diagram Link Idle L1: L_IDLE4 Transmit SYNCP. 1. Transport layer requests frame transmission and PHYRDY2. HL_SendChkRdy or DL_SendChkRdy1 2. Transport layer requests transition to Partial and PHYRDY2,5. L_TPMPartial 3. Transport layer requests transition to Slumber and PHYRDY2,5. L_TPMSlumber 4. X_RDYP received from Phy. 5. Phy layer forwards ( PMREQ_PP or PMREQ_SP ) and power modes are enabled and acceptable. 6. Phy layer forwards ( PMREQ_PP or PMREQ_SP ) and power modes are disabled or are unacceptable. 7. Phy layer forwards AnyDword other than (X_RDYP or PMREQ_PP or from Transport PlaMyeRr2E,Q3._SP) and no transmit request L_RcvWaitFifo L_PMOff L_PMDeny L_IDLE 8. PHYRDYn L_NoCommErr NOTES: 1. The host Link layer makes a transition to the HL_SendChkRdy state; the device Link layer makes a transition to the DL_SendChkRdy state. 2. This transition is taken even if errors such as 10b decoding errors are detected. 3. This statement also ignores any unrecognized sequences or commands not defined in this specification. 4. Upon entry to this state from the LS3:L_SendAlign state or the LPM8:L_WakeUp2 state, use of CONTP is not allowed until either a minimum of 10 non-ALIGNP primitives have been transmitted or until receipt of a primitive other than SYNCP or ALIGNP has been detected. 5. Hosts shall not attempt initiating an interface power state transition between an issued reset and the receipt of the device reset signature. Hosts should not attempt initiating an interface power management request without first verifying the device has such capabilities as determined by the information in the device’s IDENTIFY DEVICE (or IDENTIFY PACKET DEVICE) data structure. L2: L_SyncEscape1 Transmit SYNCP. 1. AnyDword other than X_RDYP or SYNCP received from Phy. L_SyncEscape 2. X_RDYP or SYNCP received from Phy. 3. PHYRDYn L_IDLE L_NoCommErr2 NOTES: 1. This state is entered asynchronously from any other Link layer state where the Link layer has transmitted SYNCP to escape a FIS transfer, also known as a SYNC Escape. 2. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. Serial ATA Revision 3.0 Gold Revision page 360 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization LS1: L_NoCommErr 1. Unconditional Post Phy not ready error to Transport layer. L_NoComm LS2: L_NoComm 1. PHYRDYn Transmit ALIGNP1. 2. PHYRDY NOTES: 1. Also deactivate any signal for Phy layer to abort operation. L_NoComm L_SendAlign LS3: L_SendAlign 1. PHYRDYn 2. PHYRDY Transmit ALIGNP. L_NoCommErr L_IDLE LS4: L_RESET1 Reset Link state to initial conditions. 1. LRESET Link reset signal asserted. L_RESET 2. LRESET Link reset signal negated. L_NoComm NOTES: 1. This state is entered asynchronously when the link reset control is active. L1: L_IDLE state: This state is entered when a frame transmission has been completed by the Link layer. When in this state, the Link layer transmits SYNCP and waits for X_RDYP from the Phy layer or a frame transmission request from the Transport layer. Transition L1:1a: When the host Link layer receives a request to transmit a frame from the Transport layer and the Phy layer is ready, the Link layer shall make a transition to the LT1: HL_SendChkRdy state. Transition L1:1b: When the device Link layer receives a request to transmit a frame from the Transport layer and the Phy layer is ready, the Link layer shall make a transition to the LT2: DL_SendChkRdy state. Transition L1:2: When the Link layer receives a request to enter the Partial power mode from the Transport layer and the Phy layer is ready, the Link layer shall make a transition to the L_TPMPartial state. Transition L1:3: When the Link layer receives a request to enter the Slumber power mode from the Transport layer and the Phy layer is ready, the Link layer shall make a transition to the L_TPMSlumber state. Transition L1:4: When the Link layer receives an X_RDYP from the Phy layer, the Link layer shall make a transition to the LR2: L_RcvWaitFifo state. Transition L1:5: When the Link layer receives a PMREQ_PP or PMREQ_SP from the Phy layer,is enabled to perform power management modes, and in a state to accept power mode requests, the Link layer shall make a transition to the LPM3: L_PMOff state. Serial ATA Revision 3.0 Gold Revision page 361 of 663 Transition L1:6: When the Link layer receives a PMREQ_PP or a PMREQ_SP from the Phy layer and is not enabled to perform power management modes or is not in a state to accept power mode requests, the Link layer shall make a transition to the LR0: L_PMDeny state. This transition is still valid if interface power states are supported and enabled as verified by Word 76 bit 9 set to one in IDENTIFY (PACKET) DEVICE data. Transition L1:7: When the Link layer does not receive a request to transmit a frame from the Transport layer, does not receive a request to go to a power mode from the Transport layer, does not receive an X_RDYP from the Phy layer or does not receive a PMREQ_x from the Phy layer the Link layer shall make a transition to the L1: L_IDLE state. Transition L1:8: If the Phy layer becomes not ready even if the Transport layer is requesting an operation, the Link layer transitions to the L_NoCommErr state. L2: L_SyncEscape state: This state is entered when the Link layer transmits SYNCP to escape a FIS transmission. The Link layer may choose to escape a FIS transmission due to a request from the Transport layer or due to an invalid state transition. This state is only entered by the initiator of the SYNC Escape. When in this state, the Link layer transmits SYNCP and waits for a SYNCP from the Phy layer before proceeding to L_IDLE. The Link layer also transitions to L_IDLE if X_RDYP is received in order to avoid a deadlock condition. Transition L2:1: When the Link layer receives any Dword from the Phy that is not X_RDYP or SYNCP, the Link layer shall make a transition to the L2: L_SyncEscape state. Transition L2:2: When the Link layer receives X_RDYP or SYNCP from the Phy, the Link layer shall make a transition to the L1: L_IDLE state. Transition L2:3: When the host Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. LS1: L_NoCommErr state: This state is entered upon detection of a non ready condition of the Phy layer while attempting to process another state. The entry into this state heralds a relatively serious error condition in the Link layer. This state is executed only once so as to pass on the error condition up to the Transport layer. Transition LS1:1: The transition is made to LS1:L_NoComm unconditionally. LS2: L_NoComm state: This state is entered directly from the LS1:L_NoCommErr state or the LS4:L_RESET State. The Link layer remains in this state until the Phy signals that it has established communications and is ready. Transition LS2:1: For as long as the Phy layer stays not ready, the transition is made to LS2: L_NoComm. Transition LS2:2: When the Phy layer signals it is ready, a transition is made to LS3: L_SendAlign. LS3: L_SendAlign state: This state is entered whenever an ALIGNP needs to be sent to the Phy layer. Serial ATA Revision 3.0 Gold Revision page 362 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transition LS3:1: If the Phy layer becomes not ready, then a transition is made to LS1: L_NoCommErr. Transition LS3:2: If the Phy layer indicates that it is ready, a transition is made to the L1: L_IDLE state. LS4: L_RESET state: This state is entered whenever the Link LRESET control is active. All Link layer hardware is initialized to and held at a known state/value. While in this state all requests or triggers from other layers are ignored. While in this state, the Phy reset signal is also asserted. Transition LS4:1: While the RESET control is active a transition is made back to the LS4: L_RESET state. Transition LS4:2: When the RESET control goes inactive a transition is made to the LS2: L_NoComm state. 9.6.3 Link Transmit State Diagram Table 70 – State Diagram Link Transmit LT1: HL_SendChkRdy Transmit X_RDYP. 1. R_RDYP received from Phy. L_SendSOF 2. X_RDYP received from Phy. 3. AnyDword other than (R_RDYP or X_RDYP)1 received from Phy layer. 4. PHYRDYn L_RcvWaitFifo HL_SendChkRdy L_NoCommErr2 NOTES: 1. Any received errors such as 10b decoding errors and invalid primitives are ignored. 2. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. LT2: DL_SendChkRdy Transmit X_RDYP. 1. R_RDYP received from Phy. 2. AnyDword other than R_RDYP received from Phy. 3. PHYRDYn L_SendSOF DL_SendChkRdy L_NoCommErr LT3: L_SendSOF 1. PHYRDY1 Transmit SOFP L_SendData 2. PHYRDYn L_NoCommErr2 3. SYNCP received from Phy. L_IDLE2 NOTES: 1. Any received errors such as 10b decoding errors and invalid primitives are ignored. 2. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. Serial ATA Revision 3.0 Gold Revision page 363 of 663 LT4: L_SendData Transmit data Dword 1. More data to transmit and AnyDword other than (HOLDP or DMATP or SYNCP) received from Phy1,2. L_SendData 2. More data to transmit and HOLDP received from Phy. 3. Data transmit not complete and data not ready to transmit and AnyDword other than SYNCP received from Phy. L_RcvrHold L_SendHold 4. DMATP received from Phy or data transmit complete and AnyDword other than SYNCP received from Phy. 5. SYNCP received from Phy. 6. PHYRDYn L_SendCRC5 L_IDLE3 L_NoCommErr3 7. Transport layer indicates request to escape current frame4. L_SyncEscape NOTES: 1. Any received errors such as 10b decoding errors and invalid primitives are ignored. 2. This makes possible a back channel during this time. 3. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. 4. When this condition is true, the associated transition has priority over all other transitions exiting this state. 5. The DMATP signal is advisory and data transmission should be halted at the earliest opportunity but is not required to cease immediately. It is allowable to stay in the LT4: L_SendData state when there is more data to transmit and DMATP is received. LT5: L_RcvrHold Transmit HOLDAP. 1. More data to transmit and AnyDword other than (HOLDP or SYNCP or DMATP) received from Phy with no DecErr. L_SendData 2. More data to transmit and HOLDP received from Phy or DecErr. 3. More data to transmit and SYNCP received from Phy. 4. More data to transmit and DMATP received from Phy 5. PHYRDYn. L_RcvrHold L_IDLE1 L_SendCRC3 L_NoCommErr1 6. Transport layer indicates request to escape current frame2. L_SyncEscape 7. SYNCP received from Phy. L_IDLE1 NOTES: 1. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. 2. When this condition is true, the associated transition has priority over all other transitions exiting this state. 3. The DMATP signal is advisory and data transmission should be halted at the earliest opportunity but is not required to cease immediately. It is allowable to stay in the LT5: L_RcvrHold state when there is more data to transmit and DMATP is received. Serial ATA Revision 3.0 Gold Revision page 364 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization LT6: L_SendHold Transmit HOLDP. 1. More data ready to transmit and AnyDword other than (HOLDP or SYNCP) received from Phy. 2. More data ready to transmit and HOLDP received from Phy. L_SendData L_RcvrHold 3. Data transmit not complete and data not ready to transmit and AnyDword other than (SYNCP or DMATP) received from Phy. L_SendHold 4. DMATP received from Phy or data transmit complete and AnyDword other than SYNCP received from Phy. 5. SYNCP received from Phy. 6. PHYRDYn L_SendCRC3 L_IDLE1 L_NoCommErr1 7. Transport layer indicates request to escape current frame2. L_SyncEscape NOTES: 1. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. 2. When this condition is true, the associated transition has priority over all other transitions exiting this state. 3. The DMATP signal is advisory and data transmission should be halted at the earliest opportunity but is not required to cease immediately. It is allowable to stay in the LT6: L_SendHold state when there is more data to transmit and DMATP is received. LT7: L_SendCRC Transmit CRC. 1. PHYRDY and SYNCP not received from Phy. 2. PHYRDYn 3. PHYRDY and SYNCP received from Phy. L_SendEOF L_NoCommErr1 L_IDLE1 NOTES: 1. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. LT8: L_SendEOF Transmit EOFP. 1. PHYRDY and SYNCP not received from Phy. 2. PHYRDYn L_Wait L_NoCommErr1 3. PHYRDY and SYNCP received from Phy. L_IDLE1 NOTES: 1. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. Serial ATA Revision 3.0 Gold Revision page 365 of 663 LT9: L_Wait Transmit WTRMP. 1. R_OKP received from Phy. L_IDLE (good status) 2. R_ERRP received from Phy. 3. SYNCP received from Phy. L_IDLE (bad status) L_IDLE1 4. AnyDword other than (R_OKP or R_ERRP or SYNCP) received from Phy. 5. PHYRDYn L_Wait L_NoCommErr1 NOTES: 1. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. LT1: HL_SendChkRdy state: This state is entered when a frame transmission has been requested by the host Transport layer. When in this state, the Link layer transmits X_RDYP and waits for X_RDYP or R_RDYP from the Phy layer. NOTE – It is possible that both the host and the device simultaneously request frame transmission by transmitting X_RDYP. If the host receives X_RDYP while transmitting X_RDYP, the host shall back off and enter the L_RcvWaitFifo state, postponing its desired frame transmission until the device has completed its frame transmission and the bus is idle. Transition LT1:1: When the host Link layer receives R_RDYP from the Phy layer, the Link layer shall make a transition to the LT3: L_SendSOF state. Transition LT1:2: When the host Link layer receives X_RDYP from the Phy layer, the Link layer shall make a transition to the LR2: L_RcvWaitFifo state. Transition LT1:3: When the host Link layer receives any Dword other than R_RDYP or X_RDYP from the Phy layer, the Link layer shall make a transition to the LT1: HL_SendChkRdy state. Transition LT1:4: When the host Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. LT2: DL_SendChkRdy state: This state is entered when a frame transmission has been requested by the device Transport layer. When in this state, the Link layer transmits X_RDYP and waits for R_RDYP from the Phy layer. Transition LT2:1: When the device Link layer receives R_RDYP from the Phy layer, the Link layer shall make a transition to the LT3: L_SendSOF state. Transition LT2:2: When the device Link layer does not receive R_RDYP from the Phy layer, the Link layer shall make a transition to the LT2: DL_SendChkRdy state. Transition LT2:3: When the device Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. Serial ATA Revision 3.0 Gold Revision page 366 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization LT3: L_SendSOF state: This state is entered when R_RDYP has been received from the Phy layer. When in this state, the Link layer transmits SOFP. Transition LT3:1: When the device Link layer has transmitted SOFP, the Link layer shall make a transition to the LT4: L_SendDATA state. Transition LT3:2: When the Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. Transition LT3:3: When the Link layer receives SYNCP from the Phy layer, the Link layer shall notify the Transport layer of the illegal transition error condition and shall make a transition to the L1:L_IDLE state. LT4: L_SendData state: This state is entered when SOFP has been transmitted. When in this state, the Link layer takes a data Dword from the Transport layer, encodes the Dword, and transmits it. The Dword is also entered into the CRC calculation before encoding. Transition LT4:1: When the Link layer receives any Dword other than a HOLDP, DMATP, or SYNCP primitive from the Phy layer and the Transport layer indicates a Dword is available for transfer, the Link layer shall make a transition to the LT4: L_SendData state. The DMATP signal is advisory and data transmission should be halted at the earliest opportunity but is not required to cease immediately. It is therefore allowable to stay in the LT4: L_SendData state when there is more data to transmit and DMATP is received. Transition LT4:2: When the device Link layer receives HOLDP from the Phy layer, the Link layer shall make a transition to the LT5: L_RcvrHold state. Transition LT4:3: When the Transport layer indicates that the next Dword is not available to transfer and any Dword other than SYNCP has been received from the Phy layer, the Link layer shall make a transition to the LT6: L_SendHold state. Transition LT4:4: When the Transport layer indicates that all data for the frame has been transferred and any Dword other than SYNCP has been received from the Phy layer, the Link layer shall make a transition to the LT7: L_SendCRC state. When the Link layer receives DMATP from the Phy layer, it shall notify the Transport layer and terminate the transmission in progress as described in section 9.4.4 and shall transition to the LT7: L_SendCRC state. Transition LT4:5: When the Link layer receives SYNCP from the Phy layer, the Link layer shall notify the Transport layer of the illegal transition error condition and shall make a transition to the L1:L_IDLE state Transition LT4:6: When the Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. Transition LT4:7: When the Link layer receives notification from the Transport layer that the current frame transfer should be escaped, a transition to the L_SyncEscape state shall be made. LT5: L_RcvrHold state: This state is entered when HOLDP has been received from the Phy layer. When in this state, the Link layer shall transmit HOLDAP. Serial ATA Revision 3.0 Gold Revision page 367 of 663 Transition LT5:1: When the Link layer receives any Dword other than a HOLDP, SYNCP, or a DMATP primitive from the Phy layer with no decoding error detected, and the Transport layer indicates that a Dword is available for transfer, the Link layer shall make a transition to the LT4: L_SendData state. Transition LT5:2: When the device Link layer receives HOLDP from the Phy layer or a decoding error was detected, the Link layer shall make a transition to the LT5: L_RcvrHold state. Transition LT5:3: When the Link layer receives SYNCP from the Phy layer, the Link layer shall make a transition to the L1: L_IDLE state. The Transport layer shall be notified of the illegal transition error condition. Transition LT5:4: When the Link layer receives DMATP from the Phy layer, it shall notify the Transport layer and terminate the transmission in progress as described in section 9.4.4 and shall transition to the LT7: L_SendCRC state. Transition LT5:5: When the Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. Transition LT5:6: When the Link layer receives notification from the Transport layer that the current frame should be escaped, a transition to the L_SyncEscape state shall be made. Transition LT5:7: When the Link layer receives SYNCP from the Phy layer, the Link layer shall notify the Transport layer of the illegal transition error condition and shall make a transition to the L1:L_IDLE state. LT6: L_SendHold state: This state is entered when the Transport layer indicates a Dword is not available for transfer and HOLDP has not been received from the Phy layer. When in this state, the Link layer shall transmit HOLDP. Transition LT6:1: When the Link layer receives any Dword other than a HOLDP or SYNCP primitive from the Phy layer and the Transport layer indicates that a Dword is available for transfer, the Link layer shall make a transition to the LT4: L_SendData state. Transition LT6:2: When the Link layer receives HOLDP from the Phy layer and the Transport layer indicates a Dword is available for transfer, the Link layer shall make a transition to the LT5: L_RcvrHold state. Transition LT6:3: When the Transport layer indicates that a Dword is not available for transfer and any Dword other than SYNCP is received from the Phy layer, the Link layer shall make a transition to the LT6: L_SendHold state. Transition LT6:4: When the Transport layer indicates that all data for the frame has been transferred and any Dword other than SYNCP has been received from the Phy layer, the Link layer shall make a transition to the LT7: L_SendCRC state. When the Link layer receives DMATP from the Phy layer, it shall notify the Transport layer and terminate the transmission in progress as described in section 9.4.4 and shall transition to the LT7:L_SendCRC state. Transition LT6:5: When the Link layer receives SYNCP from the Phy layer, the Link layer shall make a transition to the L1: L_IDLE state. The Transport layer shall be notified of the illegal transition error condition. Transition LT6:6: When the Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. Serial ATA Revision 3.0 Gold Revision page 368 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transition LT6:7: When the Link layer receives notification from the Transport layer that the current frame should be escaped, a transition to the L_SyncEscape state shall be made. LT7: L_SendCRC state: This state is entered when the Transport layer indicates that all data Dwords have been transferred for this frame. When in this state, the Link layer shall transmit the calculated CRC for the frame. Transition LT7:1: When the CRC has been transmitted, the Link layer shall make a transition to the LT8: L_SendEOF state. Transition LT7:2: When the Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. Transition LT7:3: When the Link layer receives SYNCP from the Phy layer, the Link layer shall notify the Transport layer of the illegal transition error condition and shall make a transition to the L1:L_IDLE state. LT8: L_SendEOF state: This state is entered when the CRC for the frame has been transmitted. When in this state, the Link layer shall transmit EOFP. Transition LT8:1: When EOFP has been transmitted, the Link layer shall make a transition to the LT9: L_Wait state. Transition LT8:2: When the Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. Transition LT8:3: When the Link layer receives SYNCP from the Phy layer, the Link layer shall notify the Transport layer of the illegal transition error condition and shall make a transition to the L1:L_IDLE state. LT9: L_Wait state: This state is entered when EOFP has been transmitted. When in this state, the Link layer shall transmit WTRMP. Transition LT9:1: When the Link layer receives R_OKP from the Phy layer, the Link layer shall notify the Transport layer and make a transition to the L1: L_IDLE state. Transition LT9:2: When the Link layer receives R_ERRP from the Phy layer, the Link layer shall notify the Transport layer and make a transition to the L1: L_IDLE state. Transition LT9:3: When the Link layer receives SYNCP from the Phy layer, the Link layer shall notify the Transport layer and make a transition to the L1: L_IDLE state. Transition LT9:4: When the Link layer receives any Dword other than an R_OKP, R_ERRP, or SYNCP primitive from the Phy layer, the Link layer shall make a transition to the LT9: L_Wait state. Transition LT9:5: When the Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. Serial ATA Revision 3.0 Gold Revision page 369 of 663 9.6.4 Link Receive State Diagram Table 71 – State Diagram Link Receive LR1: L_RcvChkRdy Transmit R_RDYP. 1. X_RDYP received from Phy. L_RcvChkRdy 2. SOFP received from Phy. L_RcvData 3. Any Dword other than (X_RDYP or SOFP) received from Phy. 4. PHYRDYn L_IDLE L_NoCommErr1 NOTES: 1. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. LR2: L_ RcvWaitFifo Transmit SYNCP. 1. X_RDYP received from Phy and FIFO space available. L_RcvChkRdy 2. X_RDYP received from Phy and FIFO space not available. L_RcvWaitFifo 3. Any Dword other than X_RDYP received from Phy. 4. PHYRDYn L_IDLE L_NoCommErr1 NOTES: 1. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. LR3: L_RcvData Transmit R_IPP or DMATP1. 1. (DatDword received from Phy and FIFO space) or HOLDAP received from Phy. 2. DatDword received from Phy and insufficient FIFO space. L_RcvData L_Hold 3. HOLDP received from Phy. L_RcvHold 4. EOFP received from Phy. L_RcvEOF 5. WTRMP received from Phy. L_BadEnd 6. SYNCP received from Phy. 7. AnyDword other than (HOLDP or EOFP or HOLDAP or SYNCP or WTRMP) received from Phy. 8. PHYRDYn L_IDLE L_RcvData L_NoCommErr2 9. Transport layer indicates request to escape current frame. L_SyncEscape NOTES: 1. If the Transport layer signals that it wishes to terminate the transfer, DMATP is transmitted in place of R_IPP. 2. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. Serial ATA Revision 3.0 Gold Revision page 370 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization LR4: L_Hold Transmit HOLDP. 1. FIFO space available and AnyDword other than HOLDP or EOFP received from Phy. 2. FIFO space available and HOLDP received from Phy. L_RcvData L_RcvHold 3. EOFP received from Phy. 4. No FIFO space available and EOFP not received from Phy and SYNC not received from Phy and PHYRDY P 5. PHYRDYn L_RcvEOF L_Hold L_NoCommErr1 6. SYNCP received from Phy. 7. Transport layer indicates request to escape current frame. L_IDLE L_SyncEscape NOTES: 1. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. LR5: L_RcvHold Transmit HOLDAP or DMATP 1. 1. AnyDword other than (HOLDP or EOFP or SYNCP) received from Phy. L_RcvData 2. HOLDP received from Phy. L_RcvHold 3. EOFP received from Phy. L_RcvEOF 4. SYNCP received from Phy. 5. PHYRDYn L_IDLE L_NoCommErr2 6. Transport layer indicates request to escape current frame. L_SyncEscape NOTES: 1. If the Transport layer signals that it wishes to terminate the transfer, DMATP is transmitted in place of HOLDAP. 2. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. LR6: L_RcvEOF Transmit R_IPP. 1. CRC check not complete. L_RcvEOF 2. CRC good. L_GoodCRC 3. CRC bad. 4. PHYRDYn L_BadEnd L_NoCommErr1 NOTES: 1. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. Serial ATA Revision 3.0 Gold Revision page 371 of 663 LR7: L_GoodCRC Transmit R_IPP. 1. Transport layer indicated good result. L_GoodEnd 2. Transport layer indicates unrecognized FIS. L_BadEnd 3. Transport layer has yet to respond. 4. PHYRDYn L_GoodCRC L_NoCommErr2 5. Transport or Link layer indicated error detected during reception of recognized FIS. L_BadEnd 6. SYNCP received from Phy. L_IDLE NOTES: 1. Upon entering this state for the first time, the Link layer shall notify the Transport layer that the CRC for this frame is valid. 2. The Link layer shall notify the Transport layer of the condition and fail the attempted transfer. LR8: L_GoodEnd Transmit R_OKP. 1. SYNCP received from Phy. 2. AnyDword other than SYNCP received from Phy. 3. PHYRDYn L_IDLE L_GoodEnd L_NoCommErr LR9: L_BadEnd Transmit R_ERRP. 1. SYNCP received from Phy. 2. AnyDword other than SYNCP received from Phy. 3. PHYRDYn L_IDLE L_BadEnd L_NoCommErr LR1: L_RcvChkRdy state: This state is entered when X_RDYP has been received from the Phy layer. When in this state, the Link layer shall transmit R_RDYP and wait for SOFP from the Phy layer. Transition LR1:1: When the Link layer receives X_RDYP from the Phy layer, the Link layer shall make a transition to the LR1: L_RcvChkRdy state. Transition LR1:2: When the Link layer receives SOFP from the Phy layer, the Link layer shall make a transition to the LR3: L_RcvData state. Transition LR1:3: When the Link layer receives any Dword other than an X_RDYP or SOFP primitive from the Phy layer, the Link layer shall notify the Transport layer of the condition and make a transition to the L1: L_IDLE state. Transition LR1:4: When the Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. LR2: L_RcvWaitFifo state: This state is entered when an X_RDYP has been received, and the FIFO is not ready to receive a FIS. When in this state, the Link layer shall transmit SYNCP. Serial ATA Revision 3.0 Gold Revision page 372 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transition LR2:1: When the Link layer receives X_RDYP from the Phy layer and the FIFO is ready to accept data, the Link layer shall make a transition to the LR1: L_RcvChkRdy state. Transition LR2:2: When the Link layer receives X_RDYP from the Phy layer and the FIFO is not ready to accept data, the Link layer shall make a transition to the LR2: L_RcvWaitFifo state. Transition LR2:3: When the Link layer receives any Dword other than X_RDYP from the Phy layer, the Link layer shall notify the Transport layer of the condition and make a transition to the L1: L_IDLE state. Transition LR2:4: When the Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. LR3: L_RcvData state: This state is entered when SOFP has been received from the Phy layer. When in this state, the Link layer receives an encoded character sequence from the Phy layer, decodes it into a Dword, and passes the Dword to the Transport layer. The Dword is also entered into the CRC calculation. When in this state the Link layer either transmits R_IPP to signal transmission to continue or transmits DMATP to signal the transmitter to terminate the transmission. Transition LR3:1: When the Transport layer indicates that space is available in its FIFO, the Link layer shall make a transition to the LR3: L_RcvData state. Transition LR3:2: When the Transport layer indicates that sufficient space is not available in its FIFO, the Link layer shall make a transition to the LR4: L_Hold state. Transition LR3:3: When the Link layer receives HOLDP from the Phy layer, the Link layer shall make a transition to the LR5: L_RcvHold state. Transition LR3:4: When the Link layer receives EOFP from the Phy layer, the Link layer shall make a transition to the LR6: L_RcvEOF state. Transition LR3:5: When the Link layer receives WTRMP from the Phy layer, the Link layer shall make a transition to the LR9: L_BadEnd state. Transition LR3:6: When the Link layer receives SYNCP from the Phy layer, the Link layer shall notify the Transport layer that reception was aborted and shall make a transition to the L1: L_IDLE state. Transition LR3:7: When the Link layer receives any Dword other than a HOLDP, HOLDAP, EOFP, or SYNCP primitive from the Phy layer, the Link layer shall make a transition to the LR3: L_RcvData state. Transition LR3:8: When the Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. Transition LR3:9: When the Link layer receives notification from the Transport layer that the current frame should be escaped, a transition to the L_SyncEscape state shall be made. LR4: L_Hold state: This state is entered when the Transport layer indicates that sufficient space is not available in its receive FIFO. Serial ATA Revision 3.0 Gold Revision page 373 of 663 When in this state, the Link layer shall transmit HOLDP and may receive an encoded character from the Phy layer. Transition LR4:1: When the Link layer receives any Dword other than a HOLDP primitive from the Phy layer and the Transport layer indicates that sufficient space is now available in its receive FIFO, the Link layer shall make a transition to the LR3: L_RcvData state. Transition LR4:2: When the Link layer receives HOLDP from the Phy layer and the Transport layer indicates that space is now available in its FIFO, the Link layer shall make a transition to the LR5: L_RcvHold state. Transition LR4:3: When the Link layer receives EOFP from the Phy layer, the Link layer shall make a transition to the LR6: L_RcvEOF state. Note that due to pipeline latency, an EOFP may be received when in the L_Hold state in which case the receiving Link shall use its FIFO headroom to receive the EOFP and close the frame reception. Transition LR4:4: When the Transport layer indicates that there is not sufficient space available in its FIFO and the Phy layer is ready, the Link layer shall make a transition to the LR4: L_Hold state. Transition LR4:5: When the Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. Transition LR4:6: When the Link layer receives SYNCP from the Phy layer, the Link layer shall notify the Transport layer of the illegal transition error condition and shall make a transition to the L1: L_IDLE state. Transition LR4:7: When the Link layer receives notification from the Transport layer that the current frame should be escaped, a transition to the L_SyncEscape state shall be made. LR5: L_RcvHold state: This state is entered when HOLDP has been received from the Phy layer. When in this state, the Link layer shall either transmit HOLDAP to signal transmission to proceed when the transmitter becomes ready or transmit DMATP to signal the transmitter to terminate the transmission. Transition LR5:1: When the Link layer receives any Dword other than a HOLDP or SYNCP primitive from the Phy layer, the Link layer shall make a transition to the LR3: L_RcvData state. Transition LR5:2: When the Link layer receives HOLDP from the Phy layer, the Link layer shall make a transition to the LR5: L_RcvHold state. Transition LR5:3: When the Link layer receives EOFP from the Phy layer, the Link layer shall make a transition to the LR6: L_RcvEOF state. Transition LR5:4: When the Link layer receives SYNCP from the Phy layer, the Link layer shall make a transition to the L1: L_IDLE state. The Transport layer shall be notified of the illegal transition error condition. Transition LR5:5: When the Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. Transition LR5:6: When the Link layer receives notification from the Transport layer that the current frame should be escaped, a transition to the L_SyncEscape state shall be made. Serial ATA Revision 3.0 Gold Revision page 374 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization LR6: L_RcvEOF state: This state is entered when the Link layer has received EOFP from the Phy layer. When in this state, the Link layer shall check the calculated CRC for the frame and transmit one or more R_IPP primitives. Transition LR6:1: If the CRC calculation and check is not yet completed, the Link layer shall make a transition to the LR6: L_RcvEOF state. Transition LR6:2: When the CRC indicates no error, the Link layer shall notify the Transport layer and make a transition to the LR7: L_GoodCRC state. Transition LR6:3: When the CRC indicates an error has occurred, the Link layer shall notify the Transport layer and make a transition to the LR9: L_BadEnd state. Transition LR6:4: When the Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. LR7: L_GoodCRC state: This state is entered when the CRC for the frame has been checked and determined to be good. When in this state, the Link layer shall wait for the Transport layer to check the frame and transmit one or more R_IPP primitives. Transition LR7:1: When the Transport layer indicates a good result, the Link layer shall transition to the LR8: L_GoodEnd state. Transition LR7:2: When the Transport layer indicates an unrecognized FIS, the Link layer shall transition to the LR9: L_BadEnd state. Transition LR7:3: If the Transport layer has not supplied status, then the Link layer shall transition to the LR7: L_GoodCRC state. Transition LR7:4: When the Link layer detects that the Phy layer is not ready, the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. Transition LR7:5: When the Transport layer or Link layer indicates an error was encountered during the reception of the recognized FIS, the Link layer shall transition to the LR9: L_BadEnd state. Transition LR7:6: When the Link layer receives SYNCP from the Phy layer, the Link layer shall notify the Transport layer of the illegal transition error condition and shall make a transition to the L1: L_IDLE state. LR8: L_GoodEnd state: This state is entered when the CRC for the frame has been checked and determined to be good. When in this state, the Link layer shall transmit R_OKP. Transition LR8:1: When the Link layer receives SYNCP from the Phy layer, the Link layer shall make a transition to the L1: L_IDLE state. Transition LR8:2: When the Link layer receives any Dword other than a SYNCP primitive from the Phy layer, the Link layer shall make a transition to the LR7: L_GoodEnd state. Serial ATA Revision 3.0 Gold Revision page 375 of 663 Transition LR8:3: When the Link layer detects that the Phy layer is not ready, the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. LR9: L_BadEnd state: This state is entered when the CRC for the frame has been checked and determined to be bad or when the Transport layer has notified the Link layer that the received FIS is invalid. When in this state, the Link layer shall transmit R_ERRP. Transition LR9:1: When the Link layer receives SYNCP from the Phy layer, the Link layer shall make a transition to the L1: L_IDLE state. Transition LR9:2: When the Link layer receives any Dword other than SYNCP from the Phy layer, the Link layer shall make a transition to the LR9: BadEnd state. Transition LR9:3: When the Link layer detects that the Phy layer is not ready the Link layer shall notify the Transport layer of the condition and make a transition to the LS1: L_NoCommErr state. 9.6.5 Link Power Mode State Diagram Table 72 – State Diagram Link Power Mode LPM1: L_TPMPartial Transmit PMREQ_PP. 1. PMACKP received from Phy layer. 2. X_RDYP received from Phy layer. L_ChkPhyRdy L_RcvWaitFifo1 3. SYNCP or R_OK P received from Phy layer. 4. AnyDword other than (PMACKP or PMNAKP PXM_RRDEYQP_oSrPS3Y)1NCrePceoirvRed_OfrKomP oPr hPyMlaRyEeQr._PP or 3 or 5. PMREQ_PP or PMREQ_SP received from Phy layer. 6. PHYRDYn L_TPMPartial L_IDLE L_TPMPartial3 L_NoCommErr2 7. PMNAKP received from Phy layer. L_NoPmnak NOTE: 1. This transition aborts the request from the Transport layer to enter a power mode. A status indication to the Transport layer of this event is required. 2. This is an unexpected transition and constitutes an error condition. An error condition needs to be sent to the Transport layer as a result. 3. If PMREQ_PP or PMREQ_SP is received, the host shall make a transition to the L_IDLE state, but the device shall make a transition to the L_TPMPartial state. Serial ATA Revision 3.0 Gold Revision page 376 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization LPM2: L_TPMSlumber Transmit PMREQ_SP. 1. PMACKP received from Phy layer. 2. X_RDYP received from Phy layer. 3. SYNCP or R_OK P received from Phy layer. 4. AXPnM_RyRDDEwYQoP_rodSrPoS3thY)1eNrrCethcPaeonivr e(RPd_MfOrAoKmCPKoPPrhoPyrMlPaRyMEeNrQ.A_KPPP3oror 5. PMREQ_PP or PMREQ_SP received from Phy layer. 6. PHYRDYn L_ChkPhyRdy L_RcvWaitFifo1 L_TPMSlumber L_IDLE L_TPMSlumber3 L_NoCommErr2 7. PMNAKP received from Phy layer. L_NoPmnak NOTE: 1. This transition aborts the request from the Transport layer to enter a power mode. A status indication to the Transport layer of this event is required. 2. This is an unexpected transition and constitutes an error condition. An error condition needs to be sent to the Transport layer as a result. 3. If PMREQ_PP or PMREQ_SP is received, the host shall make a transition to the L_IDLE state, but the device shall make a transition to the L_TPMSlumber state. LPM3: L_PMOff Transmit PMACKP1. 1. A total of 4<=n<=16 PMACKP primitives sent. L_ChkPhyRdy 2. Less than n PMACKP primitives sent. L_PMOff NOTE: 1. A flag is set according to whether a PMREQ_PP or PMREQ_SP was received from the Phy layer. LPM4: L_PMDeny Transmit PMNAKP. 1. PMREQ_PP or PMREQ_SP received from Phy layer. 2. AnyDword other than (PMREQ_PP or PMREQ_SP) received from Phy layer. 3. PHYRDYn L_PMDeny L_IDLE L_NoCommErr LPM5: L_ChkPhyRdy 1. PHYRDY 2. PHYRDYn Assert Partial/Slumber to Phy layer (as appropriate). L_ChkPhyRdy L_NoCommPower LPM6: L_NoCommPower Maintain Partial/Slumber assertion (as appropriate). 1. Transport layer requests a wakeup or COMWAKE detected. L_WakeUp1 2. Transport layer not requesting wakeup and COMWAKE not detected. L_NoCommPower Serial ATA Revision 3.0 Gold Revision page 377 of 663 LPM7: L_WakeUp1 1. PHYRDY 2. PHYRDYn Negate both Partial and Slumber. L_WakeUp2 L_WakeUp1 LPM8: L_WakeUp2 1. PHYRDY 2. PHYRDYn Transmit ALIGNP. L_IDLE L_NoCommErr LPM9: L_NoPmnak Transmit SYNCP. 1. PMNAKP received from Phy layer. 2. AnyDword other than (PMNAKP) received from Phy layer. L_NoPmnak L_IDLE LPM1: L_TPMPartial state: This state is entered when the Transport layer has indicated that a transition to the Partial power state is desired. Transition LPM1:1: When in this state PMREQ_PP shall be transmitted. When the Link layer receives PMACKP a transition to the LPM5: L_ChkPhyRdy state shall be made. Transition LPM1:2: If the Link layer receives X_RDYP a transition shall be made to the LR2: L_RcvWaitFifo state, effectively aborting the request to a power mode state. Transition LPM1:3: If the Link layer receives a SYNCP or R_OKP primitive, then it is assumed that the opposite side has not yet processed PMREQ_PP yet and time is needed. A transition to the LPM1: L_TPMPartial state shall be made. Transition LPM1:4: If the host Link layer receives any Dword from the Phy layer other than a PMACKP, PMNAKP, X_RDYP, SYNCP or R_OKP primitive, then the request to enter the Partial state is aborted and a transition to L1: L_IDLE shall be made. If the device Link layer receives any Dword from the Phy layer other than a PMACKP, PMNAKP, X_RDYP, SYNCP, PMREQ_PP, PMREQ_SP, or R_OKP primitive, then the request to enter the Partial state is aborted and a transition to L1: L_IDLE shall be made. Transition LPM1:5: The host Link layer shall not make this transition as it applies only to the device Link layer. If the device Link layer receives PMREQ_PP or PMREQ_SP from the host, it shall remain in this state by transitioning back to LPM1: L_TPMPartial. Transition LPM1:6: If the Link layer detects that the Phy layer has become not ready, this is interpreted as an error condition. The Transport layer shall be notified of the condition and a transition shall be made to the LS1: L_NoCommErr state. Transition LPM1:7: If the Link layer receives a PMNAKP, then the request to enter the Partial state is aborted and a transition to LPM9: L_NoPmnak shall be made. LPM2: L_TPMSlumber state: This state is entered when the Transport layer has indicated that a transition to the Slumber power state is desired. Transition LPM2:1: When in this state PMREQ_SP shall be transmitted. When the Link layer receives PMACKP, a transition to the LPM5: L_ChkPhyRdy state shall be made. Serial ATA Revision 3.0 Gold Revision page 378 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transition LPM2:2: If the Link layer receives X_RDYP, a transition to the LR2: L_RcvWaitFifo state shall be made, effectively aborting the request to a power mode state. Transition LPM2:3: If the Link layer receives SYNCP or R_OKP, then it is assumed that the opposite side has not yet processed PMREQ_SP yet and time is needed. The transition to the LPM2: L_TPMSlumber state shall be made. Transition LPM2:4: If the host Link layer receives any Dword from the Phy layer other than a PMACKP, PMNAKP, X_RDYP, SYNCP, or R_OKP primitive, then the request to enter the Slumber state is aborted and a transition to L1: L_IDLE shall be made. If the device Link layer receives any Dword from the Phy layer other than a PMACKP, PMNAKP, X_RDYP, SYNCP, PMREQ_PP, PMREQ_SP, or R_OKP primitive, then the request to enter the Slumber state is aborted and a transition to L1: L_IDLE shall be made. Transition LPM2:5: The host Link layer shall not make this transition as it applies only to the device Link layer. If the device Link layer receives PMREQ_PP or PMREQ_SP from the host, it shall remain in this state by transitioning back to LPM2: L_TPMSlumber. Transition LPM2:6: If the Link layer detects that the Phy layer has become not ready, this is interpreted as an error condition. The Transport layer shall be notified of the condition and a transition shall be made to the L_NoCommErr state. Transition LPM2:7: If the Link layer receives a PMNAKP, then the request to enter the Slumber state is aborted and a transition to LPM9: L_NoPmnak shall be made. LPM3: L_PMOff state: This state is entered when either PMREQ_SP or PMREQ_PP was received by the Link layer. The Link layer transmits PMACKP for each execution of this state. Transition LPM3:1: If 4<=n<=16 PMACKP primitives have been transmitted, a transition shall be made to the L_ChkPhyRdy state. Transition LPM3:2: If less than n PMACKP primitives have been transmitted, a transition shall be made to L_PMOff state. LPM4: L_PMDeny state: This state is entered when any primitive is received by the Link layer to enter a power mode and power modes are currently disabled. The Link layer shall transmit PMNAKP to inform the opposite end that a power mode is not allowed. Transition LPM4:1: If the Link layer continues to receive a request to enter any power mode than a transition back to the same LPM4: L_PMDeny state shall be made. Transition LPM4:2: If the Link layer receives any Dword other than a power mode request primitive, then the Link layer assumes that the power mode request has been removed and shall make a transition to the L1: L_IDLE state. Transition LPM4:3: If the Link layer detects that the Phy layer has become not ready, this is interpreted as an error condition. The Transport layer shall be notified of the condition and a transition shall be made to the LS1: L_NoCommErr state. LPM5: L_ChkPhyRdy state: This state is entered whenever it is desired for the Phy layer to enter a low power condition. For each execution in this state a request is made to the Phy layer to enter the state and deactivate the PHYRDY signal. Partial or Slumber is asserted to the Phy layer as appropriate. Serial ATA Revision 3.0 Gold Revision page 379 of 663 Transition LPM6:1: If the Phy layer has not yet processed the request to enter the power saving state and not deactivated the PHYRDY signal, then the Link layer shall remain in the LPM5: L_ChkPhyRdy state and continue to request the Phy layer to enter the power mode state. Transition LPM6:2: When the Phy layer has processed the power mode request and has deactivated the PHYRDY signal, then a transition shall be made to the LPM6: L_NoCommPower state. LPM6: L_NoCommPower state: This state is entered when the Phy layer has negated its PHYRDY signal indicating that it is in either Partial or Slumber state. In this state, the Link layer waits for the OOB detector to signal reception of the COMWAKE signal ( for a wakeup initiated by the other device ), or for the Transport layer to request a wakeup. Transition LPM6:1: If the Transport layer requests a wakeup or the OOB signal detector indicates reception of the COMWAKE signal, then a transition shall be made to LPM7: L_WakeUp1 Transition LPM6:2: If the Transport layer does not request a wakeup and the OOB detector does not indicate reception of the COMWAKE signal, then a transition shall be made to LPM6: L_NoCommPower. LPM7: L_WakeUp1 state: This state is entered when the Transport layer has initiated a wakeup. In this state, the Link layer shall negate both Partial and Slumber to the Phy layer, and wait for the PHYRDY signal from the Phy layer to be asserted. While in this state the Phy layer is performing the wakeup sequence. Transition LPM7:1 When the Phy layer asserts its PHYRDY signal, a transition shall be made to LPM8: L_WakeUp2. Transition LPM7:2: When the Phy layer remains not ready, a transition shall be made to LPM7: L_WakeUp1. LPM8: L_WakeUp2 state: This state is entered when the Phy layer has acknowledged an initiated wakeup request by asserting its PHYRDY signal. In this state, the Link layer shall transmit the ALIGN sequence, and transition to the L1: L_IDLE state. Transition LPM8:1 If the Phy layer keeps PHYRDY asserted, a transition shall be made to the L1: L_IDLE state. Transition LPM8:2 If the Phy layer negates PHYRDY, this is an error condition. The Transport layer shall be notified of the condition and a transition shall be made to the LS1: L_NoCommErr state. LPM9: L_NoPmnak state: This state is entered when the Link layer has indicated that a request to enter the Slumber or Partial state has been denied. The Link layer transmits SYNCP for each execution of this state. In this state, the Link layer waits for receipt of any Dword that is not PMNAKP from the Phy layer. Transition LPM9:1: If the Link layer receives PMNAKP, then the Link layer shall remain in the LPM9: L_NoPmnak state and continue to wait for receipt of a primitive that is not PMNAKP from the Phy layer. Transition LPM9:2: If the Link layer receives any Dword from the Phy layer other than PMNAKP, then the request to enter the power management state is aborted and a transition to L1: L_IDLE shall be made. Serial ATA Revision 3.0 Gold Revision page 380 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 10 Transport Layer 10.1 Overview The Transport layer need not be cognizant of how frames are transmitted and received. The Transport layer simply constructs Frame Information Structures (FISes) for transmission and decomposes received Frame Information Structures. Host and device Transport layer state differ in that the source of the FIS content differs. The Transport layer maintains no context in terms of ATA commands or previous FIS content. 10.1.1 FIS construction When requested to construct a FIS by a higher layer, the Transport layer provides the following services: Gathers FIS content based on the type of FIS requested. Places FIS content in the proper order. Notifies the Link layer of required frame transmission and passes FIS content to Link. Manages Buffer/FIFO flow, notifies Link of required flow control. Receives frame receipt acknowledge from Link layer. Reports good transmission or errors to requesting higher layer. 10.1.2 FIS decomposition When a FIS is received from the Link layer, the Transport layer provides the following services: Receives the FIS from the Link layer. Determines FIS type. Distributes the FIS content to the locations indicated by the FIS type. For the host Transport layer, receipt of a FIS may also cause the construction of a FIS to be returned to the device. Reports good reception or errors to higher layer 10.2 Frame Information Structure (FIS) 10.2.1 Overview A FIS is a group of Dwords that convey information between host and device as described previously. Primitives are used to define the boundaries of the FIS and may be inserted to control the rate of the information flow. This section describes the information content of the FIS referred to as payload - and assumes the reader is aware of the primitives that are needed to support the information content. The contents of the info field is divided into three categories: (1) register type, (2) setup type, and (3) data type. For each category the organization of each frame is defined in the following section. Serial ATA Revision 3.0 Gold Revision page 381 of 663 10.2.2 Payload content The type and layout of the payload is indicated by the Frame Information Type field located in byte 0 of the first Dword of the payload. See Figure 194 as an example. This example type is used primarily to transfer the contents of the Shadow Register Block Registers from the host to the device. Table 73 may be referenced to refresh the reader’s memory of a simplified version of the Shadow Register Block organization of an ATA adapter. Table 73 – Simplified Shadow Register Block register numbering A2 A1 A0 0 0 0 0 0 1 CS 0 0 1 0 Active 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Register access operation Read Write Data Port Error Features Sector Count [15:8], [7:0] LBA Low [31:24], [7:0] LBA Mid [39:32], [15:8] LBA High [47:40], [23:16] Device / Head Status Command CS 1 active 1 1 0 Alternate Status Device Control The following sections detail the types of payloads that are possible. The SOFP, EOFP and HOLDP primitives have been removed for clarity. 10.3 FIS Types The following sections define the structure of each individual FIS. 10.3.1 FIS Type values The value for the FIS Type fields of all FISes has been selected to provide additional robustness. In minimally buffered implementations that may not buffer a complete FIS, the state machines may begin acting on the received FIS Type value prior to the ending CRC having been checked. Because the FIS Type value may be acted upon prior to the integrity of the complete FIS being checked against its ending CRC, the FIS Type field values have been selected to maximize the Hamming distance between them. Figure 193 enumerates the FIS Type values and their assignments. Serial ATA Revision 3.0 Gold Revision page 382 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Type field value Description 27h Register FIS – Host to Device 34h Register FIS – Device to Host 39h DMA Activate FIS – Device to Host 41h DMA Setup FIS – Bi-directional 46h Data FIS – Bi-directional 58h BIST Activate FIS – Bi-directional 5Fh PIO Setup FIS – Device to Host A1h Set Device Bits FIS – Device to Host A6h Reserved for future Serial ATA definition B8h Reserved for future Serial ATA definition BFh Reserved for future Serial ATA definition C7h Vendor specific D4h Vendor specific D9h Reserved for future Serial ATA definition Figure 193 – FIS type value assignments 10.3.1.1 Unrecognized FIS Types A device or host may receive a FIS type that is not defined or vendor specific in Figure 193. The receiver of a FIS determines whether to handle a FIS type that is not defined or reserved as “unrecognized”. There may be cases where a receiver accepts undefined or vendor specific FISes. The host and device should negotiate any undefined or vendor specific FIS types that may be transmitted prior to their use. If the receiver decides to treat a FIS type as unrecognized, it shall follow the Link layer state machine definitions in section 9.6 upon receipt of that FIS type. 10.3.2 CRC Errors on Data FISes Following a Serial ATA CRC error on a Data FIS, if the device transmits a Device-to-Host FIS it shall set the ERR bit to one and both the BSY bit and DRQ bit cleared to zero in the Status field, and the ABRT bit set to one in the Error field. It is recommended for the device to also set the bit 7 (i.e. ICRC bit) to one in the Error field. See ATA8-ACS. There is no Device-to-Host FIS transmitted after a Serial ATA CRC error on the last Data FIS of a PIO-in command nor following a Serial ATA CRC error on the ATAPI command packet transfer. Thus, there is no mechanism for the device to indicate a Serial ATA CRC error to the host in either of these cases. The host should check the SError register to determine if a Link layer error has occurred in both of these cases. 10.3.3 All FIS types In all of the following FIS structures the following rules shall apply: 1. All reserved fields shall be written or transmitted as all zeroes 2. All reserved fields shall be ignored during the reading or reception process. Serial ATA Revision 3.0 Gold Revision page 383 of 663 10.3.4 Register - Host to Device 0 Features(7:0) Command C R R R PM Port FIS Type (27h) 1 Device LBA(23:16) LBA(15:8) LBA(7:0) 2 Features(15:8) LBA(47:40) LBA(39:32) LBA(31:24) 3 Control ICC 76543210 Count(15:8) 4 Reserved (0) Reserved (0) Reserved (0) Count(7:0) Reserved (0) Figure 194 – Register - Host to Device FIS layout If a field in this FIS is not defined by a command, it shall be Reserved for that command. Field Definitions FIS Type - Set to a value of 27h. Defines the rest of the FIS fields. Defines the length of the FIS as five Dwords. C - This bit is set to one when the register transfer is due to an update of the Command register. The bit is cleared to zero when the register transfer is due to an update of the Device Control register. Setting C bit to one and SRST bit to one in the Device Control Field is invalid and results in indeterminate behavior. Command - Contains the contents of the Command register of the Shadow Register Block. LBA(7:0) - Contains the contents of the LBA Low register of the Shadow Register Block. Control - Contains the contents of the Device Control register of the Shadow Register Block. LBA(15:8) - Contains the contents of the LBA Mid register of the Shadow Register Block. LBA(39:32) – Contains the contents of the expanded address field of the Shadow Register Block LBA(23:16) - Contains the contents of the LBA High register of the Shadow Register Block. LBA(47:40) – Contains the contents of the expanded address field of the Shadow Register Block Device - Contains the contents of the Device register of the Shadow Register Block. Features(7:0) - Contains the contents of the Features register of the Shadow Register Block. Features(15:8) – Contains the contents of the expanded address field of the Shadow Register Block PM Port – When an endpoint device is attached via a Port Multiplier, specifies the device port address that the FIS should be delivered to. This field is set by the host. R – Reserved – shall be cleared to zero. Count(7:0) - Contains the contents of the Sector Count register of the Shadow Register Block. Count(15:8) – Contains the contents of the expanded address field of the Shadow Register Block Serial ATA Revision 3.0 Gold Revision page 384 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization LBA(7:0) - Contains the contents of the LBA Low register of the Shadow Register Block. LBA(31:24) – Contains the contents of the expanded address field of the Shadow Register Block ICC - Isochronous Command Completion (ICC) contains a value is set by the host to inform device of a time limit. If a command does not define the use of this field, it shall be reserved. 10.3.4.1 Description The Register – Host to Device FIS is used to transfer the contents of the Shadow Register Block from the host to the device. This is the mechanism for issuing ATA commands to the device. 10.3.4.2 Transmission Transmission of a Register – Host to Device FIS is initiated by a write operation to either the command register, or a write to the Device Control register with a value different than is currently in the Device Control register in the host adapter’s Shadow Register Block. Upon initiating transmission, the current contents of the Shadow Register Block are transmitted and the C bit in the FIS is set according to whether the transmission was a result of the Command register being written or the Device Control register being written. The host adapter shall set the BSY bit in the shadow Status register to one within 400 ns of the write operation to the Command register that initiated the transmission. The host adapter shall set the BSY bit in the shadow Status register to one within 400 ns of a write operation to the Device Control register if the write to the Device Control register changes the state of the SRST bit from zero to one. The host adapter shall not set the BSY bit in the shadow Status register for writes to the Device Control register that do not change the state of the SRST bit from zero to one. It is important to note that Serial ATA host adapters enforce the same access control to the Shadow Register Block as parallel ATA devices enforce to the Command Block Registers. Specifically, the host is prohibited from writing the Features(7:0), Count(7:0), LBA(7:0), LBA(15:8), LBA(23:16), or Device registers when either BSY bit or DRQ bit is set in the Status Register. Any write to the Command Register when BSY bit or DRQ bit is set is ignored unless the write is to issue a Device Reset command. 10.3.4.3 Reception Upon reception of a valid Register - Host to Device FIS the device updates its local copy of the Command and Control Block Register contents. Then the device either initiates execution of the command indicated in the Command register or initiates execution of the control request indicated in the Device Control register, depending on the state of the C bit in the FIS. There are legacy BIOS and drivers that write the Device Control register to enable the interrupt just prior to issuing a command. To avoid unnecessary overhead, this FIS is transmitted to the device only upon a change of state from the previous value. Serial ATA Revision 3.0 Gold Revision page 385 of 663 10.3.5 Register - Device to Host 0 Error 1 Device 2 Reserved (0) 3 Reserved (0) 4 Reserved (0) Status LBA(23:16) LBA(47:40) Reserved (0) Reserved (0) R I R R PM Port LBA(15:8) LBA(39:32) Count(15:8) Reserved (0) FIS Type (34h) LBA(7:0) LBA(31:24) Count(7:0) Reserved (0) Figure 195 – Register - Device to Host FIS layout Field Definitions FIS Type - Set to a value of 34h. Defines the rest of the FIS fields. Defines the length of the FIS as five Dwords. LBA(15:8) - Contains the new value of the LBA Mid register of the Shadow Register Block. LBA(39:32) – Contains the contents of the expanded address field of the Shadow Register Block LBA(23:16) - Contains the new value of the LBA High register of the Shadow Register Block. LBA(47:40) – Contains the contents of the expanded address field of the Shadow Register Block Device - Contains the new value of the Device register of the Shadow Register Block. Error - Contains the new value of the Error register of the Shadow Register Block. I - Interrupt bit. This bit reflects the interrupt bit line of the device. Devices shall not modify the behavior of this bit based on the state of the nIEN bit received in Register Host to Device FISes. PM Port – When an endpoint device is attached via a Port Multiplier, specifies the device port address that the FIS is received from. This field is set by the Port Multiplier. Endpoint devices shall set this field to 0h. R - Reserved, – shall be cleared to zero. Count(7:0) - Contains the new value of the Sector Count register of the Shadow Register Block. Count(15:8) – Contains the contents of the expanded address field of the Shadow Register Block LBA(7:0) - Contains the new value of the LBA Low register of the Shadow Register Block. LBA(31:24) – Contains the contents of the expanded address field of the Shadow Register Block Status - Contains the new value of the Status (and Alternate status) register of the Shadow Register Block. 10.3.5.1 Description Serial ATA Revision 3.0 Gold Revision page 386 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization The Register – Device to Host FIS is used to by the device to update the contents of the host adapter’s Shadow Register Block. This is the mechanism by which devices indicate command completion status or otherwise change the contents of the host adapter’s Shadow Register Block. 10.3.5.2 Transmission Transmission of a Register - Device to Host FIS is initiated by the device in order to update the contents of the host adapter's Shadow Register Block. Transmission of the Register - Device to Host FIS is typically as a result of command completion by the device. The Register - Device to Host FIS shall only be used to set the SERV bit in the Status Register to request service for a bus released command if the BSY bit or the DRQ bit is currently set in the Status Register; the Set Device Bits FIS shall be used to set the SERV bit when the BSY bit and DRQ bit are both cleared to zero in the Status Register. The SERV bit transmitted with the Register - Device to Host FIS is written to the shadow Status Register and so the bit should accurately reflect the state of pending service requests when the FIS is transmitted as a result of a command completion by the device. 10.3.5.3 Reception Upon reception of a valid Register - Device to Host FIS the received register contents are transferred to the host adapter's Shadow Register Block. If the BSY bit and DRQ bit in the shadow Status Register are both cleared when a Register Device to Host FIS is received by the host adapter, then the host adapter shall discard the contents of the received FIS and not update the contents of any shadow register. 10.3.6 Set Device Bits - Device to Host 0 Error R Status Hi R Status Lo N I R R PM Port FIS Type (A1h) 1 Protocol Specific Figure 196 – Set Device Bits - Device to Host FIS layout Field Definitions FIS Type – Set to a value of A1h. Defines the rest of the FIS fields. Defines the length of the FIS as two Dwords. I – Interrupt Bit. This bit signals the host adapter to enter an interrupt pending state. If the host is executing tagged queued commands (READ FPDMA QUEUED, WRITE FPDMA QUEUED or NCQ QUEUE MANAGEMENT) with the device, the host should only enter the interrupt pending state if both the BSY bit and the DRQ bit in the shadow Status register are zero when the frame is received. If the host is executing native queued commands (READ FPDMA QUEUED, WRITE FPDMA QUEUED or NCQ QUEUE MANAGEMENT) with the device, the interrupt pending state is entered regardless of the current state of the BSY bit or the DRQ bit in the shadow Status register. Devices shall not modify the behavior of this bit based on the state of the nIEN bit received in Register Host to Device FISes. N – Notification Bit. This bit signals the host that the device needs attention. If the bit is set to one, the host should interrogate the device and determine what type of action is needed. If the bit is cleared to zero, the device is not requesting attention from the host. Refer to section 13.8. Serial ATA Revision 3.0 Gold Revision page 387 of 663 Error – Contains the new value of the Error register of the Shadow Register Block. PM Port – When an endpoint device is attached via a Port Multiplier, specifies the device port address that the FIS is received from. This field is set by the Port Multiplier. Endpoint devices shall set this field to 0h. Status-Hi – Contains the new value of bits 6, 5, and 4 of the Status register of the Shadow Register Block. Status-Lo– Contains the new value of bits 2,1, and 0 of the Status register of the Shadow Register Block. Protocol Specific – The value of this field is only defined for use with the Native Command Queuing Protocol. Refer to 13.6 for details. This field shall be cleared to zero for any uses other than Native Command Queuing (e.g. Asynchronous Notification). R – Reserved – shall be cleared to zero. 10.3.6.1 Description The Set Device Bits FIS is used by the device to load Shadow Register Block bits for which the device has exclusive write access. These bits are the eight bits of the Error register and six of the eight bits of the Status register. This FIS does not alter the BSY bit or the DRQ bit of the Status register. The FIS includes a bit to signal the host adapter to generate an interrupt if the BSY bit and the DRQ bit in the shadow Status Register are both cleared to zero when this FIS is received. Some Serial ATA to parallel ATA bridge solutions may elect to not support this FIS based on the requirements of their target markets. 10.3.6.2 Transmission The device transmits a Set Device Bits FIS to alter one or more bits in the Error register or in the Status register in the Shadow Register Block. This FIS should be used by the device to set the SERV bit in the Status register to request service for a bus released command. When used for this purpose the device shall set the Interrupt bit to one. 10.3.6.3 Reception Upon receiving a Set Device Bits FIS, the host adapter shall load the data from the Error field into the shadow Error register, the data from the Status-Hi field into bits 6, 5, and 4, of the shadow Status register, and the data from the Status-Lo field into bits 2, 1, and 0 of the shadow Status register. The BSY bit and the DRQ bit of the shadow Status register shall not be changed. If the Interrupt bit in the FIS is set to a one, and if both the BSY bit and the DRQ bit in the Shadow status register are cleared to zero when this FIS is received, then the host adapter shall enter an interrupt pending state. 10.3.7 DMA Activate - Device to Host 0 Reserved (0) Reserved (0) R R R R PM Port FIS Type (39h) Figure 197 – DMA Activate - Device to Host FIS layout Field Definitions FIS Type - Set to a value of 39h. Defines the rest of the FIS fields. Defines the length of the FIS as one Dword. Serial ATA Revision 3.0 Gold Revision page 388 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization PM Port – When an endpoint device is attached via a Port Multiplier, specifies the device port address that the FIS is received from. This field is set by the Port Multiplier. Endpoint devices shall set this field to 0h. R - Reserved – shall be cleared to zero. 10.3.7.1 Description The DMA Activate FIS is used by the device to signal the host to proceed with a DMA data transfer of data from the host to the device. A situation may arise where the host needs to send multiple Data FISes in order to complete the overall data transfer request. The host shall wait for a successful reception of a DMA Activate FIS before sending each of the Data FISes that are needed. 10.3.7.2 Transmission The device transmits a DMA Activate to the host in order to initiate the flow of DMA data from the host to the device as part of the data transfer portion of a corresponding DMA write command. When transmitting this FIS, the device shall be prepared to subsequently receive a Data - Host to Device FIS from the host with the DMA data for the corresponding command. 10.3.7.3 Reception Upon receiving a DMA Activate, if the host adapter’s DMA controller has been programmed and armed, the host adapter shall initiate the transmission of a Data FIS and shall transmit in this FIS the data corresponding to the host memory regions indicated by the DMA controller’s context. If the host adapter’s DMA controller has not yet been programmed and armed, the host adapter shall set an internal state indicating that the DMA controller has been activated by the device, and as soon as the DMA controller has been programmed and armed, a Data FIS shall be transmitted to the device with the data corresponding to the host memory regions indicated by the DMA controller context. 10.3.8 DMA Setup – Device to Host or Host to Device (Bidirectional) 0 Reserved (0) 1 2 3 4 5 6 Reserved (0) A I D R PM Port DMA Buffer Identifier Low DMA Buffer Identifier High Reserved (0) DMA Buffer Offset DMA Transfer Count Reserved (0) FIS Type (41h) Figure 198 – DMA Setup – Device to Host or Host to Device FIS layout Field Definitions Serial ATA Revision 3.0 Gold Revision page 389 of 663 FIS Type - Set to a value of 41h. Defines the rest of the FIS fields. Defines the total length of the FIS as seven Dwords. D Direction - Specifies whether subsequent data transferred after this FIS is from transmitter to receiver or from receiver to transmitter If set to one the direction is transmitter to receiver.If cleared to zero, the direction is receiver to transmitter. A Auto-Activate - If set to one, in response to a DMA Setup FIS with data transfer direction of Host-to-Device, causes the host to initiate transfer of the first Data FIS to the device after the DMA context for the transfer has been established. The device shall not transmit a DMA Activate FIS to trigger the transmission of the first Data FIS from the host. If cleared to zero, a DMA Activate FIS is required to trigger the transmission of the first Data FIS from the host when the data transfer direction is Host-to-Device. DMA Buffer Identifier Low/High - This field is used to identify a DMA buffer region in host memory. The contents are not described in this specification and are host dependent. The buffer identifier is supplied by the host to the device and the device echoes it back to the host. This allows the implementation to pass a physical address or or, in more complex implementations, the buffer identifier could be a scatter gather list or other information that may identify a DMA “channel”. DMA Buffer Offset - This is the byte offset into the buffer. Bits [1:0] shall be zero. DMA Transfer Count - This is the number of bytes to be read or written. Bit zero shall be zero. I Interrupt - If the Interrupt bit is set to one an interrupt pending shall be generated when the DMA transfer count is exhausted. Devices shall not modify the behavior of this bit based on the state of the nIEN bit received in Register Host to Device FISes. PM Port – When an endpoint device is attached via a Port Multiplier, specifies the device port address that the FIS should be delivered to or is received from. This field is set by the host for Host to Device transmission and this field is set by the Port Multiplier for Device to Host transmission. Endpoint devices shall set this field to 0h for Device to Host transmissions. R - Reserved – shall be cleared to zero. 10.3.8.1 Description The DMA Setup – Device to Host or Host to Device FIS is the mechanism by which first-party DMA access to host memory is initiated. This FIS is used to request the host or device to program its DMA controller before transferring data. The FIS allows the actual host memory regions to be abstracted (depending on implementation) by having memory regions referenced via a base memory descriptor representing a memory region that the host has granted the device access to. The specific implementation for the memory descriptor abstraction is not defined. The device or host is informed of the 64-bit DMA buffer identifier/descriptor at some previous time by an implementation specific mechanism such as a command issued to or as defined in a specification. Random access within a buffer is accomplished by using the buffer offset. First party DMA is a superset capability not necessarily supported by legacy mode devices or legacy mode device drivers but essential for accommodating future capabilities. 10.3.8.2 Transmission A device or host transmits a DMA Setup – Device to Host or Host to Device FIS as the first step in performing a DMA access. The purpose of the DMA Setup – Device to Host or Host to Device is to establish DMA hardware context for one or more data transfers. Serial ATA Revision 3.0 Gold Revision page 390 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization A DMA Setup – Device to Host or Host to Device is required only when the DMA context is to be changed. Multiple Data – Host to Device or Device to Host FISes may follow in either direction, for example, if the transfer count exceeds the maximum Data – Host to Device or Device to Host transfer length or when a data transfer is interrupted. When multiple Data – Host to Device or Device to Host FISes follow a DMA Setup – Device to Host or Host to Device FIS, the device or host shall place the data contained in the FIS in sequential addresses; that is, if the last Dword of a FIS is placed in (or obtained from) address N, the first Dword of a subsequent Data – Host to Device or Device to Host shall be placed in (or obtained from) address N+4 unless an intervening DMA Setup – Device to Host or Host to Device FIS is used to alter the DMA context. This mechanism allows for the efficient streaming of data into a buffer. 10.3.8.3 Reception Upon receiving a DMA Setup – Device to Host or Host to Device FIS, the receiver of the FIS shall validate the received DMA Setup request, and provided that the buffer identifier and the specified offset/count are valid, program and arm the adapter’s DMA controller using the information in the FIS. The specific implementation of the buffer identifier and buffer/address validation is not specified. After a valid DMA Setup – Device to Host or Host to Device FIS with the D bit cleared to zero, the receiver of the DMA Setup – Device to Host or Host to Device FIS responds with one or more Data – Host to Device or Device to Host FISes until the DMA count is exhausted. After a valid DMA Setup – Device to Host or Host to Device FIS with the D bit set to one, the receiver of the FIS shall be prepared to accept one or more Data – Host to Device or Device to Host FISes until the DMA count is exhausted. An interrupt pending condition shall be generated upon the completion of the DMA transfer if the Interrupt bit is set to one. The definition of DMA transfer completion is system dependent but typically includes the exhaustion of the transfer count or the detection of an error by the DMA controller. NOTE First-party DMA accesses are categorized in two groups: command/status transfers and user-data transfers. Interrupts would not typically be generated on user-data transfers. The optimal interrupt scheme for command/status transfers is not defined in this specification. 10.3.8.3.1 Auto-Activate First Party DMA transfers from the host to the device require transmission of both the DMA Setup FIS and a subsequent DMA Activate FIS in order to trigger the host transfer of data to the device. Because the device may elect to submit the DMA Setup FIS only when it is already prepared to receive the subsequent Data FIS from the host, the extra transaction for the DMA Activate FIS may be eliminated by merely having the DMA Setup FIS automatically activate the DMA controller by setting the Auto-Activate ‘A’ bit to one in the DMA Setup FIS. Devices shall not attempt to utilize this capability prior to the optimization having been explicitly enabled by the host as defined in section 13.3.2. The host response to a DMA Setup FIS with the Auto-Activate bit set to one when the host has not enabled Auto-Activate is not defined. 10.3.8.4 HBA Enforcement of First-party DMA Data Phase Atomicity The host bus adapter shall ensure the First-party DMA Data Phase is uninterrupted. Unless the ERR bit in the shadow Status register is set, the host shall ensure no FIS other than requested data payload or a FIS for a software reset is transmitted from the host to device between the reception of a DMA Setup FIS and the exhaustion of the associated transfer count. Serial ATA Revision 3.0 Gold Revision page 391 of 663 10.3.9 BIST Activate - Bidirectional 0 Reserved (0) Pattern Definition R R R R PM Port FIS Type (58h) TASL FPRV 1 Data1 [31:24] Data1 [23:16] Data1 [15:8] Data1 [7:0] 2 Data2 [31:24] Data2 [23:16] Data2 [15:8] Data2 [7:0] Figure 199 – BIST Activate - Bidirectional Field Definitions FIS Type - Set to a value of 58h. Defines the rest of the FIS fields. PM Port – When an endpoint device is attached via a Port Multiplier, specifies the device port address that the FIS should be delivered to or is received from. This field is set by the host for Host to Device transmission and this field is set by the Port Multiplier for Device to Host transmission. Endpoint devices shall set this field to 0h for Device to Host transmissions. R - Reserved – shall be cleared to zero. Pattern Definition F – Far End Analog (AFE) Loopback (Optional) L - Far End Retimed Loopback* Transmitter shall insert additional ALIGNP primitives T - Far end transmit only mode A - ALIGNP Bypass (Do not Transmit ALIGNP primitives) (valid only in combination with T Bit) S - Bypass Scrambling (valid only in combination with T Bit) P - Primitive bit. (valid only in combination with the T Bit) (Optional) V - Vendor Specific Test Mode. Causes all other bits to be ignored Data1 – Dword #1 of data information used to determine what pattern is transmitted as a result of the BIST Activate FIS. Applicable only when the T bit is set to one. Data2 - Dword #2 of data information used to determine what pattern is transmitted as a result of the BIST Activate FIS. Applicable only when the T bit is set to one. 10.3.9.1 Description The BIST Activate FIS shall be used to place the receiver in one of several loopback modes. The BIST Activate FIS is a bi-directional FIS that may be sent by either the host or the device. The sender and receiver have distinct responsibilities in order to insure proper cooperation between the two parties. The state machines for transmission and reception of the FIS are symmetrical. The method of causing a BIST Activate FIS transmission is not defined in this specification. The state machines for the transmission of the FIS do not attempt to specify the actions the sender takes once successful transmission of the request has been performed. After the Application layer is notified of the successful transmission of the FIS the sender’s Application layer prepares its own Application, Transport and Physical layers into the appropriate states that support the transmission of a stream of data. The FIS shall not be considered successfully transmitted until the receiver has acknowledged reception of the FIS as per normal FIS transfers documented in various sections of this specification. The transmitter of the BIST Activate FIS should transmit continuous SYNCP primitives after reception of R_OKP until such a time that it is ready to interact with the receiver in the BIST exchange. Serial ATA Revision 3.0 Gold Revision page 392 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Similarly, the state machines for the reception of the FIS do not specify the actions of the receiver’s Application layer. Once the FIS has been received, the receiver’s Application layer places its own Application, Transport and Physical layers into states that perform the appropriate retransmission of the sender’s data. The receiver shall not enter the BIST state until after it has properly received a good BIST Activate FIS (good CRC), indicated a successful transfer of the FIS to the transmitting side via R_OKP and has received at least one good SYNCP. Once in the self-test mode, a receiver shall continue to allow processing of the COMINIT or COMRESET signals in order to exit from the self-test mode. Note, that BIST mode is intended for Inspection/Observation Testing, as well as support for conventional laboratory equipment, rather than for in-system automated testing. The setting of the F, L, and T bits is mutually exclusive. It is the responsibility of the sender of the BIST Activate FIS to ensure that only one of these bits is set. Refer to Table 74 for valid bit settings within a BIST Activate FIS. Table 74 – BIST Activate FIS Modes and Bit Settings BIST Test Mode FLTPASV Far End Analog Loopback 100 0 0 0 0 Far End Retimed Loopback 010 0 0 0 0 Far End Transmit with ALIGNs, scrambled data 0 0 1 0 0 0 0 Far End Transmit with ALIGNs, unscrambled data 0 0 1 0 0 1 0 Far End Transmit without ALIGNs, scrambled data 001 0 1 0 0 Far End Transmit without ALIGNs, unscrambled data 001 0 1 1 0 Far End Transmit primitives with ALIGNs 0 0 1 1 0 na 0 Far End Transmit primitives without ALIGNs 0 0 1 1 1 na 0 Vendor Specific na na na na na na 1 Key: 0 – bit shall be cleared to zero 1 – bit shall be set to one F: The Far End Analog (Analog Front End - AFE) Loopback Mode is defined as a vendor optional mode where the raw data is received, and retransmitted, without any retiming or resynchronization, etc. The implementation of Far End AFE Loopback is optional due to the roundtrip characteristics of the test as well as the lack of retiming. This mode is intended to give a quick indication of connectivity, and test failure is not an indication of system failure. L: The Far End Retimed LoopbackMode is defined as a mode where the receiver retimes the data, and retransmits the retimed data. The initiator of the retimed loopback mode shall account for the loopback device consuming up to two ALIGNP primitives (one ALIGN sequence) every 256 Dwords transmitted and, if it requires any ALIGNP primitives to be present in the returned data stream, it should insert additional ALIGNP primitives in the transmitted stream. The initiator shall transmit additional ALIGN sequences in a single burst at the normal interval of every 256 Dwords transmitted (as opposed to inserting ALIGN sequences at half the interval). The loopback device may remove zero, one, or two ALIGNP primitives from the received data. It may insert one or more ALIGNP primitives if they are directly preceded or followed by the initiator inserted ALIGNP primitives (resulting in ALIGN sequences consisting of at least two ALIGNP Serial ATA Revision 3.0 Gold Revision page 393 of 663 primitives) or it may insert two or more ALIGNP primitives if not preceded or followed by the initiator’s ALIGNP primitives. One side effect of the loopback retiming is that the returned data stream may have instances of an odd number of ALIGNP primitives, however, returned ALIGNP primitives are always in bursts and if the initiator transmitted dual ALIGN sequences (four consecutive ALIGNP primitives), then the returned data stream shall include ALIGNP bursts that are no shorter than two ALIGNP primitives long (although the length of the ALIGNP burst may be odd). The initiator of the retimed loopback mode shall not assume any relationship between the relative position of the ALIGNP primitives returned by the loopback device and the relative position of the ALIGNP primitives sent by the initiator. In retimed loopback mode, the initiator shall transmit only valid 8b/10b characters so the loopback device may 10b/8b decode it and re-encode it before retransmission. If the loopback device descrambles incoming data it is responsible for rescrambling it with the same sequence of scrambling syndromes in order to ensure the returned data is unchanged from the received data. The loopback device’s running disparity for its transmitter and receiver are not guaranteed to be the same and thus the loopback initiator shall 10b/8b decode the returned data rather than use the raw 10b returned stream for the purpose of data comparison. The loopback device shall return all received data unaltered and shall disregard protocol processing of primitives. Only the OOB signals and ALIGNP processing is acted on by the loopback device, while all other data is retransmitted without interpretation. T: The Far-End Transmit Mode is defined as a mode that may be used to invoke the Far-End Interface to send data patterns, upon receipt of the BIST Activate FIS, as defined by the content located in Data1 and Data2. Note that Data1 and Data2 shall be applicable only when the T bit is active, indicating “Far-End Transmit Mode”. It is not required that the values within Data1 and Data2 are equal. These two Dwords are programmable to any value. This data is modified by the following bits. P: The transmit primitives bit. When this bit is set in far end transmit mode, the lowest order byte of the two following Dwords are treated as K Characters in order to identify the appropriate primitive(s) for transmission. The encoding for primitives is defined in section 9.4. It is the responsibility of the sender of the BIST Activate FIS to ensure that the values contained within Data1 and Data2 are valid D character versions of the K character (i.e. BCh for K28.5). The setting of this bit is applicable only when the T bit is set. A: ALIGNP sequence bypass mode. When set to one, no ALIGNP primitives are sent. When the A-bit is not asserted, ALIGNP primitives are sent normally as defined in this document. The setting of this bit is applicable only when the T bit is set. S: The Bypass Scrambling Mode is defined as a mode that may be used to send data or patterns, during BIST activation, that are not scrambled, however are encoded and decoded to normal and legal 8b/10b values. The setting of this bit is applicable only when the T bit is set. The S bit is ignored when the P bit is set to one. V: The vendor unique mode is implementation specific and shall be reserved for individual vendor use. All other bits are ignored in this mode. 10.3.9.2 Transmission The initiator transmits a BIST Activate to the recipient in order to initiate the BIST mode of operation. 10.3.9.3 Reception Serial ATA Revision 3.0 Gold Revision page 394 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Upon receiving a BIST Activate, the recipient shall begin operations as per the BIST Activate FIS, described in this document above. 10.3.10 PIO Setup – Device to Host 0 Error Status R I D R PM Port FIS Type (5Fh) 1 Device LBA(23:16) LBA(15:8) LBA(7:0) 2 Reserved (0) LBA(47:40) LBA(39:32) LBA(31:24) 3 E_Status Reserved (0) Count(15:8) Count(7:0) 4 Reserved (0) Transfer Count Figure 200 – PIO Setup - Device to Host FIS layout Field Definitions FIS Type - Set to a value of 5Fh. Defines the rest of the FIS fields. Defines the length of the FIS as five Dwords. LBA(15:8) - Holds the contents of the LBA(15:8) register of the Command Block. LBA(39:32) – Contains the contents of the LBA(39:32) field of the Shadow Register Block LBA(23:16) - Holds the contents of the LBA(23:16) register of the Command Block. LBA(47:40) – Contains the contents of the LBA(47:40) field of the Shadow Register Block D - Specifies the data transfer direction. When set to one the transfer is from device to host, when cleared to zero the transfer is from host to device. Device - Holds the contents of the Device register of the Command Block. Status - Contains the new value of the Status register of the Command Block for initiation of host data transfer. Error - Contains the new value of the Error register of the Command Block at the conclusion of all subsequent Data to Device frames. I - Interrupt bit. This bit reflects the interrupt bit line of the device. Devices shall not modify the behavior of this bit based on the state of the nIEN bit received in Register – Host to Device FISes. PM Port – When an endpoint device is attached via a Port Multiplier, specifies the device port address that the FIS is received from. This field is set by the Port Multiplier. Endpoint devices shall set this field to 0h. R – Reserved – shall be cleared to zero. Count(7:0) - Holds the contents of the Count(7:0) register of the Command Block. Count(15:8) – Contains the contents of the Count(15:8) field of the Shadow Register Block LBA(7:0) - Holds the contents of the LBA(7:0) register of the Command Block. LBA(31:24) – Contains the contents of the LBA(31:24) field of the Shadow Register Block Serial ATA Revision 3.0 Gold Revision page 395 of 663 E_Status - Contains the new value of the Status register of the Command Block at the conclusion of the subsequent Data FIS. Transfer Count – Holds the number of bytes to be transferred in the subsequent Data FIS. The Transfer Count value shall be nonzero and the low order bit shall be zero (even number of bytes transferred). 10.3.10.1 Description The PIO Setup – Device to Host FIS is used by the device to provide the host adapter with sufficient information regarding a PIO data phase to allow the host adapter to efficiently handle PIO data transfers. For PIO data transfers, the device shall send to the host a PIO Setup – Device to Host FIS just before each and every data transfer FIS that is required to complete the data transfer. Data transfers from Host to Device as well as data transfers from Device to Host shall follow this algorithm. Because of the stringent timing constraints in the ATA standard, the PIO Setup FIS includes both the starting and ending status values. These are used by the host adapter to first signal to host software readiness for PIO write data (BSY bit is cleared to zero and DRQ bit is set to one), and following the PIO write burst to properly signal host software by clearing the DRQ bit to zero and possibly setting the BSY bit to one. 10.3.10.2 Transmission of PIO Setup by Device Prior to a Data Transfer from Host to Device The device transmits a PIO Setup – Device to Host FIS to the host in preparation for a PIO data payload transfer just before each and every PIO data payload transfer required to complete the total data transfer for a command. The device includes in the FIS the values to be placed in the Shadow Status register at the beginning of the PIO data payload transfer and the value to be placed in the Shadow Status register at the end of the data payload transfer. The device shall be prepared to receive a Data FIS in response to transmitting a PIO Setup FIS. 10.3.10.3 Reception of PIO Setup by Host Prior to a Data Transfer from Host to Device Upon receiving a PIO Setup – Device to Host FIS, the host shall update all Shadow registers and shall hold the E_Status value in a temporary register. The Transfer Length value shall be loaded into a countdown register. Upon detecting the change in the Shadow Status register, host software proceeds to perform a series of write operations to the Data shadow register, which the host adapter shall collect to produce a Data FIS to the device. Each write of the Data shadow register results in another word of data being concatenated into the Data FIS, and the countdown register being decremented accordingly. The E_Status value shall be transferred to the Shadow Status register within 400 ns of the countdown register reaching terminal count. In the case that the transfer length represents an odd number of words, the last word shall be placed in the low order (word 0) of the final Dword and the high order word (word 1) of the final Dword shall be padded with zeros before transmission. This process is repeated for each and every data FIS needed to complete the overall data transfer of a command. 10.3.10.4 Transmission of PIO Setup by Device Prior to a Data Transfer from Device to Host The device transmits a PIO Setup – Device to Host FIS to the host in preparation for a PIO data payload transfer just before each and every PIO data payload transfer required to complete the total data transfer for a command. The device includes in the FIS the values to be placed in the Shadow Status register at the beginning of the PIO data payload transfer and the value to be placed in the Shadow Status register at the end of the data payload transfer. The device shall be prepared to transmit a Data FIS following the transmittal of a PIO Setup FIS. Serial ATA Revision 3.0 Gold Revision page 396 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 10.3.10.5 Reception of PIO Setup by Host Prior to a Data Transfer from Device to Host Upon receiving a PIO Setup – Device to Host FIS for a device to host transfer, the host shall hold the Status, Error, and E_Status values in temporary registers. The Transfer Length value shall be loaded into a countdown register. Upon reception of a Data FIS from the device, the host shall update all Shadow registers and host software proceeds to perform a series of read operations from the Data shadow register. Each read of the Data shadow register results in a countdown register being decremented accordingly. The E_Status value shall be transferred to the Shadow Status register within 400 ns of the countdown register reaching terminal count. This process is repeated for each and every data FIS needed to complete the overall data transfer of a command. 10.3.11 Data - Host to Device or Device to Host (Bidirectional) 0 Reserved (0) Reserved (0) R R R R PM Port FIS Type (46h) … N Dwords of data … (minimum of one Dword - maximum of 2048 Dwords) n Figure 201 – Data – Host to Device or Device to Host FIS layout Field Definitions FIS Type - Set to a value of 46h. Defines the rest of the FIS fields. Defines the length of the FIS as n+1 Dwords. Dwords of data - Contain the actual data to transfer. Only 32 bit fields are transferred. The last Dword is padded with zeros when only a partial Dword is to be transmitted. NOTE The maximum amount of user data that may be sent in a single Data – Host to Device or Data – Device to Host FIS is limited. See description. PM Port – When an endpoint device is attached via a Port Multiplier, specifies the device port address that the FIS should be delivered to or is received from. This field is set by the host for Host to Device transmission and this field is set by the Port Multiplier for Device to Host transmission. Endpoint devices shall set this field to 0h for Device to Host transmissions. R – Reserved – shall be cleared to zero. 10.3.11.1 Description The Data – Host to Device and the Data – Device to Host FISes are used for transporting payload data, such as the data read from or written to a number of sectors on a hard drive. The FIS may either be generated by the device to transmit data to the host or may be generated by the host to transmit data to the device. This FIS is generally only one element of a sequence of transactions Serial ATA Revision 3.0 Gold Revision page 397 of 663 leading up to a data transmission and the transactions leading up to and following the Data FIS establish the proper context for both the host and device. The byte count of the payload is not an explicit parameter, rather it is inferred by counting the number of Dwords between SOFP and EOFP, and discounting the FIS type and CRC Dwords. The payload size shall be no more than 2048 Dwords (8192 bytes). Non-packet devices, with or without bridges, should report a SET MULTIPLE limit of 16 sectors or less in word 47 of their IDENTIFY DEVICE information. In the case that the transfer length represents an odd number of words, the last word shall be placed in the low order (word 0) of the final Dword and the high order word (word 1) of the final Dword shall be padded with zeros before transmission. 10.3.11.2 Transmission The device transmits a Data – Device to Host FIS to the host during the data transfer phase of legacy mode PIO reads, DMA reads, and First-party DMA writes to host memory. The device shall precede a Data FIS with any necessary context-setting transactions as appropriate for the particular command sequence. For example, a First-party DMA host memory write shall be preceded by a DMA Setup – Device to Host FIS to establish proper context for the Data FIS that follows. The host transmits a Data – Host to Device FIS to the device during the data transfer phase of PIO writes, DMA writes, and First-party DMA reads of host memory. The FIS shall be preceded with any necessary context-setting transactions as appropriate for the particular command sequence. For example, a legacy mode DMA write to the device is preceded by a DMA Activate – Device to Host FIS with the DMA context having been pre-established by the host. When used for transferring data for DMA operations multiple Data – Host to Device or Device to Host FISes may follow in either direction. Segmentation may occur when the transfer count exceeds the maximum Data – Host to Device or Device to Host transfer length or if a data transfer is interrupted. When used for transferring data in response to a PIO Setup, the Data FIS shall contain the number of bytes indicated in the Transfer Count field of the preceding PIO Setup FIS. In the event that a transfer is broken into multiple FISes, all intermediate FISes shall contain an integral number of full Dwords. If the total data transfer is for an odd number of words, then the high order word (word 1) of the last Dword of the last FIS shall be padded with zeros before transmission and discarded on reception. The Serial ATA protocol does not permit for the transfer of an odd number of bytes. 10.3.11.3 Reception Neither the host nor device is expected to buffer an entire Data FIS in order to check the CRC of the FIS before processing the data. Incorrect data reception for a Data FIS shall be reflected in the overall command completion status. Serial ATA Revision 3.0 Gold Revision page 398 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 10.4 Host transport states FIS reception is asynchronous in nature. In the case of a non-Data FIS transmission, the host may be pre-empted by a non-Data FIS reception from the device. The host shall hold off on the pending transmission and process the incoming FIS from the device before attempting to retransmit the pending FIS. 10.4.1 Host transport idle state diagram HTI1: HT_HostIdle Host adapter waits for frame or frame request. 1. Command Register FIS transmission pending HT_CmdFIS 2. Control Register FIS transmission pending HT_CntrlFIS 1 3. Frame receipt indicated by Link layer HT_ChkTyp3 4. DMA Setup FIS transmission pending HT_DMASTUPFIS 5. BIST Activate FIS transmission pending HT_XmitBIST 6. Previous FIS was PIO Setup and Application layer HT_PIOOTrans2 2 indicates data direction is host to device NOTE: 1. Transmission of a Control Register FIS is mandatory if the state of the SRST bit in the Device Control Shadow Register is changed, and is optional if the state of the SRST bit is not changed. If a Control Register FIS transmission with a modified value for the SRST bit is triggered while another non-Control Register FIS transmission is already pending, all pending non-Control Register FIS transmissions shall be aborted. If the state of the SRST bit is not modified from its previous value in a Control Register FIS transmission, then pending non-Control Register FIS transmissions shall not be aborted. 2. The PIO Setup FIS shall set an indication that PIO Setup was the last FIS received. Indication from the Application layer that it is transmitting data to the device may be determined from the Application layer performing write operations to the Data register in the Shadow Register Block. 3. FIS reception shall have priority over all other transitions in this state. Serial ATA Revision 3.0 Gold Revision page 399 of 663 HTI2: HT_ChkTyp Received FIS type checked. 1. Register FIS type detected HT_RegFIS 2. Set Device Bits FIS type detected 3. DMA Activate FIS type detected HT_DB_FIS HT_DMA_FIS 4. PIO Setup FIS type detected HT_PS_FIS 5. DMA Setup FIS type detected HT_DS_FIS 6. BIST FIS type detected HT RcvBIST 7. Data FIS type detected and previous FIS was not PIO Setup 8. Data FIS type detected and previous FIS was PIO Setup HT_DMAITrans 1 HT_PIOITrans1 1 9. Unrecognized FIS received HT_HostIdle 10. Notification of illegal transition error received from Link HT_HostIdle layer NOTE: 1. The PIO Setup FIS shall set an indication that PIO Setup was the last FIS sent, so that this state may determine whether to transition to DMA data transfer, or PIO data transfer. HTI1: HT_HostIdle state: This state is entered when a Frame Information Structure (FIS) transaction has been completed by the Transport layer. When in this state, the Transport layer waits for the shadow Command register to be written, the shadow Device Control register to be written, or the Link layer to indicate that a FIS is being received. TransitionHTI1:1: When a Command Register FIS transmission is pending, the Transport layer shall make a transition to the HTCM1: HT_CmdFIS state. A Command Register FIS becomes pending upon a write operation to the Command shadow register, and ceases pending at successful transmission of the FIS as indicated by the Link layer. Transition HTI1:2: When a Control Register FIS transmission is pending, the Transport layer shall make a transition to the HTCR1: HT_CntrlFIS state. A Control Register FIS becomes pending upon a write operation to the Device Control shadow register that changes the state of the SRST bit from the previous value, or optionally upon a write operation to the Device Control shadow register that does not change the state of the SRST bit. A Control Register FIS ceases pending at successful transmission of the FIS as indicated by the Link layer. Transition HTI1:3: When the Link layer indicates that a FIS is being received, the Transport layer shall make a transition to the HTI2: HT_ChkTyp state. Transition HTI1:4: When the Application layer indicates that a DMA Setup FIS is to be sent, the Transport layer shall make a transition to the HT_DMASTUP0:HT_DMASTUPFIS state. Transition HTI1:5: When the Application layer requests the transmission of a BIST request to the device the Transport layer shall make a transition to the HTXBIST1:HT state. Transition HTI1:6: When the Application layer requests the transmission of data to the device and the previous FIS was a PIOSetup type, the Transport layer shall make a transition to the HTPS3:HT_PIOOTrans2 state. The Application layer signals transmission of PIO data to the device by performing writes to the Data register in the Shadow Register Block. Serial ATA Revision 3.0 Gold Revision page 400 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization HTI2: HT_ChkTyp state: This state is entered when the Link layer indicates that a FIS is being received. When in this state, the Transport layer checks the FIS type of the incoming FIS. Transition HTI2:1: When the incoming FIS is a register type, the Transport layer shall notify the Link layer that it has received a valid FIS, and make a transition to the HTR1: HT_RegFIS state. Transition HTI2:2: When the incoming FIS is a Set Device Bits type, the Transport layer shall notify the Link layer that it has received a valid FIS and make a transition to the HTDB0:HT_DB_FIS state. Transition HTI2:3: When the incoming FIS is a DMA Activate type, the Transport layer shall notify the Link layer that it has received a valid FIS, and make a transition to the HTDA1: HT_DMA_FIS state. Transition HTI2:4: When the incoming FIS is a PIO Setup type, the Transport layer shall notify the Link layer that it has received a valid FIS, and make a transition to the HTPS1: HT_PS_FIS state. Transition HTI2:5: When the incoming FIS is a DMA Setup type, the Transport layer shall notify the Link layer that it has received a valid FIS, and make a transition to the HTDS1: HT_DS_FIS state. Transition HTI2:6: When the incoming FIS is a BIST Activate type, the Transport layer shall notify the Link layer that it has received a valid FIS, and make a transition to the HTRBIST1:HT_RcvBIST state. Transition HTI2:7: When the incoming FIS is a Data type, and the previous FIS was not a PIO Setup type, the Transport layer shall notify the Link layer that it has received a valid FIS, and make a transition to the HTDA5:HT_DMAITrans state. Transition HTI2:8: When the incoming FIS is a Data type, and the previous FIS was a PIO Setup type, the Transport layer shall notify the Link layer that it has received a valid FIS, and make a transition to the HTPS5:HT_PIOITrans1 state. Transition HTI2:9: When the received FIS is of an unrecognized, or unsupported type, the Transport layer shall notify the Link layer that it has received an unrecognized FIS, and make a transition to the HTI1: HT_HostIdle state. Transition HTI2:10: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the HTI1: HT_HostIdle state. Serial ATA Revision 3.0 Gold Revision page 401 of 663 10.4.2 Host Transport transmit command FIS diagram This protocol builds a FIS that contains the host adapter shadow register content and sends it to the device when the software driver or BIOS writes the host adapter shadow Command register. HTCM1: HT_CmdFIS Construct Register – Host to Device FIS with C bit set to one from the content of the shadow registers and notify Link to transfer. 1. FIS transfer complete HT_CmdTransStatus 2. Notification of illegal transition error received from Link layer 3. Frame receipt indicated by Link layer HT_HostIdle HT_HostIdle HTCM2: Check Link and Phy transmission results and if an error occurred HT_CmdTransStatus take appropriate action. 1. Status checked and no error detected HT_HostIdle 2. Status checked and error detected1 HT_HostIdle NOTE: 1. Upon return to the HT_HostIdle state in response to a detected error, the associated FIS remains pending for transmission HTCM1: HT_CmdFIS state: This state is entered when the shadow Command register is written. When in this state, the Transport layer shall construct a Register – Host to Device FIS with C bit set to one, notify the Link layer that the FIS is to be transmitted, and pass the FIS to the Link layer. Transition HTCM1:1: When the entire FIS has been passed to the Link layer, the Transport layer shall indicate to the Link layer that the FIS transmit is complete and make a transition to the HTCM2: HT_CmdTransStatus state. Transition HTCM1:2: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the HTI1: HT_HostIdle state. Transition HTCM1:3: When the Link layer indicates that a FIS is being received, the Transport layer shall make a transition to the HTI1:HT_HostIdle state. HTCM2: HT_CmdTransStatus state: This state is entered when the entire FIS has been passed to the Link layer. When in this state, the Transport layer shall wait for the Link and Phy layer ending status for the FIS and take appropriate error handling action if required. Transition HTCM2:1: When the FIS status has been handled and no errors detected, the Transport layer shall transition to the HTI1: HT_HostIdle state. Transition HTCM2:2: When the FIS status has been handled and an error has been detected, the Transport layer shall transition to the HTI1: HT_HostIdle state. The associated FIS remains pending for transmission. Serial ATA Revision 3.0 Gold Revision page 402 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 10.4.3 Host Transport transmit control FIS diagram This protocol builds a FIS that contains the host adapter shadow register content and sends it to the device when the software driver or BIOS writes the host adapter shadow Device Control register. HTCR1: HT_CntrlFIS Construct Register – Host to Device FIS with C bit cleared to zero from the content of the shadow registers and notify Link to transfer. 1. FIS transfer complete HT_CtrlTransStatus 2. Notification of illegal transition error received from Link layer 3. Frame receipt indicated by Link layer HT_HostIdle HT_HostIdle HTCR2: Check Link and Phy transmission results and if an error occurred HT_CtrlTransStatus take appropriate action. 1. Status checked and no errors detected HT_HostIdle 2. Status checked and error detected1 HT_HostIdle NOTE: 1. Upon return to the HT_HostIdle state in response to a detected error, the associated FIS remains pending for transmission HTCR1: HT_Cntrl_FIS state: This state is entered when the shadow Device Control register is written. When in this state, the Transport layer shall construct a Register – Host to Device FIS with C bit cleared to zero, notify the Link layer that the FIS is to be transmitted, and pass the FIS to the Link layer. Transition HTCR1:1: When the entire FIS has been passed to the Link layer, the Transport layer shall indicate to the Link layer that the FIS transmit is complete and make a transition to the HTCR2: HT_CtrlTransStatus state. Transition HTCR1:2: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the HTI1: HT_HostIdle state. Transition HTCR1:3: When the Link layer indicates that a FIS is being received, the Transport layer shall make a transition to the HTI1:HT_HostIdle state. HTCR2: HT_CtrlTransStatus state: This state is entered when the entire FIS has been passed to the Link layer. When in this state, the Transport layer shall wait for the Link and Phy ending status for the FIS and take appropriate error handling action if required. Transition HTCR2:1: When the FIS status has been handled and no errors have been detected, the Transport layer shall transition to the HTI1: HT_HostIdle state. Transition HTCR2:2: When the FIS status has been handled and an error has been detected, the Transport layer shall transition to the HTI1: HT_HostIdle state. The associated FIS remains pending for transmission. Serial ATA Revision 3.0 Gold Revision page 403 of 663 10.4.4 Host Transport transmit DMA Setup – Device to Host or Host to Device FIS state diagram This protocol transmits a DMA Setup – Device to Host or Host to Device FIS to a receiver. This FIS is a request by a transmitter for the receiver to program its DMA controller for a First-party DMA transfer and is followed by one or more Data FISes that transfer data. The DMA Setup – Device to Host or Host to Device FIS request includes the transfer direction indicator, the host buffer identifier, the host buffer offset, the byte count, and the interrupt flag. HTDMASTUP0: Construct the DMA Setup – Host to Device or Device to Host FIS HT_DMASTUPFIS from the content provided by the Application layer and notifies Link to transfer. 1. FIS transfer complete HT_DMASTUPTrans Status 2. Notification of illegal transition error received from Link HT_HostIdle layer 3. Frame receipt indicated by Link layer HT_HostIdle HTPDMASTUP1: Check Link and Phy transmission results and if an error occurred HT_DMASTUPTransStatus take appropriate action. 1. Status checked and no error detected HT_HostIdle 2. Status checked and error detected1 HT_HostIdle NOTE: 1. Upon return to the HT_HostIdle state in response to a detected error, the associated FIS remains pending for transmission HTDMASTUP0: HT_DMASTUPFIS state: This state is entered when the Application requests the transmission of a DMA Setup – Host to Device or Device to Host FIS. When in this state, the Transport layer shall construct a DMA Setup – Host to Device or Device to Host FIS, notify the Link layer that the FIS is to be transmitted, and pass the FIS to the Link layer. Transition HTDMASTUP0:1: When the entire FIS has been passed to the Link layer, the Transport layer shall indicate to the Link layer that the FIS transmission is complete and make a transition to the HTDMASTUP1: HT_DMASTUPTransStatus state. Transition HTDMASTUP0:2: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the HTI1: HT_HostIdle state. Transition HTDMASTUP0:3: When the Link layer indicates that a FIS is being received, the Transport layer shall make a transition to the HTI1:HT_HostIdle state. HTPDMASTUP1: HT_DMASTUPTransStatus state: This state is entered when the entire FIS has been passed to the Link layer. When in this state, the Transport layer shall wait for the Link and Phy ending status for the FIS and take appropriate error handling action if required. Transition HTDMASTUP1:1: When the FIS status has been handled, and no error detected, the Transport layer shall transition to the HTI1: HT_HostIdle state. Serial ATA Revision 3.0 Gold Revision page 404 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transition HTDMASTUP1:2: When the FIS status has been handled, and an error detected, the Transport layer shall transition to the HTI1: HT_HostIdle state. The associated FIS remains pending for transmission. 10.4.5 Host Transport transmit BIST Activate FIS This protocol builds a BIST Activate FIS that tells the device to prepare to enter the appropriate Built-in Self-test mode. After successful transmission, the host Transport layer enters the idle state. The Application layer, upon detecting successful transmission to the device shall then cause the host’s Transport layer, Link layer and Physical layer to enter the appropriate mode for the transmission of the test data pattern defined by the FIS. The means by which the Transport, Link and Physical layers are placed into self-test mode are not defined by this specification. HTXBIST1: HT_XmitBIST Construct the BIST Activate FIS from the content provided by the Application layer and notify Link to transfer. 1. FIS transfer complete HT_TransBISTStatus 2. Notification of illegal transition error received from Link layer 3. Frame receipt indicated by Link layer HT_HostIdle HT_HostIdle HTXBIST2: Check Link and Phy transmission results and if an error occurred HT_TransBISTStatus take appropriate action. 1. Status check completed HT_HostIdle 2. Status check and at least one error detected HT_HostIdle1 NOTE: 1. Re-transmission of the BIST Activate FIS due to errors is not required but allowed. HTXBIST1: HT_XmitBIST state: This state is entered to send a BIST FIS to the device. Transition HTXBIST1:1: When the entire FIS has been passed to the Link layer, the Transport layer shall indicate to the Link layer that the FIS transmission is complete and make a transition to the HTXBIST2:HT_TransBISTStatus state. Transition HTXBIST1:2: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the HTI1: HT_HostIdle state. Transition HTXBIST1:3: When the Link layer indicates that a FIS is being received, the Transport layer shall make a transition to the HTI1:HT_HostIdle state. HTXBIST2: HT_TransBISTStatus state: This state is entered when the entire FIS has been passed to the Link layer. Transition HTXBIST2:1: When the FIS transmission is completed the Transport layer shall transition to the HTI1:HT_HostIdle state. Transition HTXBIST2:2: When the FIS transmission is completed and at least one error is detected the Transport layer shall transition to the HTI1:HT_HostIdle state. The associated FIS may remain pending for transmission. Serial ATA Revision 3.0 Gold Revision page 405 of 663 10.4.6 Host Transport decomposes Register FIS diagram This protocol receives a Register – Device to Host FIS from the device containing new shadow register content and places that content into the shadow registers. HTR1: HT_RegFIS Place FIS contents from device into appropriate holding registers. 1. FIS transfer complete HT_RegTransStatus 2. Notification of illegal transition error received from Link layer HT_HostIdle HTR2: HT_RegTransStatus Check Link and Phy transmission results and if an error occurred take appropriate action. 1. Status checked HT_HostIdle HTR1: HT_RegFIS state: This state is entered the Link layer has indicated that a FIS is being received and that the FIS is of the register type. When in this state, the Transport layer shall decompose the Register FIS and place the contents into the appropriate holding registers. Transition HTR1:1: When the entire Register – Device to Host FIS has been placed into the holding registers, the Transport layer shall make a transition to the HTR2: HT_RegTransStatus state. Transition HTR1:2: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the HTI1: HT_HostIdle state. HTR2: HT_RegTransStatus state: This state is when the entire FIS has been placed into the holding registers. When in this state, the Transport layer shall wait for the Link and Phy layer ending status for the FIS and take appropriate error handling action if required. Transition HTR2:1: When the FIS status has been handled and no errors detected, the contents of the holding registers shall be placed in the shadow registers and if the interrupt bit is set, the Transport layer shall set the interrupt pending flag. The Transport layer shall transition to the HTI1: HT_HostIdle state. When the FIS status has been handled and at least one error detected, the contents of the holding registers shall not be transferred to the shadow registers, error status shall be returned to the device, and the Transport layer shall transition to the HTI1: HT_HostIdle state. Serial ATA Revision 3.0 Gold Revision page 406 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 10.4.7 Host Transport decomposes a Set Device Bits FIS state diagram This protocol receives a Set Device Bits FIS from the device containing new Error and Status Shadow register content and places that content into the Error and Status Shadow registers. The Set Device Bits FIS may also contain SActive register content and asynchronous notification content. HTDB0:HT_DB_FIS Receive Set Device Bits FIS 1. FIS status checked and no error detected 2. FIS status checked and error detected. HT_Dev_Bits HT_HostIdle HTDB1:HT_Dev_Bits Load Error register and bits of the Status register 1. Register bits loaded HT_HostIdle HTDB0:HT_DB_FIS state: This state is entered when the Link layer has indicated that a FIS being received and that the FIS is a Set Device Bits type. When in this state, the Transport layer shall wait for the FIS reception to complete and for Link and Phy layer ending status to be posted. Transition HTDB0:1: When the FIS reception is complete with no errors detected, the Transport layer shall transition to the HTDB1:HT_Dev_Bits state. Transition HTDB0:2: When the FIS reception is complete with errors detected, the Transport layer shall return error status to the device and transition to the HTI1:HT_HostIdle state. HTDB1:HT_Dev_Bits state: This state is entered when a Set Device Bits FIS has been received with no errors. When in this state, the data in the Error field of the received FIS shall be loaded into the host adapter's shadow Error register. The data in the Status-Hi field of the received FIS shall be loaded into bits 6, 5, and 4 of the shadow Status register. The data in the Status-Lo field of the received FIS shall be loaded into bits 2, 1, and 0 of the shadow Status register. The BSY bit and the DRQ bit in the shadow Status register shall not be changed. If the Interrupt bit in the FIS is set to one and if both the BSY bit and the DRQ bit in the shadow Status register are cleared to zero, then the host adapter shall enter an interrupt pending state. Transition HTDB1:1: The Transport layer shall transition to the HTI1:HT_HostIdle state. Serial ATA Revision 3.0 Gold Revision page 407 of 663 10.4.8 Host Transport decomposes a DMA Activate FIS diagram This protocol receives a DMA Activate FIS that requests a DMA data out transfer. The data transfer is from the host to the device and the DMA Activate FIS causes the host adapter to transmit the data in a subsequent Data FIS. HTDA1: HT_DMA_FIS 1. Status checked and no error detected. 2. Status checked and error detected 3. Notification of illegal transition error received from Link layer HT_DMAOTrans1 HT_HostIdle HT_HostIdle HTDA2: HT_DMAOTrans1 DMA controller initialized? 1. DMA controller not initialized. 2. DMA controller initialized. 3. SRST asserted, or DEVICE RESET command requested HT_DMAOTrans1 HT_DMAOTrans2 HT_HostIdle HTDA3: HT_DMAOTrans2 Activate DMA controller 1. Transfer not complete and < 2048 Dwords transmitted 2. Transfer not complete and 2048 Dwords transmitted 3. Abort notification from Link layer 4. Transfer complete 5. Notification of illegal transition error received from Link layer 6. SRST asserted, or DEVICE RESET command requested HT_DMAOTrans2 HT_DMAEnd HT_DMAEnd HT_DMAEnd HT_HostIdle HT_HostIdle HTDA4: HT_DMAEnd Check DMA Controller completion 1. DMA controller actions completed, no error detected 2. DMA controller actions completed, and error detected. 3. Abort notification from Link layer, no error detected 4. Abort notification from Link layer, error detected. HT_HostIdle HT_HostIdle HT_HostIdle HT_HostIdle HTDA5: HT_DMAITrans Activate DMA controller if initialized, receive Data FIS. 1. Transfer not complete HT_DMAITrans 2. SRST asserted, or device reset command issued HT_HostIdle 3. Transfer complete HT_DMAEnd 4. Notification of illegal transition error received from Link layer HT_HostIdle HTDA1: HT_DMA_FIS state: This state is entered when the Link layer has indicated that a FIS is being received and the Transport layer has determined that a DMA Activate FIS is being received. When in this state, the Transport layer shall determine the direction of the DMA transfer being activated. Serial ATA Revision 3.0 Gold Revision page 408 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transition HTDA1:1: The Transport layer shall make a transition to the HTDA2: HT_DMAOTrans1 state. This transition occurs if no error is detected. Transition HTDA1:2: When an error is detected, status is conveyed to the Link layer and to the Application layer. The Transport layer shall make a transition to the HTI1:HT_HostIdle state. Transition HTDA1:3: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the HTI1: HT_HostIdle state. HTDA2: HT_DMAOTrans1 state: This state is entered when it is determined that the DMA transfer that is being activated is a transfer from host to device.. When in this state, the Transport layer shall determine if the DMA controller has been initialized. Transition HTDA2:1: When the DMA controller has not yet been initialized, the Transport layer shall transition to the HTDA2: HT_DMAOTrans1 state. Transition HTDA2:2: When the DMA controller has been initialized, the Transport layer shall transition to the HTDA3: HT_DMAOTrans2 state. Transition HTDA2:3: When the host has asserted the SRST bit by writing to the Device Control register, or the DEVICE RESET command is requested, the Transport layer shall inform the Link layer to send a SYNC Escape, and the Transport layer shall transition to the HTI1:HT_HostIdle state. HTDA3: HT_DMAOTrans2 state: This state is entered when the DMA controller has been initialized. When in this state, the Transport layer shall activate the DMA controller and pass data to the Link layer. Transition HTDA3:1: When the transfer is not complete and less than 2048 Dwords of payload data has been transmitted, the Transport layer shall transition to the HTDA3: HT_DMAOTrans2 state. Transition HTDA3:2: When the transfer is not complete but 2048 Dwords of payload data has been transmitted, the Link layer shall be notified to close the current frame and the Transport layer shall deactivate the DMA engine and transition to the HTDA4: HT_DMAEnd state. Transition HTDA3:3: When notified by the Link layer that the DMA Abort primitive was received, the Transport layer shall transition to the HTDA4: HT_DMAEnd state. Transition HTDA3:4: When the requested DMA transfer is complete, the Transport layer shall transition to the HTDA4: HT_DMAEnd state. Transition HTDA3:5: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the HTI1: HT_HostIdle state. Transition HTDA3:6: When the host has asserted the SRST bit by writing to the Device Control register, or the DEVICE RESET command is requested, the Transport layer shall inform the Link layer to send a SYNC Escape, and the Transport layer shall transition to the HTI1:HT_HostIdle state. HTDA4: HT_DMAEnd state: This state is entered when the DMA data transfer is complete. Serial ATA Revision 3.0 Gold Revision page 409 of 663 When in this state, the Transport layer shall ensure that the activities of the DMA controller have completed. Transition HTDA4:1: When the DMA controller has completed its activities, whether it has exhausted its transfer count or has been deactivated as a result of reaching the 2048 Dword data payload limit, the Transport layer shall transition to the HTI1: HT_HostIdle state. This transition occurs if no error is detected. NOTE : The host should not assume received data is valid (even with a valid CRC receipt for the FIS) until command completion status is returned by the device. Transition HTDA4:2: When an error is detected, status shall be reported to the Link and Application layers. The Transport layer shall transition to the HTI1:HT_HostIdle state. Transition HTDA4:3: When notified by the Link layer that a DMA Abort primitive was received, the transfer shall be truncated, and the Link layer notified to append CRC and end the frame. When it is determined that the transfer is completed with no error, the Transport layer shall make a transition to the HTI1:HT_HostIdle state. Transition HTDA4:4: When notified by the Link layer that a DMA Abort primitive was received, the transfer shall be truncated, and the Link layer notified to append CRC and end the frame. When it is determined that the transfer is completed with an error, the Transport layer shall report status to the Application layer and make a transition to the HTI1:HT_HostIdle state. HTDA5: HT_DMAITrans state: This state is entered when the Transport layer has determined that the DMA transfer being activated is from device to host. When in this state, the Transport layer shall activate the DMA controller if the DMA controller is initialized. A data frame is received from the device and a received data Dword shall be placed in the data FIFO. When in this state, the Transport layer shall wait until the Link layer has begun to receive the DMA data frame and data is available to be read by the host. Transition HTDA5:1: When the transfer is not complete, the Transport layer shall transition to the HTDA5: HT_DMAITrans state. This includes the condition where the host DMA engine has not yet been programmed and the transfer is therefore held up until the DMA engine is prepared to transfer the received data to the destination memory locations. Transition HTDA5:2: When the SRST bit is asserted by the host writing the Device Control register, or a device reset command has been written to an ATAPI device, the Link layer shall be informed to send SYNCP, and the Transport layer shall transition to the HTI1:HT_HostIdle state. Transition HTDA5:3: When the requested DMA transfer is complete, the Transport layer shall transition to the HTDA4: HT_DMAEnd state. Transition HTDA5:4: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the HTI1: HT_HostIdle state. Serial ATA Revision 3.0 Gold Revision page 410 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 10.4.9 Host Transport decomposes a PIO Setup FIS state diagram This protocol receives a PIO Setup FIS that requests a PIO data transfer. If the direction is from host to device, the Transport layer transmits a Data FIS to the device containing the PIO data. If the direction of transfer is from device to host, the Transport layer receives a Data FIS from the device. The PIO data shall be sent in a single Data FIS. HTPS1: HT_PS_FIS Determine the direction of the requested PIO transfer. 1. Transfer host to device, no error detected. D bit cleared to zero. HT_PIOOTrans1 2. Transfer device to host, no error detected. D bit set to one. HT_HostIdle 3. Error detected. HT_HostIdle 4. Notification of illegal transition error received from Link layer HT_HostIdle HTPS2: HT_PIOOTrans1 1. Unconditional Place initial register content received from FIS into shadow registers. HT_ HostIdle HTPS3: HT_PIOOTrans2 Wait for Link layer to indicate data transfer complete 1. Transfer not complete HT_PIOOTrans2 2. Transfer complete HT_PIOEnd 3. Abort notification from Link layer HT_PIOEnd 4. Notification of illegal transition error received from Link layer 5. SRST asserted, or DEVICE RESET command requested HT_HostIdle HT_HostIdle HTPS4: HT_PIOEnd Place ending register content from PIO REQ FIS into shadow registers. 1. No error detected. HT_HostIdle 2. Error detected HT_HostIdle HTPS5: HT_PIOITrans1 Wait until initial PIO data received in data frame. 1. Received PIO data available. HT_PIOITrans21 2. SRST asserted, or DEVICE RESET command HT_HostIdle requested 3. Notification of illegal transition error received from Link HT_HostIdle layer NOTE: 1. When transitioning to the HT_PIOITrans2 state, the starting status and Interrupt bit value from the PIO Setup FIS shall be transferred to the Shadow Status register and interrupt signal shall then reflect the value of the Interrupt bit. Serial ATA Revision 3.0 Gold Revision page 411 of 663 HTPS6: HT_PIOITrans2 Wait for Link layer to indicate data transfer complete. 1. Transfer not complete HT_PIOITrans2 2. Transfer complete HT_PIOEnd 3. Abort notification from Link layer HT_PIOEnd 4. Notification of illegal transition error received from Link layer 5. SRST asserted, or DEVICE RESET command requested HT_HostIdle HT_HostIdle HTPS1: HT_PS_FIS state: This state is entered when the Link layer has indicated that a FIS is being received and that the Transport layer has determined a PIO Setup FIS is being received. When in this state, the Transport layer shall determine the direction of the requested PIO transfer and indicate that the last FIS sent was a PIO Setup. Transition HTPS1:1: When the direction of transfer requested is from host to device (D bit cleared to zero), the Transport layer shall make a transition to the HTPS2: HT_PIOOTrans1 state. This transition occurs if no error is detected. Transition HTPS1:2: When the direction of transfer requested is from device to host (D bit set to one), the Transport layer shall make a transition to the HTI1:HT_HostIdle state. This transition occurs if no error is detected. Transition HTPS1:3: When an error is detected, status shall be reported to the Link layer. The Transport layer shall make a transition to the HTI1:HT_HostIdle state. Transition HTPS1:4: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the HTI1:HT_HostIdle state. HTPS2: HT_PIOOTrans1 state: This state is entered when the direction of the requested PIO data transfer is from host to device. When in this state, the Transport layer shall place the FIS initial register content into the shadow registers, the FIS byte count, and set the interrupt pending flag if the FIS indicates to do so. Transition HTPS2:1: When the FIS initial register content has been placed into the shadow registers, interrupt pending set if requested, and the Transport layer is ready to begin transmitting the requested PIO data FIS, the Transport layer shall make a transition to the HTI1:HT_HostIdle state. HTPS3: HT_PIOOTrans2 state: This state is entered when PIO data is available in the PIO FIFO to be passed the Link layer. When in this state, the Transport layer shall wait for the Link layer to indicate that all data has been transferred. NOTE Since the software driver or BIOS sees the DRQ bit set to one and the BSY bit cleared to zero, it continues writing the Data register filling the PIO FIFO. Transition HTPS3:1: When the transfer is not complete, the Transport layer shall transition to the HTPS3: HT_PIOOTrans2 state. Serial ATA Revision 3.0 Gold Revision page 412 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transition HTPS3:2: When the byte count for this DRQ data block is reached, the Transport layer shall transition to the HTPS4: HT_PIOEnd state. Transition HTPS3:3: When notified by the Link layer that the DMA Abort primitive was received, the Transport layer shall transition to the HTPS4: HT_PIOEnd state. Transition HTPS3:4: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the HTI1:HT_HostIdle state. Transition HTPS3:5: When the host has asserted the SRST bit by writing to the Device Control register, or the DEVICE RESET command is requested, the Transport layer shall inform the Link layer to send a SYNC Escape, and the Transport layer shall transition to the HTI1:HT_HostIdle state. HTPS4: HT_PIOEnd state: This state is entered when the PIO data transfer is complete. When in this state, the Transport layer shall place the ending register content from the received PIO request FIS into the shadow registers. Transition HTPS4:1: When the ending register content for the PIO request FIS has been placed into the shadow registers and there were no errors detected with the transfer, the Transport layer shall transition to the HTI1: HT_HostIdle state. NOTE : The host should not assume received data is valid (even with a valid CRC receipt for the FIS) until command completion status is returned by the device. Transition HTPS4:2: When the ending register content from the previous PIO Setup FIS has been placed into the shadow registers, the Transport layer shall transition to the HTI1:HT_HostIdle state. For data in transfers, the Transport layer shall notify the Link layer of any error encountered during the transfer, and the error shall be reflected in the end of frame handshake. If the transfer was not the final transfer for the PIO data in command, the device shall reflect the error status by transmitting an appropriate Register FIS to the host. If the transfer was the final transfer for the associated PIO data in command, the error condition is not detectable. For data out transfers, errors detected by the device shall be reflected in the end of frame handshake. The device shall reflect the error status by transmitting an appropriate Register FIS to the host. HTPS5: HT_PIOITrans1 state: This state is entered when the direction of the PIO data transfer is device to host. When in this state, the Transport layer shall wait until the Link layer has begun to receive the PIO data frame and data is available to be read by the host. Transition HTPS5:1: When data is available for the host to read in the shadow Data register, the Transport layer shall place the initial register content received in the PIO Setup frame into the shadow registers and transition to the HTPS6: HT_PIOITrans2 state. Transition HTPS5:2: When the host has asserted the SRST bit by writing to the Device Control register, or the DEVICE RESET command is requested, the Transport layer shall inform the Link layer to send a SYNC Escape, and the Transport layer shall transition to the HTI1: HT_HostIdle state. Transition HTPS5:3: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the HTI1:HT_HostIdle state. Serial ATA Revision 3.0 Gold Revision page 413 of 663 HTPS6: HT_PIOITrans2 state: This state is entered when PIO data is available in the PIO FIFO to be read by the host and the initial shadow register content has been set. When in this state, the Transport layer shall wait for the Link layer to indicate that the data transfer is complete Transition HTPS6:1: When the transfer is not complete, the Transport layer shall transition to the HTPS6: HT_PIOITrans2 state. Transition HTPS6:2: When the byte count for this DRQ data block is reached, the Transport layer shall transition to the HTPS4: HT_PIOEnd state. Transition HTPS6:3: When notified by the Link layer that the DMA Abort primitive was received, the Transport layer shall transition to the HTPS4: HT_PIOEnd state. Transition HTPS6:4: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the HTI1:HT_HostIdle state. Transition HTPS6:5: When the host has asserted the SRST bit by writing to the Device Control register, or the DEVICE RESET command is requested, the Transport layer shall inform the Link layer to send a SYNC Escape, and the Transport layer shall transition to the HTI1: HT_HostIdle state. 10.4.10 Host Transport decomposes a DMA Setup FIS state diagram This protocol receives a FIS that sets up the host adapter DMA controller to allow the transfer of subsequent Data FISes according to the First-party DMA protocol. For a a First-party DMA write request when Auto-Activate is not used, a separate DMA Activate FIS is issued by the device to trigger the start of the data transfer from the host. HTDS1: HT_DS_FIS Initialize the DMA controller for a First-party DMA transfer with the content of the DMA Setup FIS. 1. No error detected and (D bit set to one in DMA Setup HT_HostIdle FIS) or (Dbit cleared to zero and Auto-Activate bit cleared to zero in DMA Setup FIS). 2. Error detected. HT_HostIdle 3. Notification of illegal transition error received from Link layer 4. No error detected and (D bit cleared to zero and AutoActivate bit set to one in DMA Setup FIS). HT_HostIdle HT_DMAOTrans2 HTDS1: HT_DS_FIS state: This state is entered when the Link layer has indicated that a FIS is being received and that the Transport layer has determined the FIS is of the DMA Setup type. When in this state, the Transport layer shall initialize the DMA controller with content from the FIS. Transition HTDS1:1: When the DMA controller has been initialized and the request is a read (Direction is set to one) or the request is a write (Direction is cleared to zero) and Auto-Activate is zero in the DMA Setup FIS, the Transport layer shall transition to the HTI1: HT_HostIdle state. This transition is made if no error is detected. Serial ATA Revision 3.0 Gold Revision page 414 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transition HTDS1:2: When an error is detected, status shall be reported to the Link layer. The Transport layer shall transition to the HTI1:HI_HostIdle state. Transition HTDS1:3: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the HTI1:HT_HostIdle state. Transition HTDS1:4: When the DMA controller has been initialized and the request is a write (Direction is cleared to zero) and Auto-Activate is one in the DMA Setup FIS, the Transport layer shall transition to the HT_DMAOTrans2 state. This transition is made if no error is detected. 10.4.11 Host transport decomposes a BIST Activate FIS state diagram This protocol receives a BIST Activate FIS that instructs the host to enter one of several Built-in Self-test modes that cause the host to retransmit the data it receives. If the mode is supported the host’s Application layer places both the transmit and receive portions of the Transport, Link and/or Physical layers into appropriate state to perform the loopback operation. HTRBIST1: HT_RcvBIST Determine validity of loopback mode requested. 1. Status checked, no error detected and Loopback mode valid 2. Status checked, no error detected and Loopback mode is invalid or not supported. 3. Status checked and error detected HT_BISTTrans1 HT_HostIdle HT_HostIdle 4. Notification of illegal transition error received from Link layer HT_HostIdle HTRBIST2: HT_BISTTrans1 1. Unconditional Notify Application layer of desired BIST modes HT_HostIdle HTRBIST1: HT_RcvBIST state: This state is entered when the Link layer has indicated that a FIS is being received and the Transport layer has determined that a BIST Activate FIS is being received. When in this state, the Transport layer shall determine the validity of the loopback request. Transition HTRBIST1:1: If no reception error is detected and the FIS contents indicate a form of loopback request that is supported by the host the Transport layer shall make a transition to the HTRBIST2: HT_BISTTrans1 state. Transition HTRBIST1:2: If no reception error is detected and the FIS contents indicate a form of loopback request that is not supported by the host the Transport layer shall make a transition to the HTI1:HT_HostIdle state. Transition HTRBIST1:3: If a reception error is indicated the Transport layer shall make a transition to the HTI1:HT_HostIdle state. Transition HTRBIST1:4: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the HTI1:HT_HostIdle state. HTRBIST2: HT_BISTTrans1 state: This state is entered when the Transport layer has determined that a valid BIST Activate FIS has been received. Serial ATA Revision 3.0 Gold Revision page 415 of 663 Having received a valid FIS, the Transport layer informs the Application layer that it should place the Transport, Link and Physical layers into the appropriate modes to loop the received data back to the transmitter. The method by which this is performed is not defined by this specification. Transition HTRBIST2:1: When the Application layer has been notified the Transport layer shall transition to the HTI1:HostIdle state. 10.5 Device transport states 10.5.1 Device transport idle state diagram DTI0: DT_DeviceIdle Device waits for FIS or FIS request. 1. Transmission of Register – Device to Host FIS requested by Application layer 2. Transmission of Set Device Bits FIS requested by Application layer 3. Transmission of PIO Setup FIS requested by Application layer 4. Transmission of DMA Activate FIS requested by Application layer 5. Transmission of DMA Setup FIS requested by Application layer 6. Transmission of Data FIS requested by Application layer 7. Transmission of BIST Activate FIS requested by Application layer 8. Frame receipt indicated by Link layer DTI1: DT_ChkTyp Received FIS type checked. 1. Register – Host to Device FIS type detected 2. Data FIS type detected 3. DMA Setup FIS type detected 4. BIST Activate FIS type detected 5. Notification of illegal transition error received from Link layer or unrecognized FIS type DT_RegDHFIS DT_DB_FIS DT_PIOSTUPFIS DT_DMAACTFIS DT_DMASTUPDHFIS DT_DATAIFIS DT_XmitBIST DT_ChkTyp DT_RegHDFIS DT_DATAOFIS DT_DMASTUPHDFIS DT_RcvBIST DT_DeviceIdle DTI0: DT_DeviceIdle state: This state is entered when a Frame Information Structure (FIS) transaction has been completed by the Transport layer. When in this state, the Transport layer waits for the Application layer to indicate that a FIS is to be transmitted or the Link layer to indicate that a FIS is being received. Transition DTI0:1: When the Application layer indicates that a Register – Device to Host FIS is to be transmitted, the Transport layer shall make a transition to the DTR0: DT_RegDHFIS state. Transition DTI0:2: When the Application layer indicates that a Set Device Bits FIS is to be transmitted, the Transport layer shall make a transition to the DTDB0:DT_DB_FIS state. Serial ATA Revision 3.0 Gold Revision page 416 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transition DTI0:3: When the Application layer indicates that a PIO Setup FIS is to be transmitted, the Transport layer shall make a transition to the DTPIOSTUP0: DT_PIOSTUPFIS state. Transition DTI0:4: When the Application layer indicates that a DMA Activate FIS is to be transmitted, the Transport layer shall make a transition to the DTDMAACT0: DT_DMAACTFIS state. Transition DTI0:5: When the Application layer indicates that a DMA Setup FIS is to be transmitted, the Transport layer shall make a transition to the DTDMASTUP0: DT_DMASTUPDHFIS state. Transition DTI0:6: When the Application layer indicates that a Data FIS is to be transmitted, the Transport layer shall make a transition to the DTDATAI0: DT_DATAIFIS state. Transition DTI0:7: When the Application layer indicates that a BIST Activate FIS is to be transmitted, the Transport layer shall make a transition to the DTXBIST1:DT XmitBIST state. Transition DTI0:8: When the Link layer indicates that a FIS is being received, the Transport layer shall make a transition to the DTI1: DT_ChkTyp state. DTI1: DT_ChkTyp state: This state is entered when the Transport layer is idle and Link layer indicates that a FIS is being received. When in this state, the Transport layer checks the FIS type of the incoming FIS. Transition DTI1:1: When the incoming FIS is a Register – Host to Device FIS type, the Transport layer shall make a transition to the DTCMD0: DT_RegHDFIS state. Transition DTI1:2: When the incoming FIS is a Data - Host to Device FIS type, the Transport layer shall make a transition to the DTDATAO0: DT_DATAOFIS state. Transition DTI1:3: When the incoming FIS is a DMA Setup FIS type, the Transport layer shall make a transition to the DTSTP0: DT_ DMASTUPHDFIS state. Transition DTI1:4: When the incoming FIS is a BIST Activate FIS type, the Transport layer shall make a transition to the DTRBIST1:DT_RcvBIST state. Transition DTI1:5: When the Transport layer receives notification from the Link layer of an illegal state transition or the FIS type is not recognized, the Transport layer shall make a transition to the DTI0: DT_DeviceIdle state. 10.5.2 Device Transport sends Register – Device to Host state diagram This protocol builds a Register – Device to Host FIS that contains the register content and sends it to the host when the Application layer requests the transmission. DTR0: DT_RegDHFIS Construct Register – Device to Host FIS from the content of the registers and notify Link to transfer. 1. FIS transfer complete DT_RegTransStatus 2. Notification of illegal transition error received from Link layer DT_DeviceIdle Serial ATA Revision 3.0 Gold Revision page 417 of 663 DTR1: DT_RegTransStatus Check Link and Phy transmission results and if an error occurred take appropriate action. 1. Status checked, and no error detected. DT_DeviceIdle 2. Status checked, and error detected. DT_RegDHFIS DTR0: DT_RegDHFIS state: This state is entered the Application requests the transmission of a Register – Device to Host FIS. When in this state, the Transport layer shall construct a Register – Device to Host FIS, notify the Link layer that the FIS is to be transmitted, and pass the FIS to the Link layer. Transition DTR0:1: When the entire FIS has been passed to the Link layer, the Transport layer shall indicate to the Link layer that the FIS transmission is complete and make a transition to the DTR1: DT_RegTransStatus state. Transition DTR0:2: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the DTI0: DT_DeviceIdle state. DTR1: DT_RegTransStatus state: This state is when the entire FIS has been passed to the Link layer. When in this state, the Transport layer shall wait for the Link and Phy layer ending status for the FIS and take appropriate error handling action if required. Transition DTR1:1: When the FIS status has been handled, and no error detected, the Transport layer shall transition to the DTI0: DT_DeviceIdle state. Transition DTR1:2: When the FIS status has been handled, and an error detected, the Transport layer shall report status to the Link layer, and retry this transfer by transitioning to the DT_RegDHFISstate. 10.5.3 Device Transport sends Set Device Bits FIS state diagram This protocol sends a Set Device Bits FIS to the host adapter when the Application layer requests the transmission. DTDB0: DT_DB_FIS Inform Link to transmit Set Device Bits FIS 1. FIS transfer complete 2. Notification of illegal transition error received from Link layer DT_SDBTransSt atus DT_DeviceIdle DTDB1: Check Link and Phy transmission results and if an error occurred DT_SDBTransStatus take appropriate action. 1. Status checked and no error detected DT_DeviceIdle 2. Status checked and error detected. DT_DB_FIS Serial ATA Revision 3.0 Gold Revision page 418 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization DTDB0:DT_DB_FIS state: This state is entered when the Application layer requests the transmission of a Set Device Bits FIS. When in this state, the Transport layer shall construct a Set Device Bits FIS, notify the Link layer that the FIS is to be transmitted, and pass the FIS to the Link layer. Transition DTDB0:1: When the entire FIS has been passed to the Link layer, the Transport layer shall indicate to the Link layer that the FIS transmission is complete and make a transition to the DTDB1:DT_SDBTransStatus state. Transition DTDB0:2: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the DTI0: DT_DeviceIdle state. DTDB1:DT_SDBTransStatus state: This state is entered when the entire FIS has been passed to the Link layer. When in this state, the Transport layer shall wait for the Link and Phy layer ending status for the FIS and take appropriate error handling action if required. Transition DTDB1:1: When the FIS status has been handled and no error detected, the Transport layer shall transition to the DTI0:DT_DeviceIdle state. Transition DTDB1:2: When the FIS status has been handled and an error detected, the Transport layer shall report status to the Link layer and retry this transfer by transitioning to the DTDB0:DT_DB_FIS state. 10.5.4 Device Transport transmit PIO Setup – Device to Host FIS state diagram This protocol transmits a PIO Setup – Device to Host FIS to the host. Following this PIO Setup frame, a single data frame containing PIO data shall be transmitted or received depending on the state of the D bit in the PIO Setup frame. DTPIOSTUP0: Construct PIO Setup – Device to Host FIS from the content DT_PIOSTUPFIS provided by the Application layer and notify Link to transfer. This FIS shall include the beginning and ending register content, the byte count, and the interrupt flag. 1. FIS transfer complete DT_PIOSTUPTransSt atus 2. Notification of illegal transition error received from Link DT_DeviceIdle layer DTPIOSTUP1: Check Link and Phy transmission results and if an error occurred DT_PIOSTUPTransStatus take appropriate action. 1. Status checked, and no error detected. DT_Device Idle 2. Status checked, and error detected. DT_PIOSTUPFIS DTPIOSTUP0: DT_PIOSTUPFIS state: This state is entered the Application layer requests the transmission of a PIO Setup – Device to Host FIS. When in this state, the Transport layer shall construct a PIO Setup – Device to Host FIS, notify the Link layer that the FIS is to be transmitted, and pass the FIS to the Link layer. Serial ATA Revision 3.0 Gold Revision page 419 of 663 Transition DTPIOSTUP0:1: When the entire FIS has been passed to the Link layer, the Transport layer shall indicate to the Link layer that the FIS transmission is complete and make a transition to the DTPIOSTUP1: DT_PIOSTUPTransStatus state. Transition DTPIOSTUP0:2: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the DTI0: DT_DeviceIdle state. DTPIOSTUP1: DT_PIOSTUPTransStatus state: This state is entered when the entire FIS has been passed to the Link layer. When in this state, the Transport layer shall wait for the Link and Phy ending status for the FIS and take appropriate error handling action if required. Transition DTPIOSTUP1:1: When the FIS status has been handled and no error detected, the Transport layer shall transition to the DTI0: DT_DeviceIdle state. Transition DTPIOSTUP1:2: When the FIS status has been handled and an error detected, the Transport layer shall report status to the Link layer and retry this transfer by transitioning to the DT_PIOSTUPFIS state. 10.5.5 Device Transport transmit DMA Activate FIS state diagram This protocol transmits a DMA Activate FIS to the host adapter. Following the DMA Activate FIS, a Data FIS shall be sent from the host to the device. DTDMAACT0: Construct DMA Activate FIS from the content provided by the DT_DMAACTFIS Application layer and notify Link to transfer. 1. FIS transfer complete DT_DMAACTTransSt atus 2. Notification of illegal transition error received from Link DT_DeviceIdle layer DTDMAACT1: DT_DMAACTTransStatus Check Link and Phy transmission results and if an error occurred take appropriate action. 1. Status checked, and no error detected. DT_DeviceIdle 2. Status checked, and error detected. DT_DMAACTFIS DTDMAACT0: DT_DMAACTFIS state: This state is entered when the Application layer requests the transmission of a DMA Activate FIS. When in this state, the Transport layer shall construct a DMA Activate FIS, notify the Link layer that the FIS is to be transmitted, and pass the FIS to the Link layer. Transition DTDMAACT0:1: When the entire FIS has been passed to the Link layer, the Transport layer shall indicate to the Link layer that the FIS transmission is complete and make a transition to the DTDMAACT1: DT_DMAACTTransStatus state. Transition DTDMAACT0:2: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the DTI0: DT_DeviceIdle state. Serial ATA Revision 3.0 Gold Revision page 420 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization DTDMAACT1: DT_DMAACTTransStatus state: This state entered is when the entire FIS has been passed to the Link layer. When in this state, the Transport layer shall wait for the Link and Phy ending status for the FIS and take appropriate error handling action if required. Transition DTDMAACT1:1: When the FIS status has been handled and no error detected, the Transport layer shall transition to the DTI0: DT_DeviceIdle state. Transition DTDMAACT1:2: When the FIS status has been handled and an error detected, the Transport layer shall report status to the Link layer and retry this transfer by transitioning to the DT_DMAACTFIS state. 10.5.6 Device Transport transmit DMA Setup – Device to Host FIS state diagram This protocol transmits a DMA Setup – Device to Host FIS to the host adapter. This FIS is a request by the device for the host adapter to program the DMA controller for a First-party DMA transfer and is followed by one or more Data FISes that transfer the data to or from the host adapter depending on the direction of the transfer. The DMA Setup – Device to Host request includes the transfer direction indicator, the host buffer identifier, the host buffer offset, the byte count, and the interrupt flag. DTDMASTUP0: Construct the DMA Setup – Device to Host FIS from the content DT_DMASTUPDHFIS provided by the Application layer and notify Link to transfer. 1. FIS transfer complete DT_DMASTUPTrans Status 2. Notification of illegal transition error received from Link DT_DeviceIdle layer DTDMASTUP1: Check Link and Phy transmission results and if an error occurred DT_DMASTUPTransStatus take appropriate action. 1. Status checked, and no error detected. DT_DeviceIdle 2. Status checked, and error detected. DT_DMASTUPDHFIS DTDMASTUP0: DT_DMASTUPDHFIS state: This state is entered when the Application layer requests the transmission of a DMA Setup – Device to Host FIS. When in this state, the Transport layer shall construct a DMA Setup – Device to Host FIS, notify the Link layer that the FIS is to be transmitted, and pass the FIS to the Link layer. Transition DTDMASTUP0:1: When the entire FIS has been passed to the Link layer, the Transport layer shall indicate to the Link layer that the FIS transmission is complete and make a transition to the DTDMASTUP1: DT_DMASTUPTransStatus state. Transition DTIDMASTUP0:2: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the DTI0: DT_DeviceIdle state. DTDMASTUP1: DT_DMASTUPTransStatus state: This state is entered when the entire FIS has been passed to the Link layer. When in this state, the Transport layer shall wait for the Link and Phy ending status for the FIS and take appropriate error handling action if required. Serial ATA Revision 3.0 Gold Revision page 421 of 663 Transition DTDMASTUP1:1: When the FIS status has been handled and no error detected, the Transport layer shall transition to the DTI0: DT_DeviceIdle state. Transition DTDMASTUP1:2: When the FIS status has been handled and an error detected, the Transport layer shall report status to the Link layer and retry this transfer by transitioning to the DT_DMASTUPDHFIS state. 10.5.7 Device Transport transmit Data – Device to Host FIS diagram This protocol builds a Data – Device to Host FIS. DTDATAI0: DT_DATAIFIS 1. Unconditional Construct Data – Device to Host FIS content from the content provided by the Application layer and notify Link to transfer. DT_DATAITrans DTDATAI1: Pass data Dwords from data FIFO to Link layer DT_DATAITrans 1. Transfer not complete DT_DATAITrans 2. Transfer complete DT_DATAIEnd 3. Application layer requests termination of DMA in transfer. 4. Notification of illegal transition error received from Link layer DT_DATAIEnd DT_DeviceIdle DTDATAI2: DT_DATAIEnd Check Link and Phy transmission results and if an error occurred take appropriate action. 1. Status checked, and no error detected. DT_DeviceIdle 2. Status checked, and error detected. DT_DeviceIdle 3. Application layer requests termination of DMA in transfer, no error detected. 4. Application layer requests termination of DMA in transfer, error detected. DT_DeviceIdle DT_DeviceIdle 5. Notification of illegal transition error received from Link layer DT_DeviceIdle DTDATAI0: DT_DATAFIS state: This state is entered when the Application layer has requested the transmission of a Data – Device to Host FIS. When in this state the Transport layer shall pass a portion of the DMA data to the Link layer. Transition DTDATAI0:1: When ready and there is data in the FIFO to be passed to the Link layer, the Transport layer shall transition to the DTDATAI1: DT_DATAITrans state. DTDATAI1: DT_DATAITrans state: This state is entered when data is available in the FIFO to be passed the Link layer. When in this state, the Transport layer shall pass a Dword of data from the FIFO to the Link layer. Transition DTDATAI1:1: When the transfer is not complete, the Transport layer shall transition to the DTDATAI1: DT_DATAITrans state. Serial ATA Revision 3.0 Gold Revision page 422 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transition DTDATAI1:2: When the transfer is complete, the Transport layer shall transition to the DTDATAI2: DT_DATAIEnd state. Transition DTDATAI1:3: When the Application layer requests that a DMA operation is to be aborted, the Transport layer shall transition to the DTDATAI2:DT_DATAIEnd state. Transition DTDATAI1:4: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the DTI0: DT_DeviceIdle state. DTDATAI2: DT_DATAIEnd state: This state is entered when the data transfer is complete or an abort has been requested by the Application layer. When in this state, the Transport layer shall wait for the Link layer and Phy layer ending status for the FIS and take appropriate error handling action if required. Transition DTDATAI2:1: When the FIS status has been handled and no error detected, the Transport layer shall transition to the DTI0: DT_DeviceIdle state. Transition DTDATAI2:2: When the FIS status has been handled and an error detected, status shall be reported to the Link layer. The Transport layer shall transition to the DTI0: DT_DeviceIdle state. Transition DTDATAI2:3: When the Application layer requests the termination of a DMA data in transaction, it reports the abort condition to the Link layer, waits for an EOFP and, if no error is detected, shall transition to the DTI0:DT_DeviceIdle state. Transition DTDATAI2:4: When the Application layer requests the termination of a DMA data in transaction, it reports the abort condition to the Link layer, waits for an EOFP, and if an error is detected, reports the error to the Link layer, and shall transition to the DTI0:DT_DeviceIdle state. Transition DTDATAI2:5: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall transition to the DTI0: DT_DeviceIdle state. 10.5.8 Device Transport transmit BIST Activate FIS diagram This protocol builds a BIST Activate FIS that tells the host to prepare to enter the appropriate Built-in Self Test mode. After successful transmission, the device Transport layer enters the idle state. The Application layer, upon detecting successful transmission to the host shall then cause the device’s Transport layer, Link layer and Physical layer to enter the appropriate mode for the transmission of the Built-in Test data defined by the FIS. The means by which the Transport, Link and Physical layers are placed into self-test mode are not defined by this specification. DTXBIST1: DT_XmitBIST Construct the BIST Activate FIS from the content provided by the Application layer and notifies Link to transfer. 1. FIS transfer complete DT_TransBISTStatus 2. Notification of illegal transition error received from Link layer DT_DeviceIdle Serial ATA Revision 3.0 Gold Revision page 423 of 663 DTXBIST2: Check Link and Phy transmission results and if an error occurred DT_TransBISTStatus take appropriate action. 1. Status check completed DT_DeviceIdle 2. Status check and at least one error detected DT_XmitBIST1 NOTE: 1. Re-transmission of the BIST Activate FIS due to errors is not required but allowed. Serial ATA Revision 3.0 Gold Revision page 424 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization DTXBIST1: DT_XmitBIST state: This state is entered to send a BIST FIS to the host. Transition DTXBIST1:1: When the entire FIS has been passed to the Link layer, the Transport layer shall indicate to the Link layer that the FIS transmission is complete and make a transition to the DTXBIST2:DT_TransBISTSTatus state. Transition DTXBIST1:2: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the DTI0: DT_DeviceIdle state. DTXBIST2: DT_TransBISTStatus state: This state is entered when the entire FIS has been passed to the Link layer. Transition DTXBIST2:1: When the FIS transmission is completed the Transport layer shall transition to the DTI0: DT_DeviceIdle state. Transition DTXBIST2:2: When the FIS transmission is completed and at least one error is detected, the Transport layer may transition to the DTXBIST1: DT_XmitBIST state. 10.5.9 Device Transport decomposes Register – Host to Device state diagram This protocol receives a Register – Host to Device FIS, places received register content into the device registers, and notifies the Application layer of the FIS receipt. DTCMD0: DT_RegHDFIS Receive a Register – Host to Device FIS 1. FIS transfer complete, and no error detected. 2. FIS transfer complete, and error detected 3. Notification of illegal transition error received from Link layer DT_DeviceIdle DT_DeviceIdle DT_DeviceIdle DTCMD0: DT_RegHDFIS state: This state is entered when the receipt of a DT_RegHDFISFIS is recognized. When in this state, the Transport layer shall receive the FIS and place the contents of the FIS into the device registers when it is determined that the FIS was received without error. Transition DTCMD0:1: When the entire FIS has been received from the Link layer without error, the Transport layer shall indicate to the Application layer that a command FIS was received and make a transition to the DTI0: DT_DeviceIdle state. Transition DTCMD0:2: When the entire FIS has been received from the Link layer and an error has been detected, status shall be sent to the Link layer. The Transport layer shall make a transition to the DTI0:DT_DeviceIdle state. Transition DTCMD0:3: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the DTI0: DT_DeviceIdle state. Serial ATA Revision 3.0 Gold Revision page 425 of 663 10.5.10 Device Transport decomposes Data (Host to Device) FIS state diagram This protocol receives a Data - Host to Device FIS. DTDATAO0: DT_DATAOFIS Unconditional Prepare to receive data DT_DATAOREC DTDATAO1: DT_DATAOREC Place received data Dword into data FIFO and signal Link to continue transfer. 1. Transfer not complete DT_DATAOREC 2. Transfer complete DT_DeviceIdle 3. Abort Transfer from Application layer DT_DeviceAbort 4. Notification of illegal transition error received from Link layer DT_DeviceIdle DTDATAO2: DT_DeviceAbort Signal Link to abort transfer. 1. Transfer not complete 2. Transfer complete DT_DATAOREC DT_ DeviceIdle DTDATAO0: DT_DATAOFIS state: This state is entered when the Link layer has indicated that a FIS is being received and that the Transport layer has determined the FIS is of Data - Host to Device type. When in this state, the Transport layer shall prepare to receive the data. Transition DTDATAO0:1: When ready to receive the data, the Transport layer shall make a transition to the DTDATAO1: DT_DATAOREC state. DTDATAO1: DT_DATAOREC state: This state is entered when the Transport layer is ready to receive the data. When in this state, the Transport layer shall wait for the Link layer to indicate the transfer is complete. Transition DTDATAO1:1: When Link layer has not indicated that the end of the FIS has been reached, the Transport layer shall transition to the DTDATAO1: DT_DATAOREC state. Transition DTDATAO1:2: When the Link layer indicates that the end of the FIS has been reached, the Transport layer shall transition to the DTI0: DT_DeviceIdle state. Transition DTDATAO1:3: When the Application layer indicates that the FIS is to be aborted, the Transport layer shall transition to the DTDATAO2: DT_DeviceAbort state. Transition DTDATAO1:4: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the DTI0: DT_DeviceIdle state. DTDATAO2: DT_DeviceAbort state: This state is entered when the Application layer indicates that the current transfer is to be aborted. Serial ATA Revision 3.0 Gold Revision page 426 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization When in this state, the Transport layer shall signal the Link layer to Abort the incoming transmission and return to either DT_DATAOREC or DT_DeviceIdle, depending upon the current state of the FIFO. If the abort occurs coincident with an end of transfer indication from the Link, then the transition to DTI0: DT_DeviceIdle is also accommodated. After issuing an Abort, the Transport returns to normal data transfer, and awaits the end of transfer indication from the Link. Transition DTDATAO2:1: Inform Link layer to issue an abort. When Transfer is not complete, the Transport layer shall transition to the DTDATAO1: DT_DATAOREC state. Transition DTDATAO2:2: Inform Link layer to issue an abort. When the Link layer indicates that the end of the FIS has been reached, the Transport layer shall transition to the DTI0: DT_DeviceIdle state. 10.5.11 Device Transport decomposes DMA Setup – Host to Device state diagram This protocol receives a DMA Setup – Host to Device FIS, passes received DMA Setup content, and notification of FIS receipt to the Application layer. DTSTP0: Receive a DMA Setup – Host to Device FIS DT_DMASTUPHDFIS 1. FIS transfer complete, and no error detected. DT_DeviceIdle 2. FIS transfer complete, and error detected DT_DeviceIdle 3. Notification of illegal transition error received from Link layer DT_DeviceIdle DTSTP0: DT_DMASTUPHDFIS state: This state is entered when the receipt of a DT_DMASTUP FIS is recognized. Transition DTSTP0:1: When the entire FIS has been received from the Link layer without error, the Transport layer shall indicate to the Application layer that a DMA Setup – Host to Device FIS was received and make a transition to the DTI0: DT_DeviceIdle state. Transition DTSTP0:2: When the entire FIS has been received from the Link layer and an error has been detected, status shall be sent to the link layer. The Transport layer shall make a transition to the DTI0: DT_DeviceIdle state. Transition DTSTP0:3: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the DTI0: DT_DeviceIdle state. Serial ATA Revision 3.0 Gold Revision page 427 of 663 10.5.12 Device Transport decomposes a BIST Activate FIS state diagram This protocol receives a FIS that instructs the device to enter one of several Built-in Self-test modes that cause the device to retransmit the data it receives. If the mode is supported the Device’s Application layer places both the transmit and receive portions of the Transport, Link and/or Physical layers into appropriate state to perform the loopback operation. DTRBIST1: DT_RcvBIST Determine validity of loopback mode requested. 1. Status checked, no error detected and Loopback mode valid DT_BISTTrans1 2. Status checked, no error detected and Loopback mode is invalid or not supported. DT_DeviceIdle 3. Status checked and error detected DT_DeviceIdle 4. Notification of illegal transition error received from Link layer DT_DeviceIdle DTRBIST2: DT_BISTTrans1 1. Unconditional Notify Application layer of desired BIST modes DT_DeviceIdle DTRBIST1: DT_RcvBIST state: This state is entered when the Link layer has indicated that a FIS is being received and the Transport layer has determined that a BIST Activate FIS is being received. When in this state, the Transport layer shall determine the validity of the loopback request. Transition DTRBIST1:1: If no reception error is detected and the FIS contents indicate a form of loopback request that is supported by the device the Transport layer shall make a transition to the DTRBIST2: DT_BISTTrans1 state. Transition DTRBIST1:2: If no reception error is detected and the FIS contents indicate a form of loopback request that is not supported by the device the Transport layer shall make a transition to the DTI0:DT_DeviceIdle state. Transition DTRBIST1:3: If a reception error is indicated the Transport layer shall make a transition to the DTI0:DT_DeviceIdle state. Transition DTRBIST1:4: When the Transport layer receives notification from the Link layer of an illegal state transition, the Transport layer shall make a transition to the DTI0: DT_DeviceIdle state. DTRBIST2: DT_BISTTrans1 state: This state is entered when the Transport layer has determined that a valid BIST Activate FIS has been received. Having received a valid FIS, the Transport layer informs the Application layer that it should place the Transport, Link and Physical layers into the appropriate modes to loop the received data back to the transmitter. The method by which this is performed is not defined by this specification. Transition DTRBIST2:1: When the Application layer has been notified the Transport layer shall transition to the DTI0:DT_DeviceIdle state. Serial ATA Revision 3.0 Gold Revision page 428 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 11 Device Command Layer protocol In the following Device command layer protocols, if the host sends COMRESET before the device has completed executing a command layer protocol, then the device shall start executing the COMRESET protocol from the beginning. If the device receives a Register – Host to Device FIS with C bit cleared to zero and the SRST bit set to one before the device has completed executing a command layer protocol, then the device shall start executing its software reset protocol from the beginning. SYNC Escape is used by a host or device to bring the link back to a known state, and may be used for vendor specific recovery of error or hang conditions. After a SYNC Escape is performed, a software reset may be necessary prior to issuing the next command to the device. 11.1 Power-on and COMRESET protocol If the host sends a hardware reset (power-on reset or COMRESET) regardless of the power management mode or the current device command layer state, the device shall execute the hardware reset protocol. Assertion of hardware reset is associated with entry into state DP1:DR_Reset within the Phy state machine. DHR0: Wait. Hardware_reset_asserted 1. Hardware reset negated. DHR1: Execute_diagnostics DHR1: Initialize hardware and execute diagnostics. Execute_diagnostics 1. Initialization and diagnostics completed successfully. DHR2: Send_good_status 2. Initialization completed and diagnostics failed. DHR3: Send_bad_status DHR2: Send_good_status Request transmission of Register FIS with good status. 1. Register FIS transmitted. DI0: Device_idle DHR3: Send_bad_status Request transmission of Register FIS with bad status. 1. Register FIS transmitted. DI0: Device_idle DHR0: Hardware_reset_asserted: This state is entered when the Transport layer indicates that a hardware reset (power-on reset or COMRESET) is asserted. When in this state, the device awaits the negation of a hardware reset which is associated with exit from state DP1:DR_Reset within the Phy state machine. Transition DHR0:1: When the Transport layer indicates that hardware reset has been negated, the device shall transition to the DHR1: Execute_diagnostics state. DHR1: Execute_diagnostics: This state is entered when the Transport layer indicates that the COMRESET signal has been negated. Serial ATA Revision 3.0 Gold Revision page 429 of 663 When in this state, the device initializes the device hardware and executes its power-up diagnostics. Transition DHR1:1: When the device hardware has been initialized and the power-up diagnostics successfully completed, the device shall transition to the DHR2: Send_good_status state. Transition DHR1:2: When the device hardware has been initialized and the power-up diagnostics failed, the device shall transition to the DHR3: Send_bad_status state. DHR2: Send_good_status: This state is entered when the device hardware has been initialized and the power-up diagnostics successfully completed. When in this state, the device requests that the Transport layer transmit a Register FIS to the host. If the device does not implement the PACKET command feature set the register content shall be: Count(7:0) LBA(7:0) LBA(15:8) LBA(23:16) Device Error Status 01h 01h 00h 00h na 01h 00h-70h (see note) NOTE Setting of bits [6:4] in the Status register are device specific. If the device implements the PACKET command feature set, the register content shall be: Count(7:0) 01h LBA(7:0) 01h LBA(15:8) 14h LBA(23:16 EBh Device na Error 01h Status 00h Transition DHR2:1: When the Transport layer indicates that the Register FIS has been transmitted, the device shall transition to the DI0: Device_Idle state. Serial ATA Revision 3.0 Gold Revision page 430 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization DHR3: Send_bad_status: This state is entered when the device hardware has been initialized and the power-up diagnostics failed. When in this state, the device requests that the Transport layer transmit a Register FIS to the host. If the device does not implement the PACKET command feature set the register content shall be: Count(7:0) LBA(7:0) LBA(15:8) LBA(23:16 Device Error Status 01h 01h 00h 00h na 00h, 02h-7Fh 00h-70h (see note) NOTE Setting of bits [6:4] in the Status register are device specific. If the device implements the PACKET command feature set, the register content shall be: Count(7:0) LBA(7:0) LBA(15:8) LBA(23:16 Device Error Status 01h 01h 14h EBh na 00h, 02h-7Fh 00h Transition DHR3:1: When the Transport layer indicates that the Register FIS has been transmitted, the device shall transition to the DI0: Device_Idle state. Serial ATA Revision 3.0 Gold Revision page 431 of 663 11.2 Device Idle protocol The state diagram below describes the idle protocol for a device. States and transitions preceded by an * are utilized when Native Command Queuing or ATA Tagged Command Queuing commands are implemented. DI0: Device_idle Wait. 1. FIS receipt DI1: Check_FIS 2. * Ready to complete released command. DI4: Set_service 3. * Ready to receive data for WRITE FPDMA QUEUED DFPDMAQ4: command and FIS receipt not indicated and no error DataPhase_ encountered PreWriteSetup 4. * Ready to transmit data for READ FPDMA QUEUED DFPDMAQ3: command and FIS receipt not indicated and no error DataPhase_ encountered ReadSetup 5. * One or more FPDMA QUEUED or NCQ QUEUE DFPDMAQ10: MANAGEMENT commands completed successfully and FIS receipt not indicated and no error encountered SendStatus1 6. * FPDMA QUEUED or NCQ QUEUE MANAGEMENT DFPDMAQ11: command terminated with failure and FIS receipt not ERROR indicated 7. Asynchronous Notification is enabled and event has AN0: Notify_host occurred that requires notification and NotifyPending = 0 and FIS receipt not indicated. NOTE: 1. This condition may be true simultaneously with condition 3 or 4. Devices implementing status aggregation may select any of the transitions 3, 4, or 5 if their conditions evaluate to true. Devices not implementing status aggregation shall prioritize transition 5 over transitions 3 and 4. DI1: Check_FIS Check_FIS type and C bit. 1. Register type, C bit cleared to zero, and SRST set to one. 2. Register type, C bit cleared to zero, and SRST cleared to zero. 3. Register type and C bit set to one. 4. DMA Setup FIS Received DSR0: Software_reset_ asserted DI0: Device_idle1 DI2: Check_command DI0 : Device_idle 5. Unexpected FIS type. DI0: Device_idle NOTE: 1. A Device to Host Register FIS shall not be sent in response to the received Register FIS. Serial ATA Revision 3.0 Gold Revision page 432 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization DI2: Check_command1 Check the command to determine required command protocol. If asynchronous notification is supported then NotifyPending is cleared to zero. 1. Non-data command protocol and no native queued DND0: Non-data command outstanding. 2. PIO data-in command protocol and no native queued DPIOI0: PIO_in command outstanding. 3. PIO data-out command protocol and no native queued DPIOO0: PIO_out command outstanding. 4. READ DMA command protocol and no native queued DDMAI0: DMA_in command outstanding. 5. WRITE DMA command protocol and no native queued DDMAO0: DMA_out command outstanding. 6. PACKET command protocol and no native queued DPKT0: PACKET command outstanding. 7. * READ DMA QUEUED command protocol and no DDMAQI0: native queued command outstanding. DMA_queued_in 8. * WRITE DMA QUEUED command protocol and no DDMAQO0: native queued command outstanding. DMA_queued_out 9. EXECUTE DEVICE DIAGNOSTIC command protocol DEDD0: and no native queued command outstanding. Execute_device_diag 10. DEVICE RESET command protocol. DDR0: Device_reset 11. Command not implemented and no native queued DI3: No_command command outstanding. 12. * SERVICE command protocol and no native queued DI5: Service_test command outstanding. 13. * READ FPDMA QUEUED command protocol. DFPDMAQ1: AddCommand_ ToQueue 14. * WRITE FPDMA QUEUED command protocol. DFPDMAQ1: AddCommand_ ToQueue 15. * NCQ QUEUE MANAGEMENT command protocol. DFPDMAQ1: AddCommand_ ToQueue 16. * Not READ FPDMA QUEUED and not WRITE FPDMA DFPDMAQ12: QUEUED and not NCQ QUEUE MANAGEMENT and BrokenHost_ not DEVICE RESET and native queued command(s) ClearBusy outstanding NOTE: 1. This state shows transitions for all commands. If a device does not implement any particular command, then that transition should not be processed. DI3: No_command Request transmission of Register FIS with ABRT bit set to one. 1. FIS transmission complete. DI0: Device_idle * DI4: Set_service Request transmission of Set Device Bits FIS with SERV set. 1. FIS transmission complete. DI0: Device_idle Serial ATA Revision 3.0 Gold Revision page 433 of 663 * DI5: Service_test Test command to see if Register FIS is needed to set DRQ bit and set Tag. 1. PACKET PIO data-in or PACKET PIO data-out. DI7: Service_decode 2. Other DI6: Service_send_tag * DI6: Service_send_tag Request transmission of Register FIS with BSYbit cleared to zero, DRQ bit set to one, and appropriate Tag 1. FIS transmission complete DI7: Service_decode * DI7: Service_decode Check command type to be serviced. 1. PACKET PIO data-in. 2. PACKET PIO data-out. 3. PACKET DMA data-in. 4. PACKET DMA data-out. 5. READ DMA QUEUED. 6. WRITE DMA QUEUED. DPKT4: PACKET_PIO_in DPKT6: PACKET_PIO_out DPKT9: PACKET_DMA_in DPKT11: PACKET_DMA_out DDMAQI1: Send_data DDMAQO1: Send_DMA_activate DI0: Device_Idle: This state is entered when the device has completed the execution of a command protocol, a COMRESET protocol, a software reset protocol, or a queued command has been released. When in this state, the device is awaiting a command. If queuing is supported, the device may be waiting to acquire data or establish buffer space to complete a queued command Transition DI0:1: When the device receives a FIS from the Transport layer, the device shall transition to the DI1: Check_FIS state. * Transition DI0:2: When the device is ready to complete the data transfer for a queued command, the device shall transition to the DI4: Set_service state. * Transition DI0:3: When the device is ready to receive the data for a WRITE FPDMA QUEUED command, the device shall transition to the DFPDMAQ4: DataPhasePreWriteSetup state. This condition also applies for the case where non-zero buffer offsets are used to complete a previous partial data transfer. * Transition DI0:4: When the device is ready to transmit the data for a READ FPDMA QUEUED command, the device shall transition to the DFPDMAQ3: DataPhaseReadSetup state. This condition also applies for the case where non-zero buffer offsets are used to complete a previous partial data transfer. * Transition DI0:5: When the device has successfully completed a FPDMA QUEUED or a NCQ QUEUE MANAGEMENT command, the device shall transition to the DFPDMAQ10: SendStatus state. Serial ATA Revision 3.0 Gold Revision page 434 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization * Transition DI0:6: When the device has encountered an error in a FPDMA QUEUED or a NCQ QUEUE MANAGEMENT command, the device shall transition to the DFPDMAQ11: ERROR state. Transition DI0:7: If Asynchronous Notification is enabled and an event requiring notification of the host has occurred and the NotifyPending variable is cleared to zero and FIS receipt not indicated, the device shall transition to the AN0: Notify_host state. DI1: Check_FIS state: This state is entered when the device receives a FIS from the Transport layer. When in this state, the device shall check the FIS type. Transition DI1:1: If the FIS type is a Register FIS, the C bit in the FIS is cleared to zero, and the SRST bit in the FIS is set to one, the device shall transition to the DSR0: Software_reset_asserted state. Transition DI1:2: If the FIS type is a Register FIS, the C bit in the FIS is cleared to zero, and the SRST bit in the FIS is cleared to zero, the device shall transition to the DI0: Device_idle state. Transition DI1:3: If the FIS type is a Register FIS and the C bit in the FIS is set to one, the device shall transition to the DI2: Check_command state. Transition DI1:4: If the FIS type is a First Party DMA Setup FIS, the device shall inform the Transport layer of the reception of the First Party DMA Setup FIS, and transition to the DI0: Device_idle state. Transition DI1:5: For any other FIS, the device shall transition to the DI0: Device_idle state. DI2: Check_command state: This state is entered when the device recognizes that the received Register FIS contains a new command. NOTE: This state shows transitions for all commands. If a device does not implement any particular command, then transition DI2:11 to state DI3:No_command shall be made. When in this state, the device shall check the command protocol required by the received command and clears NotifyPending to zero if asynchronous notification is supported. Clearing NotifyPending to zero allows future asynchronous notification messages to be sent to the host. Transition DI2:1: When the received command is a non-data transfer command, the device shall transition to the DND0: Non-data state. Transition DI2:2: When the received command is a PIO data-in command, the device shall transition to the DPIOI0: PIO_in state. Transition DI2:3: When the received command is a PIO data-out command, the device shall transition to the DPIOO0: PIO_out state. Transition DI2:4: When the received command is a READ DMA command, the device shall transition to the DDMAI0: DMA_in state. Transition DI2:5: When the received command is a WRITE DMA command, the device shall transition to the DDMAO0: DMA_out state. Transition DI2:6: When the received command is a PACKET command, the device shall transition to the DPKT0: PACKET state. Serial ATA Revision 3.0 Gold Revision page 435 of 663 * Transition DI2:7: When the received command is a READ DMA QUEUED command, the device shall transition to the DDMAQI0: DMA_queued_in state. * Transition DI2:8: When the received command is a WRITE DMA QUEUED command, the device shall transition to the DDMAQO0: DMA_queued_out state. Transition DI2:9: When the received command is an EXECUTE DEVICE DIAGNOSTICS command, the device shall transition to the DEDD0: Execute_device_diag state. Transition DI2:10: When the received command is an RESET DEVICE command, the device shall transition to the DDR0: Device_reset state. Transition DI2:11: When the received command is not implemented by the device, the device shall transition to the DI3: No_command state. * Transition DI2:12: When the received command is a SERVICE command, the device shall transition to the DI5: Service_test state. * Transition DI2:13: When the received command is a READ FPDMA QUEUED command protocol, the device shall transition to the DFPDMAQ1: AddCommandToQueue state. * Transition DI2:14: When the received command is a WRITE FPDMA QUEUED command protocol, the device shall transition to the DFPDMAQ1: AddCommandToQueue state. * Transition DI2:15: When the received command is a NCQ QUEUE MANAGEMENT command protocol, the device shall transition to the DFPDMAQ1: AddCommandToQueue state. * Transition DI2:16: When the received command is a not a READ FPDMA QUEUED; and not a WRITE FPDMA QUEUED; and not a NCQ QUEUE MANAGEMENT; and not a DEVICE RESET; and there are native queued command(s) outstanding, an error has occurred and the device shall transition to the DFPDMAQ12: BrokenHost_ClearBusy state. DI3: No_command state: This state is entered when the device recognizes that the received command is not implemented by the device. When in this state, the device shall request that the Transport layer transmit a Register FIS with register content as described in the command description in the ATA8-ACS standard and the Interrupt bit set to one. Transition DI2:1: When the Transport layer has transmitted the Register FIS, the device shall transition to the DI0: Device_idle state. * DI4: Set_service state: This state is entered when the ready to complete the data transfer for a queued command. When in this state, the device shall request that the Transport layer transmit a Set Device Bits FIS with the SERV bit set in the Status register and with all other bits in the Error and Status fields the same as the current contents of the respective registers, and the Interrupt bit set to one. Transition DI4:1: When the Transport layer has transmitted the Set Device Bits FIS, the device shall transition to the DI0: Device_idle state. Serial ATA Revision 3.0 Gold Revision page 436 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization * DI5: Service_test state: This state is entered when the SERVICE command has been received. When in this state, the device shall determine the type of command that the device has requested service to complete. The PACKET command using the PIO protocol provides its own register update to set DRQ and send the command tag, but other queued commands require a Register FIS. Transition DI5:1: When the command to be serviced is a PIO data-in or PIO data-out command, the device shall transition to the DI7: Service_decode state. Transition DI5:2: When the command to be serviced is neither a PIO data-in nor a PIO data-out command, the device shall transition to the DI6: Service_send_tag state. * DI6: Service_send_tag state: This state is entered when the SERVICE command has been received and sending a Register Device to Host FIS is necessary for the command being serviced. When in this state, the device shall request that the Transport layer transmit a Register FIS with register contents, including the desired command tag, as described in the command description of the ATA8-ACS standard for the command being serviced. Transition DI6:1: When the Transport layer has transmitted the Register FIS, the device shall transition to theDI7: Service_decode state. * DI7: Service_decode state: This state is entered when a Register FIS has been transmitted, if necessary to send the register contents, including the desired command tag, in response to a SERVICE command. When in this state, the device shall again determine the type of command that the device has requested service to complete, and branch to that command's data transfer and completion. Transition DI7:1: When the command to be serviced is a PIO data-in command, the device shall transition to the DPKT4: PACKET_PIO_in state. Transition DI7:2: When the command to be serviced is a PIO data-out command, the device shall transition to the DPKT6: PACKET_PIO_out state. Transition DI7:3: When the command to be serviced is a DMA data-in command, the device shall transition to the DPKT9: PACKET_DMA_in state. Transition DI7:4: When the command to be serviced is a DMA data-out command, the device shall transition to the DPKT11: PACKET_DMA_out state. Transition DI7:5: When the command to be serviced is a READ DMA QUEUED command, the device shall transition to the DDMAQI1: Send_data state. Transition DI7:6: When the command to be serviced is a WRITE DMA QUEUED command, the device shall transition to the DDMAQO1: Send_DMA_activate state. 11.3 Software reset protocol When the host sends a Register FIS with a one in the SRST bit position of the Device Control register byte, regardless of the device power management mode (e.g. SLEEP, STANDBY), the device shall execute the software reset protocol. Serial ATA Revision 3.0 Gold Revision page 437 of 663 DSR0: Begin initialization and diagnostic execution. Software_reset_asserted 1. Software reset negated. DSR1: Execute_diagnostics 2. Software reset asserted. DSR0: Software_reset_ asserted DSR1: Execute_diagnostics Complete Initialization and diagnostics execution. 1. Initialization and diagnostics completed successfully. 2. Initialization completed and diagnostics failed. DSR2: Send_good_status DSR3: Send_bad_status DSR2: Send_good_status Request transmission of Register FIS with good status. 1. Register FIS transmitted. DI0: Device_idle DSR3: Send_bad_status Request transmission of Register FIS with bad status. 1. Register FIS transmitted. DI0: Device_idle DSR0: Software_reset_asserted: This state is entered when a Register FIS is received with the C bit in the FIS cleared to zero and the SRST bit set to one in the Device Control register. When in this state, the device begins its initialization and diagnostics execution and awaits the clearing of the SRST bit. Transition DSR0:1: When a Register FIS is received with the C bit in the FIS cleared to zero and the SRST bit cleared to zero in the Device Control register, the device shall transition to the DSR1: Execute_diagnostics state. Transition DSR0:2: If a Register FIS is received with the C bit in the FIS set to one, or the SRST bit set to one in the Device Control register, the device shall transition to the DSR0: Software_reset_asserted state. DSR1: Execute_diagnostics: This state is entered when a Register FIS is received with the C bit in the FIS cleared to zero and the SRST bit cleared to zero in the Device Control register. When in this state, the device completes initialization and execution of its diagnostics. Transition DSR1:1: When the device has been initialized and the diagnostics successfully completed, the device shall transition to the DSR2: Send_good_status state. Transition DSR1:2: When the device has been initialized and the diagnostics failed, the device shall transition to the DSR3: Send_bad_status state. DSR2: Send_good_status: This state is entered when the device has been initialized and the diagnostics successfully completed. Serial ATA Revision 3.0 Gold Revision page 438 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization When in this state, the device requests that the Transport layer transmit a Register FIS to the host. If the device does not implement the PACKET command feature set the register content shall be: Count(7:0) 01h LBA(7:0) 01h LBA(15:8) 00h LBA(23:16 00h Device na Error 01h Status 00h-70h (see note) NOTE Setting of bits [6:4] in the Status register are device specific. If the device implements the PACKET command feature set, the register content shall be: Count(7:0) 01h LBA(7:0) 01h LBA(15:8) 14h LBA(23:16 EBh Device na Error 01h Status 00h Transition DSR2:1: When the Transport layer indicates that the Register FIS has been transmitted, the device shall transition to the DI0: Device_Idle state. DSR3: Send_bad_status: This state is entered when the device has been initialized and the diagnostics failed. When in this state, the device requests that the Transport layer transmit a Register FIS to the host. If the device does not implement the PACKET command feature set the register content shall be: Count(7:0) 01h LBA(7:0) 01h LBA(15:8) 00h LBA(23:16 00h Device na Error 00h, 02h-7Fh Status 00h-70h (see note) NOTE Setting of bits [6:4] in the Status register are device specific. If the device implements the PACKET command feature set, the register content shall be: Count(7:0) LBA(7:0) LBA(15:8) LBA(23:16 Device Error Status 01h 01h 14h EBh na 00h, 02h-7Fh 00h Serial ATA Revision 3.0 Gold Revision page 439 of 663 Transition DSR3:1: When the Transport layer indicates that the Register FIS has been transmitted, the device shall transition to the DI0: Device_Idle state. 11.4 EXECUTE DEVICE DIAGNOSTIC command protocol If the host sends COMRESET before the device has completed executing the EXECUTE DEVICE DIAGNOSTIC protocol, then the device shall immediately start executing the COMRESET protocol form the beginning. If the host asserts SRST in the Device Control register before the device has completed executing the EXECUTE DEVICE DIAGNOSTIC protocol, then the device shall immediately start executing its software reset protocol from the beginning. DEDD0: Execute diagnostics. Execute_device_diag 1. Diagnostics completed successfully. 2. Diagnostics failed. DEDD1: Send_good_status DEDD2: Send_bad_status DEDD1: Send_good_status Request transmission of Register FIS with good status. 1. Register FIS transmitted. DI0: Device_idle DEDD2: Send_bad_status Request transmission of Register FIS with bad status. 1. Register FIS transmitted. DI0: Device_idle DEDD0: Execute_device_diag: This state is entered when an EXECUTE DEVICE DIAGNOSTIC command is received. When in this state, the device executes its diagnostics. Transition DEDD0:1: When the device successfully completed the diagnostics, the device shall transition to the DEDD1: Send_good_status state. Transition DEDD1:2: When the device has failed the diagnostics, the device shall transition to the DEDD2: Send_bad_status state. DEDD1: Send_good_status: This state is entered when the device has successfully completed the diagnostics. When in this state, the device shall request that the Transport layer transmit a Register FIS to the host, with the Interrupt bit set to one. If the device does not implement the PACKET command feature set the register content shall be: Serial ATA Revision 3.0 Gold Revision page 440 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Count(7:0) 01h LBA(7:0) 01h LBA(15:8) 00h LBA(23:16 00h Device na Error 01h Status 00h-70h (see note) NOTE Setting of bits [6:4] in the Status register are device specific. If the device implements the PACKET command feature set, the register content shall be: Count(7:0) 01h LBA(7:0) 01h LBA(15:8) 14h LBA(23:16 EBh Device na Error 01h Status 00h Transition DEDD1:1: When the Transport layer indicates that the Register FIS has been transmitted, the device shall transition to the DI0: Device_Idle state. DEDD2: Send_bad_status: This state is entered when the device has been initialized and the diagnostics failed. When in this state, the device shall request that the Transport layer transmit a Register FIS to the host, with the Interrupt bit set to one. If the device does not implement the PACKET command feature set the register content shall be: Count(7:0) 01h LBA(7:0) 01h LBA(15:8) 00h LBA(23:16 00h Device na Error 00h, 02h-7Fh Status 00h-70h (see note) NOTE Setting of bits [6:4] in the Status register are device specific. If the device implements the PACKET command feature set, the register content shall be: Count(7:0) LBA(7:0) LBA(15:8) LBA(23:16 Device Error Status 01h 01h 14h EBh na 00h, 02h-7Fh 00h Transition DEDD2:1: When the Transport layer indicates that the Register FIS has been transmitted, the device shall transition to the DI0: Device_Idle state. Serial ATA Revision 3.0 Gold Revision page 441 of 663 11.5 DEVICE RESET command protocol If the host sends COMRESET before the device has completed executing the DEVICE RESET protocol, then the device shall immediately start executing the COMRESET protocol from the beginning. If the host asserts SRST in the Device Control register before the device has completed executing the DEVICE RESET protocol, then the device shall immediately start executing its software reset protocol from the beginning. DDR0: Device_reset Stop execution and background activity. 1. Activity ceased. DDR1: Send_good_status DDR1: Send_good_status Request transmission of Register – Device to Host FIS with good status. 1. Register FIS transmitted. DI0: Device_idle DDR0: Device_reset: This state is entered when an DEVICE RESET command is received. When in this state, the device stops any execution or activity in progress. Transition DDR0:1: When the device has ceased any execution or activity and has completed its internal diagnostics, the device shall transition to the DDR1: Send_good_status state. DDR1: Send_good_status: This state is entered when the device has been initialized and the diagnostics successfully completed. When in this state, the device requests that the Transport layer transmit a Register – Device to Host FIS to the host. The register content shall be: Count(7:0) 01h LBA(7:0) 01h LBA(15:8) 14h LBA(23:16 EBh Device na Error 01h Status 00h Transition DDR1:1: When the Transport layer indicates that the Register – Device to Host FIS has been transmitted, the device shall transition to the DI0: Device_Idle state. 11.6 Non-data command protocol Execution of this class of command involves no data transfer. See the NOP command description and the SLEEP command description for additional protocol requirements. Serial ATA Revision 3.0 Gold Revision page 442 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization DND0: Non-data Execute Non-data command. 1. Command execution complete. DND1: Send_status Request transmission of a Register FIS. 1. FIS transmission complete. DND1: Send_status DI0: Device_idle DND0: Non-data State: This state is entered when a received command is a non-data command. When in this state, the device shall execute the requested command if supported. Transition DND0: 1: When command execution completes, the device shall transition to the DND1: Send_status state. DND1: Send_status State: This state is entered when the execution of the non-data command has been completed. When in this state, the device shall request that the Transport layer transmit a Register FIS with register content as described in the command description in the ATA8-ACS standard and the Interrupt bit set to one. Transition DND1:1: When the FIS has been transmitted, then the device shall transition to the DI0: Device_idle state. 11.7 PIO data-in command protocol Execution of this class of command includes the PIO transfer of one or more blocks of data from the device to the host. DPIOI0: PIO_in Prepare a DRQ data block for transfer to the host. 1. DRQ data block ready to transfer and no error encountered. 2. Error encountered during command execution. DPIOI1: Send_PIO_setup DPIOI3: Error_status DPIOI1: Send_PIO_setup Request transmission of a PIO Setup FIS to host. 1. PIO Setup FIS transmitted. DPIOI2: Transmit_data DPIOI2: Transmit_data Request transmission of a Data FIS to host. 1. Data FIS transmitted, no more data transfer required for this command. DI0: Device_idle 2. Data FIS transmitted, more data transfer required for this command, or 2048 Dwords transmitted. DPIOI0: PIO_in DPIOI3: Error_status Request transmission of a Register - Device to Host FIS. 1. FIS transmission complete. DI0: Device_idle Serial ATA Revision 3.0 Gold Revision page 443 of 663 DPIOI0: PIO_in State: This state is entered when the device receives a PIO data-in command or the transmission of one or more additional DRQ data blocks is required to complete the command. When in this state, device shall prepare a DRQ data block for transfer to the host. Transition DPIOI0:1: When the device has a DRQ data block ready to transfer and no error was encountered, the device shall transition to the DPIOI1: Send_PIO_setup state. Transition DPIOI0:2: When the device has encountered an error during command execution, the device shall transition to the DPIOI3: Error_status state. DPIOI1: Send_PIO_setup: This state is entered when the device is ready to transmit a DRQ data block to the host. When in this state, the device shall request that the Transport layer transmit a PIO Setup FIS. The initial status shall have BSY bit cleared to zero and DRQ bit set to one and with register content as described in the command description in the ATA8-ACS standard. The Interrupt bit shall be set. If this is the last DRQ data block requested by the command, the ending status shall have BSY bit cleared to zero and DRQ bit cleared to zero. If this is not the last data block requested by the command, the ending status shall have BSY bit set to one and DRQ bit cleared to zero. Transition DPIOI1:1: When the PIO Setup FIS has been transferred, the device shall transition to the DPIOI2: Transmit_data state. DPIOI2: Transmit_data: This state is entered when the device has transmitted a PIO Setup FIS to the host. When in this state, the device shall request that the Transport layer transmit a Data FIS containing the DRQ data block. Transition DPIOI2:1: When the Data FIS has been transferred and all data requested by this command have been transferred, the device shall transition to the DI0: Device_idle. Transition DPIOI2:2: When the Data FIS has been transferred but all data requested by this command has not been transferred, or the 2048 Dword transfer limit has been reached, then the device shall transition to the DPIOI0: PIO_in state. DPIOI3: Error_status: This state is entered when the device has encountered an error that causes the command to abort before completing the transfer of the requested data. When in this state, the device shall request that the Transport layer transmit a Register FIS with register content as described in the command description in the ATA8-ACS standard and the Interrupt bit set to one. In addition to the ATA8-ACS requirements, the device may set bit 7 of the error field in the FIS to one if a CRC error was encountered in transmission of a previous FIS for this command. Transition DPIOI3:1: When the FIS has been transmitted, the device shall transition to the DI0: Device_idle state. Serial ATA Revision 3.0 Gold Revision page 444 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 11.8 PIO data-out command protocol Execution of this class of command includes the PIO transfer of one or more blocks of data from the host to the device. DPIOO0: PIO_out Prepare to receive DRQ data block transfer from the host. 1. Ready to receive DRQ data block transfer. 2. All DRQ data blocks received or command aborted due to error. DPIOO1: Send_PIO_setup DPIOO3: Send_status DPIOO1: Send_PIO_setup Request transmission of a PIO Setup FIS to host. 1. PIO Setup FIS transmitted. DPIOO2: Receive_data DPIOO2: Receive_data Receive Data FIS from the Transport layer. 1. Data FIS received. DPIOO0: PIO_out DPIOO3: Send_status Request transmission of a Register - Device to Host FIS. 1. FIS transmission complete. DI0: Device_idle DPIOO0: PIO_out State: This state is entered when the device receives a PIO data-out command or the receipt of one or more DRQ data blocks is required to complete this command. When in this state, device shall prepare to receive a DRQ data block transfer from the host. Transition DPIOO0:1: When the device is ready to receive a DRQ data block, the device shall transition to the DPIOO1: Send_PIO_setup state. Transition DPIOO0:2: When the device has received all DRQ data blocks requested by this command or the device has encountered an error that causes the command to abort before completing the transfer of the requested data, then the device shall transition to the DPIOO3: Send_status state. DPIOO1: Send_PIO_setup: This state is entered when the device is ready to receive a DRQ data block from the host. When in this state, the device shall request that the Transport layer transmit a PIO Setup FIS. The initial status shall have BSY bit cleared to zero and DRQ bit set to one. If this is the first DRQ data block for this command, the Interrupt bit shall be cleared to zero. If this is not the first DRQ data block for this command, the Interrupt bit shall be set to one. The ending status shall have BSY bit set to one and DRQ bit cleared to zero. The byte count for the DRQ data block shall be indicated. Transition DPIOO1:1: When the PIO Setup FIS has been transferred, the device shall transition to the DPIOO2: Receive_data state. DPIOO2:Receive_data: This state is entered when the device has transmitted a PIO Setup FIS to the host. Serial ATA Revision 3.0 Gold Revision page 445 of 663 When in this state, the device shall receive the requested Data FIS from the Transport layer. Transition DPIOO2:1: When the Data FIS has been received, the device shall transition to the DPIOO0: PIO_out state. DPIOO3: Send_status: This state is entered when the device has received all DRQ data blocks requested by this command or the device has encountered an error that causes the command to abort before completing the transfer of the requested data. When in this state, the device shall request that the Transport layer transmit a Register FIS with register content as described in the command description in the ATA8-ACS standard and the Interrupt bit set to one. In addition to the ATA8-ACS requirements, the device may set bit 7 of the error field in the FIS to one if a CRC error was encountered in transmission of a previous FIS for this command. Transition DPIOO3:1: When the FIS has been transmitted, the device shall transition to the DI0: Device_idle state. 11.9 DMA data in command protocol Execution of this class of command includes the transfer of one or more blocks of data from the device to the host using DMA transfer. DDMAI0: DMA_in Prepare data for the transfer of a Data FIS. 1. Data for Data FIS ready to transfer. 2. Command completed or aborted due to error. DDMAI1: Send_data DDMAI2: Send_status DDMAI1: Send_data Request transmission of a Data FIS to host. 1. Data FIS transmitted. No more data transfer required for this command, or 2048 Dwords transmitted. DDMAI0: DMA_in DDMAI2: Send_status Request transmission of a Register FIS to host. 1. Register FIS transmitted. DI0: Device_idle DDMAI0: DMA_in State: This state is entered when the device receives a DMA data-in command or the transmission of one or more data FIS is required to complete the command. When in this state, device shall prepare the data for transfer of a data FIS to the host. Transition DDMAI0:1: When the device has the data ready to transfer a data FIS, the device shall transition to the DDMAI1: Send_data state. Transition DDMAI0:2: When the device has transferred all of the data requested by this command or has encountered an error that causes the command to abort before completing the transfer of the requested data, then the device shall transition to the DDMAI2: Send_status state. DDMAI1: Send_data: This state is entered when the device has the data ready to transfer a data FIS to the host. Serial ATA Revision 3.0 Gold Revision page 446 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization When in this state, the device shall request that the Transport layer transmit a data FIS containing the data. The device command layer shall request a Data FIS size of no more than 2048 Dwords . Transition DDMAI1:1: When the data FIS has been transferred, the device shall transition to the DDMAI0: DMA_in state. DDMAI2: Send_status: This state is entered when the device has transferred all of the data requested by the command or has encountered an error that causes the command to abort before completing the transfer of the requested data. When in this state, the device shall request that the Transport layer transmit a Register FIS with register content as described in the command description in the ATA8-ACS standard and the Interrupt bit set to one. Transition DDMAI2:1: When the FIS has been transmitted, the device shall transition to the DI0: Device_idle state. 11.10 DMA data out command protocol Execution of this class of command includes the transfer of one or more blocks of data from the host to the device using DMA transfer. A single interrupt is issued at the completion of the successful transfer of all data required by the command. DDMAO0: DMA_out Prepare to receive a Data FIS from the host. 1. Ready to receive Data FIS. 2. All data requested for this command received or command aborted due to error. DDMAO1: Send_DMA_activate DDMAO3: Send_status DDMAO1: Request transmission of a DMA Activate FIS to host. Send_DMA_activate 1. DMA Activate FIS transmitted. DDMAO2: Receive_data DDMAO2: Receive_data Receive Data FIS from the Transport layer. 1. Data FIS received. DDMAO0: DMA_out DDMAO3: Send_status Request transmission of a Register FIS to host. 1. Register FIS transmitted. DI0: Device_idle DDMAO0: DMA_out State: This state is entered when the device receives a DMA data-out command or the receipt of one or more Data FIS is required to complete this command. When in this state, device shall prepare to receive a Data FIS from the host. Transition DDMAO0:1: When the device is ready to receive a Data FIS, the device shall transition to the DDMAO1: Send_DMA_activate state. Serial ATA Revision 3.0 Gold Revision page 447 of 663 Transition DDMAO0:2: When the device has received all the data requested by this command or the device has encountered an error that causes the command to abort before completing the transfer of the requested data, then the device shall transition to the DDMAO3: Send_status state. DDMAO1: Send_DMA_activate: This state is entered when the device is ready to receive a Data FIS from the host. When in this state, the device shall request that the Transport layer transmit a DMA Activate FIS. Transition DDMAO1:1: When the DMA Activate FIS has been transferred, the device shall transition to the DDMAO2: Receive_data state. DDMAO2: Receive_data: This state is entered when the device transmitted a DMA Activate FIS to the host. When in this state, the device shall receive the requested Data FIS from the Transport layer. Transition DDMAO2:1: When the Data FIS has been received, the device shall transition to the DDMAO0: DMA_out state. DDMAO3: Send_status: This state is entered when the device has received all the data requested by this command or the device has encountered an error that causes the command to abort before completing the transfer of the requested data. When in this state, the device shall request that the Transport layer transmit a Register FIS with register content as described in the command description in the ATA8-ACS standard and the Interrupt bit set to one. Transition DDMAO3:1: When the FIS has been transmitted, the device shall transition to the DI0: Device_idle state. 11.11 PACKET protocol States marked with an * are only utilized when queuing is implemented DPKT0: PACKET Request transmission of a PIO Setup FIS. 1. FIS transmission complete. DPKT1: Receive_command DPKT1: Receive_command Receive Data FIS containing command packet. 1. FIS reception complete. DPKT2: Check_command Serial ATA Revision 3.0 Gold Revision page 448 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization DPKT2: Check_command Determine the protocol required for the received command. 1. Non-data command. 2. PIO data-in command. 3. PIO data-out command. 4. DMA data-in command 5. DMA data-out command DPKT3: PACKET_non-data DPKT4: PACKET_PIO_in DPKT6: PACKET_PIO_out DPKT9: PACKET_DMA_in DPKT11: PACKET_DMA_out DPKT3: PACKET_non-data Execute Non-data command. 1. Command execution complete. DPKT14: Send_status DPKT4: PACKET_PIO_in Prepare a DRQ data block for transfer to the host. 1. DRQ data block ready to transfer. 2. Transfer complete or command aborted due to error. 3. * DRQ block is not ready for immediate transfer DPKT4a: PIO_in_setup DPKT14: Send_status DPKT15: Release DPKT4a: PIO_in_setup Request transmission of a PIO Setup FIS to host. 1. PIO Setup FIS transmitted. DPKT5: Send_PIO_data DPKT5: Send_PIO_data Request transmission of a Data FIS to host. 1. Data FIS transmitted. DPKT4: PACKET_PIO_in DPKT6: PACKET_PIO_out Prepare to receive DRQ data block from the host. 1. Ready to receive DRQ data block transfer. 2. All DRQ data blocks received or command aborted due to error. 3. * Not ready to accept DRQ block immediately. DPKT7: PIO_out_setup DPKT14: Send_status DPKT15: Release DPKT7: PIO_out_setup Request transmission of a PIO Setup FIS to host. 1. PIO Setup FIS transmitted. DPKT8: Receive_PIO_data DPKT8: Receive_PIO_data Receive Data FIS from the Transport layer. 1. Data FIS received. DPKT6: PACKET_PIO_out Serial ATA Revision 3.0 Gold Revision page 449 of 663 DPKT9: PACKET_DMA_in Prepare data for the transfer of a Data FIS. 1. Data for Data FIS ready to transfer. 2. Command completed or aborted due to error. 3. * Data is not ready for immediate transfer. DPKT10: Send_DMA_data DPKT14: Send_status DPKT15: Release DPKT10: Send_DMA_data Request transmission of a Data FIS to host. 1. Data FIS transmitted. No more data transfer required for this command, or 2048 Dwords transmitted. DPKT9: PACKET_DMA_IN DPKT11: Prepare to receive a Data FIS from the host. PACKET_DMA_out 1. Ready to receive Data FIS. DPKT12: Send_DMA_activate 2. All data requested for this command received or DPKT14: command aborted due to error. Send_status 3. * Not ready for immediate transfer. DPKT15: Release DPKT12: Request transmission of a DMA Activate FIS to host. Send_DMA_activate 1. DMA Activate FIS transmitted. DPKT13: Receive_DMA_data DPKT13: Receive Data FIS from the Transport layer. Receive_DMA_data 1. Data FIS received. DPKT11: PACKET_DMA_out DPKT14: Send_status Request transmission of a Register FIS. 1. FIS transmission complete. DI0: Device_idle * DPKT15: Release Request transmission of a Register FIS. 1. FIS transmission complete. DI0: Device_idle DPKT0: PACKET: This state is entered when the device receives a PACKET command. When in this state, the device shall request that the Transport layer transmit a PIO Setup FIS to acquire the command packet associated with this command. The initial status shall have BSY bit cleared to zero and DRQ bit set to one. The Interrupt bit shall be cleared to zero. The ending status shall have BSY bit set to one and DRQ bit cleared to zero. The byte count for the DRQ data block shall be indicated. Transition DPKT0:1: When the PIO Setup FIS has been transferred, the device shall transition to the DPKT1: Receive_command state. DPKT1: Receive_command: This state is entered when the device transmitted a PIO Setup FIS to the host to get the command packet. When in this state, the device shall receive the requested Data FIS from the Transport layer. Serial ATA Revision 3.0 Gold Revision page 450 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transition DPKT1:1: When the Data FIS has been received, the device shall transition to the DPKT2: Check_command state. DPKT2: Check_command: This state is entered when the Data FIS containing the command packet has been received. When in this state, the device shall determine the protocol for the command contained in the command packet. Transition DPKT2:1: When the command is a non-data transfer command, the device shall transition to the DPKT3: PACKET_non-data state. Transition DPKT2:2: When the command is a PIO data-in transfer command, the device shall transition to the DPKT4: PACKET_PIO_in state. Transition DPKT2:3: When the command is a PIO data-out transfer command, the device shall transition to the DPKT6: PACKET_PIO_out state. Transition DPKT2:4: When the command is a DMA data-in transfer command, the device shall transition to the DP9: PACKET_DMA_in state. Transition DPKT2:5: When the command is a DMA data-out transfer command, the device shall transition to the DPKT11: PACKET_DMA_out state. DPKT3: PACKET_non-data State: This state is entered when a received command is a non-data command. When in this state, the device shall execute the requested command. Transition DPKT3:1: When command execution completes, the device shall transition to the DPKT14: Send_status state. DPKT4: PACKET_PIO_in State: This state is entered when the device receives a PIO data-in command or the transmission of one or more DRQ data blocks is required to complete the command. When in this state, device shall prepare a DRQ data block for transfer to the host. Transition DPKT4:1: When the device has a DRQ data block ready to transfer, the device shall transition to the DPKT4a: PIO_in_setup. Transition DPKT4:2: When all of the data requested by this command has been transferred or the device has encountered an error that causes the command to abort before completing the transfer of the requested data, then the device shall transition to the DPKT14: Send_status state. * Transition DPKT4:3: When the device supports overlap and queuing and does not have a DRQ data block ready to transfer immediately, the device shall transition to the DPKT15: Release state. DPKT4a: PIO_in_setup: This state is entered when the device is ready to transfer a DRQ block to the host. When in this state, the device shall request that the Transport layer transmit a PIO Setup FIS. The initial status shall have BSY bit cleared to zero and DRQ bit set to one. The Interrupt bit shall Serial ATA Revision 3.0 Gold Revision page 451 of 663 be set to one. The ending status shall have BSY bit set to one and DRQ bit cleared to zero. The byte count for the DRQ data block shall be indicated. Transition DPKT4a:1: When the PIO Setup FIS has been transferred, the device shall transition to the DPKT5:Send_PIO_data state. DPKT5:Send_PIO_data: This state is entered when the device is ready to transfer a DRQ data block to the host. When in this state, the device shall request that the Transport layer transmit a Data FIS containing the DRQ data block. Transition DPKT5:1: When the Data FIS has been transferred, the device shall transition to the DPKT4: PACKET_PIO_in state. DPKT6: PACKET_PIO_out State: This state is entered when the device receives a PIO data-out command or the receipt of one or more DRQ data blocks is required to complete the command. When in this state, device shall prepare to receive a DRQ data block transfer from the host. Transition DPKT6:1: When the device is ready to receive a DRQ data block transfer, the device shall transition to the DPKT7: PIO_out_setup state. Transition DPKT6:2: When the device has received all DRQ data blocks requested by this command or the device has encountered an error that causes the command to abort before completing the transfer of the requested data, then the device shall transition to the DPKT14: Send_status state. * Transition DPKT6:3: When the device supports overlap and queuing and is not in a state in which it can accept a DRQ data block immediately, the device shall transition to the DPKT15: Release state. DPKT7: PIO_out_setup: This state is entered when the device is ready to receive a DRQ data block from the host. When in this state, the device shall request that the Transport layer transmit a PIO Setup FIS. The initial status shall have BSY bit cleared to zero and DRQ bit set to one. The Interrupt bit shall be set to one. The ending status shall have BSY bit set to one and DRQ bit cleared to zero. The byte count for the DRQ data block shall be indicated. Transition DPKT7:1: When the PIO Setup FIS has been transferred, the device shall transition to the DPKT8: Receive_PIO_data state. DPKT8: Receive_PIO_data: This state is entered when the device transmitted a PIO Setup FIS to the host. When in this state, the device shall receive the requested Data FIS from the Transport layer. Transition DPKT8:1: When the Data FIS has been received, the device shall transition to the DPKT6: PACKET_PIO_out state. DPKT9: PACKET_DMA_in State: This state is entered when the device receives a DMA data-in command or the transmission of one or more Data FIS is required to complete the command. Serial ATA Revision 3.0 Gold Revision page 452 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization When in this state, device shall prepare the data for transfer of a Data FIS to the host. Transition DPKT9:1: When the device has the data ready to transfer a Data FIS, the device shall transition to the DPKT10: Send_DMA_data state. Transition DPKT9:2: When the device has transferred all of the data requested by this command or has encountered an error that causes the command to abort before completing the transfer of the requested data, then the device shall transition to the DPKT14: Send_status state. * Transition DPKT9:3: When the device supports overlap and queuing and does not have data ready to transfer immediately, the device shall transition to the DPKT15: Release state. DPKT10: Send_DMA_data: This state is entered when the device has the data ready to transfer a Data FIS to the host. When in this state, the device shall request that the Transport layer transmit a Data FIS containing the data. Transition DPKT10:1: When the Data FIS has been transferred, the device shall transition to the DPKT9: PACKET_DMA_in state. The device command layer shall request a data FIS size of no more than 2048 Dwords. DPKT11: PACKET_DMA_out State: This state is entered when the device receives a DMA data-out command or the receipt of one or more Data FIS is required to complete the command. When in this state, device shall prepare to receive a Data FIS from the host. Transition DPKT11:1: When the device is ready to receive a Data FIS, the device shall transition to the DPKT12: Send_DMA_activate state. Transition DPKT11:2: When the device has received all the data requested by this command or the device has encountered an error that causes the command to abort before completing the transfer of the requested data, then the device shall transition to the DPKT14: Send_status state. * Transition DPKT11:3: When the device supports overlap and queuing and is not in a state which it can accept a Data FIS immediately, the device shall transition to the DPKT15: Release state. DPKT12: Send_DMA_activate: This state is entered when the device is ready to receive a Data FIS from the host. When in this state, the device shall request that the Transport layer transmit a DMA Activate FIS. Transition DPKT12:1: When the DMA Activate FIS has been transferred, the device shall transition to the DPKT13: Receive_DMA_data state. DPKT13: Receive_DMA_data: This state is entered when the device transmitted a DMA Activate FIS to the host. When in this state, the device shall receive the requested Data FIS from the Transport layer. Transition DPKT13:1: When the Data FIS has been received, the device shall transition to the DPKT11: PACKET_DMA_out state. Serial ATA Revision 3.0 Gold Revision page 453 of 663 DPKT14: Send_status: This state is entered when the device has received all the data requested by this command or the device has encountered an error that causes the command to abort before completing the transfer of the requested data. When in this state, the device shall request that the Transport layer transmit a Register FIS with register content as described in the command description in the ATA8-ACS standard and the Interrupt bit set to one. Transition DPKT14:1: When the FIS has been transmitted, then the device shall transition to the DI0: Device_idle state. * DPKT15: Release: This state is entered when the device is not able to do a data transfer immediately. When in this state, the device shall request that the Transport layer transmit a Register FIS with register content as described in the command description in the ATA8-ACS standard, with the REL bit set to one, and, if the bus release interrupt has been enabled by a previous Set Features Command, with the Interrupt bit set to one. Transition DPKT15:1: When the FIS has been transmitted, then the device shall transition to the DI0: Device_idle state. 11.12 READ DMA QUEUED command protocol Execution of this class of command includes the transfer of one or more blocks of data from the device to the host using DMA transfer. All data for the command may be transferred without a bus release between the command receipt and the data transfer. This command may bus release before transferring data. The host shall initialize the DMA controller prior to transferring data. When data transfer is begun, all data for the request shall be transferred without a bus release. DDMAQI0: Determine whether to transfer or release. DMA_queued_in 1. Data for Data FIS ready to transfer. 2. Command aborted due to error. 3. Bus release DDMAQI1: Send_data DDMAQI3: Send_status DDMAQI4: Release DDMAQI1: Send_data Request transmission of a Data FIS to host. 1. Data FIS transmitted. No more data transfer required for this command, or 2048 Dwords transmitted. DDMAQI2: Prepare_data DDMAQI2: Prepare_data 1. Data ready. Prepare data for the next Data FIS. 2. Command complete or aborted due to error. DDMAQI1: Send _data DDMAQI3: Send_status DDMAQI3: Send_status Request transmission of a Register FIS to host. 1. Register FIS transmitted. DI0: Device_idle Serial ATA Revision 3.0 Gold Revision page 454 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization DDMAQI4: Release Request transmission of a Register FIS to host. 1. Register FIS transmitted. DI0: Device_idle DDMAQI0: DMA_queued_in State: This state is entered when the device receives a READ DMA QUEUED command. When in this state, device shall determine if the requested data is ready to transfer to the host. Transition DDMAQI0:1: When the device has the requested data ready to transfer a Data FIS immediately, the device shall transition to the DDMAQI1: Send_data state. Transition DDMAQI0:2: When the device has encountered an error that causes the command to abort before completing the transfer of the requested data, the device shall transition to the DDMAQI3: Send_status state. Transition DDMAQI0:3: When the device does not have the requested data ready to transfer a Data FIS immediately, the device shall transition to the DDMAQI4: Release state. DDMAQI1: Send_data: This state is entered when the device has the data ready to transfer a Data FIS to the host. When in this state, the device shall request that the Transport layer transmit a Data FIS containing the data. Transition DDMAQI1:1: When the Data FIS has been transferred, the device shall transition to the DDMAQI2: Prepare_data state. The device command layer shall request a Data FIS size of no more than 2048 Dwords . DDMAQI2: Prepare_data: This state is entered when the device has completed the transfer a Data FIS to the host. When in this state, the device shall prepare the data for the next Data FIS. Transition DDMAQI2:1: When data is ready for the Data FIS, the device shall transition to the DDMAQI1: Send_data state. Transition DDMAQI2:2: When all data requested for the command has been transmitted or an error has been encountered that causes the command to abort before completing the transfer of the requested data, the device shall transition to the DDMAQI3: Send_status state. DDMAQI3: Send_status: This state is entered when the device has transferred all of the data requested by the command or has encountered an error that causes the command to abort before completing the transfer of the requested data. When in this state, the device shall request that the Transport layer transmit a Register FIS with register content as described in the command description in the ATA8-ACS standard and the Interrupt bit set to one. Transition DDMAQI3:1: When the FIS has been transmitted, the device shall transition to the DI0: Device_idle state. Serial ATA Revision 3.0 Gold Revision page 455 of 663 DDMAQI4: Release: This state is entered when the device does not have the requested data available for immediate transfer. When in this state, the device shall request that the Transport layer transmit a Register FIS with the REL bit set to one, with register content as described in the command description in the ATA8-ACS standard, and, if the bus release interrupt has been enabled by a previous Set Features Command, with the Interrupt bit set to one. Transition DDMAQI4:1: When the FIS has been transmitted, then the device shall transition to the DI0: Device_idle state. 11.13 WRITE DMA QUEUED command protocol Execution of this class of command includes the transfer of one or more blocks of data from the device to the host using DMA transfer. All data for the command may be transferred without a bus release between the command receipt and the data transfer. This command may bus release before transferring data. The host shall initialize the DMA controller prior to transferring data. When data transfer is begun, all data for the request shall be transferred without a bus release. DDMAQO0: DMA- Determine whether to transfer or release. queued_out 1. Ready to accept Data FIS 2. Command due to error. 3. Bus release DDMAQO1: Send_DMA_activate DDMAQO4: Send_status DDMAQO5: Release DDMAQO1: Request transmission of a DMA Activate FIS to host. Send_DMA_activate 1. DMA Activate FIS transmitted. DDMAQO2: Receive_data DDMAQO2: Receive_data Receive Data FIS from the Transport layer. 1. Data FIS received. DDMAQO3: Prepare_data_buffer DDMAQO3: Prepare to receive the next Data FIS. Prepare_data_buffer 1. Ready to receive. 2. Command complete or aborted due to error. DDMAQO1: Send DMA_activate DDMAQO4: Send_status DDMAQO4: Send_status Request transmission of a Register FIS to host. 1. Register FIS transmitted. DI0: Device_idle DDMAQO5: Release Request transmission of a Register FIS to host. 1. Register FIS transmitted. DI0: Device_idle Serial ATA Revision 3.0 Gold Revision page 456 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization DDMAQO0: DMA_queued_out State: This state is entered when the device receives a WRITE DMA QUEUED command. When in this state, device shall determine if it is ready to accept the requested data from the host. Transition DDMAQO0: 1: When the device is ready to receive a Data FIS immediately, the device shall transition to the DDMAQO1: Send_DMA_activate state. Transition DDMAQO0:2: When the device has encountered an error that causes the command to abort before completing the transfer of the requested data, the device shall transition to the DDMAQO4: Send_status state. Transition DDMAQO0:3: When the device is not ready to receive a Data FIS immediately, the device shall transition to the DDMAQO5: Release state. DDMAQO1:Send_DMA_activate: This state is entered when the device is ready to receive a Data FIS from the host. When in this state, the device shall request that the Transport layer transmit a DMA Activate FIS. Transition DDMAQO1:1: When the DMA Activate FIS has been transferred, the device shall transition to the DDMAQO2: Receive_data state. DDMAQO2:Receive_data: This state is entered when the device transmitted a DMA Activate FIS to the host. When in this state, the device shall receive the requested Data FIS from the Transport layer. Transition DDMAQO2:1: When the Data FIS has been received, the device shall transition to the DDMAQO3: Prepare_data_buffer state. DDMAQO3: Prepare_data_buffer: This state is entered when the device has completed receiving a Data FIS from the host. When in this state, the device shall prepare for receipt of the next Data FIS. Transition DDMAQO3:1: When ready to receive the Data FIS, the device shall transition to the DDMAQO1: Send_DMA_activate state. Transition DDMAQO3:2: When all data requested for the command has been transmitted or an error has been encountered that causes the command to abort before completing the transfer of the requested data, the device shall transition to the DDMAQO4: Send_status state. DDMAQO4: Send_status: This state is entered when the device has transferred all of the data requested by the command or has encountered an error that causes the command to abort before completing the transfer of the requested data. When in this state, the device shall request that the Transport layer transmit a Register FIS with register content as described in the command description in the ATA8-ACS standard and the Interrupt bit set to one. Transition DDMAQO4:1: When the FIS has been transmitted, then the device shall transition to the DI0: Device_idle state. Serial ATA Revision 3.0 Gold Revision page 457 of 663 DDMAQO5: Release: This state is entered when the device cannot receive the requested data immediately. When in this state, the device shall request that the Transport layer transmit a Register FIS with REL set to one, with register content as described in the command description in the ATA8-ACS standard, and, if the bus release interrupt has been enabled by a previous Set Features Command, with the Interrupt bit set to one. Transition DDMAQO5:1: When the FIS has been transmitted, then the device shall transition to the DI0: Device_idle state. 11.14 FPDMA QUEUED command protocol This class includes: READ FPDMA QUEUED WRITE FPDMA QUEUED NCQ QUEUE MANAGEMENT DFPDMAQ1: Append command to internal device command queue and store AddCommandToQueue TAG value. 1. Device successfully en-queued the command DFPDMAQ2: ClearInterfaceBsy 2. Command malformed DFPDMAQ12: BrokenHost_ ClearBusy DFPDMAQ2: Transmit Register FIS with BSY bit cleared to zero and DRQ bit ClearInterfaceBsy cleared to zero and Interrupt bit cleared to zero to mark interface ready for the next command. 1. Register FIS transmission complete DI0: Device_idle DFPDMAQ3: Transmit a DMA Setup FIS to the host with the DMA Buffer DataPhaseReadSetup Identifier = TAG and D bit set to one (direction is device to host) and Interrupt bit cleared to zero 1. First Party DMA Setup FIS transmission complete DFPDMAQ8: DataXmitRead DFPDMAQ4: DataPhasePreWriteSetup 1. DMA Setup FIS Auto-Activate option supported and enabled 2. DMA Setup FIS Auto-Activate option not supported or not enabled DFPDMAQ5: DataPhase_ WriteSetup DFPDMAQ6: DataPhase_ OldWriteSetup Serial ATA Revision 3.0 Gold Revision page 458 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization DFPDMAQ5: Transmit a DMA Setup FIS to the host with the DMA Buffer DataPhase_WriteSetup Identifier = TAG and D bit cleared to zero (direction is host to device) and Auto-Activate bit set to one and Interrupt bit cleared to zero 1. DMA Setup FIS transmission complete DFPDMAQ9: DataXmitWrite DFPDMAQ6: Transmit a DMA Setup FIS to the host with the DMA Buffer DataPhase_OldWriteSetup Identifier = TAG and D bit cleared to zero (direction is host to device) and Auto-Activate bit cleared to zero and Interrupt bit I cleared to zero 1. DMA Setup FIS transmission complete DFPDMAQ7: DataPhase_ XmitActivate DFPDMAQ7: Transmit a DMA Activate FIS to the host DataPhase_XmitActivate 1. DMA Activate FIS transmission complete DFPDMAQ9: DataXmitWrite DFPDMAQ8: Transmit Data FIS to the host DataXmitRead 1. Transfer count for previous DMA Setup FIS not exhausted and no error encountered 2. Transfer count for previous DMA Setup FIS exhausted and data transfer for this command not complete and no error encountered1 3. Finished with data transfer for this command and no error encountered 4. Unrecoverable error has occurred DFPDMAQ8: DataXmitRead DI0: Device_idle DI0: Device_idle DI0: Device_idle NOTE: 1. This condition requires that non-zero buffer offsets be supported and enabled. The transition also applies if a device switches between multiple active commands and is performing partial data transfers for the multiple outstanding commands. DFPDMAQ9: Receive Data FIS from host DataXmitWrite 1. Transfer count for previous DMA Setup FIS not exhausted and no error encountered 2. Transfer count for previous DMA Setup FIS exhausted and data transfer for this command not complete and no error encountered1 3. Finished with data transfer for this command and no error encountered 4. Unrecoverable error has occurred DFPDMAQ7: DataPhase_ XmitActivate DI0: Device_idle DI0: Device_idle DI0: Device_idle NOTE: 1. This condition requires that non-zero buffer offsets be supported and enabled. The transition also applies if a device switches between multiple active commands and is performing partial data transfers for the multiple outstanding commands. Serial ATA Revision 3.0 Gold Revision page 459 of 663 DFPDMAQ10: SendStatus Transmit Set Device Bits FIS with ERR bit cleared to zero, Interrupt bit set to one, and bit n in ACT field set to one where n = TAG for each command TAG value that has completed since the last status return 1. Set Device Bits FIS transmission complete DI0: Device_idle DFPDMAQ11: ERROR Halt command processing and transmit Set Device Bits FIS to host with ERR bit in Status field set to one, Interrupt bit set to one, ATA error code set in Error field, and bits in ACT field cleared to zero for any outstanding queued commands and bits set to one for any successfully completed queued commands for which completion notification not yet delivered. 1. Set Device Bits FIS transmission complete DFPDMAQ13: WaitforClear DFPDMAQ12: Halt command processing and transmit Register FIS to host with BrokenHost_ClearBusy ERR bit in Status field set to one, Interrupt bit set to one, BSY bit cleared to zero, DRQ bit cleared to zero, and Error field = 04h. If error condition was due to reception of an Unload request and the device supports Unload when NCQ commands are outstanding, the device shall unload/park the heads. 1. Register FIS transmission complete DFPDMAQ13: WaitforClear DFPDMAQ13: WaitforClear Wait for host to either issue a command to read the Queued Error Log or issue SRST 1. READ LOG EXT command with Queued Error Log DFPDMAQ14: received SendQueue_ CleanACK 2. READ LOG DMA EXT command with Queued Error Log received1. DFPDMAQ15: SendQueue_ CleanACKDMA 3. SRST received DSR0: Software_reset_ asserted 4. Any other command received DFPDMAQ12: BrokenHost_ ClearBusy NOTE: 1. See 13.7 DFPDMAQ14: Discard all commands in the pending device queue. Transmit Set SendQueue_CleanACK Device Bits FIS with ERR in Status field cleared to zero, Error field set to 00h, ACT field = FFFFFFFFh, and Interrupt bit cleared to zero. 1. Set Device Bits FIS transmission complete DPIOI0: PIO_in DFPDMAQ15: Discard all commands in the pending device queue. Transmit Set SendQueue_ Device Bits FIS with ERR in Status field cleared to zero, Error field CleanACKDMA set to 00h, ACT field = FFFFFFFFh, and Interrupt bit cleared to zero. 1. Set Device Bits FIS transmission complete DDMAI0: DMA_in Serial ATA Revision 3.0 Gold Revision page 460 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization DFPDMAQ1: AddCommandToQueue: This state is entered when the device has checked the command and determined it to be a native queued type command, and Native Command Queuing is supported and enabled. When in this state, the device shall check the TAG validity and verify that it is not already assigned to an outstanding command. If valid, the device shall append the command to its internal command queue and store the new TAG value. Transition DFPDMAQ1:1: When the device determines the TAG is valid, and has added the command to its internal command queue, the device shall transition to the DFPDMAQ2: ClearInterfaceBusy state. Transition DFPDMAQ1:2: When the device determines that the received command is malformed, an error has occurred and the device shall transition to the DFPDMAQ12: BrokenHost_ClearBusy state. A command may be considered malformed as a result of any of its parameters being invalid, including the use of a TAG value that corresponds to an existing TAG value for a pending command. DFPDMAQ2: ClearInterfaceBusy: This state is entered when the device has appended the command to its internal queue and is ready transmit a Register FIS with BSY bit cleared to zero and DRQ bit cleared to zero to indicate that the interface is ready to receive the next command Transition DFPDMAQ2:1: When the Register FIS has been transmitted, the device shall transition to the DI0: Device_idle state. DFPDMAQ3: DataPhaseReadSetup: This state is entered when the device has determined that it is ready to transmit data for a previously queued READ FPDMA QUEUED command. When in this state, the device shall transmit a DMA Setup FIS to the host with the DMA buffer identifier set to the queued TAG value and the Direction bit set to one (host memory write). Transition DFPDMAQ3:1: When the device completes the transmission of the DMA Setup FIS, the device shall transition to the DFPDMAQ8: DataXmitRead state. DFPDMAQ4: DataPhasePreWriteSetup: This state is entered when the device has determined that it is ready to receive data for a previously queued WRITE FPDMA QUEUED command. When in this state, the device shall determine if the DMA Setup Auto-Activate option is supported and enabled, and then make the appropriate state transition. Transition DFPDMAQ4:1: If the DMA Setup FIS Auto-Activate option is enabled, the device shall transition to the DFPDMAQ5: DataPhase_WriteSetup state. Transition DFPDMAQ4:2: If the DMA Setup FIS Auto-Activate option is not supported or not enabled, the device shall transition to the DFPDMAQ6: DataPhase_OldWriteSetup state. DFPDMAQ5: DataPhase_WriteSetup: This state is entered when the device is ready to Auto Activate and receive data for a previously queued WRITE FPDMA QUEUED command. When in this state, the device transmits a DMA Setup FIS to the host with the DMA buffer identifier set to the queued TAG value and the Direction bit cleared to zero (host memory read), and Auto-Activate bit set to one. Serial ATA Revision 3.0 Gold Revision page 461 of 663 Transition DFPDMAQ5:1: When the device completes the transmission of the DMA Setup FIS, the device shall transition to the DFPDMAQ9: DataXmitWrite state. DFPDMAQ6: DataPhase_OldWriteSetup: This state is entered when the device is ready to receive data for a previously queued WRITE FPDMA QUEUED command, and the device does not support Auto-Activate, or it is not enabled. When in this state, the device transmits a DMA setup FIS to the host with the DMA buffer identifier set to the queued TAG value and the Direction bit cleared to zero (host memory read), and Auto-Activate bit cleared to zero. Transition DFPDMAQ6:1: When the device completes the transmission of the DMA Setup FIS, the device shall transition to the DFPDMAQ7: DataPhase_XmitActivate state. DFPDMAQ7: DataPhaseXmit_Activate: This state is entered after the device has completed transmission of a DMA Setup FIS for a WRITE FPDMA QUEUED command or the device has finished receiving a Data FIS for a WRITE FPDMA QUEUED command, and the transfer count is not exhausted. When in this state, the device transmits a DMA Activate FIS to the host indicating readiness to receive Data FISes from the host. Transition DFPDMAQ7:1: When the device completes the transmission of the DMA Activate FIS, the device shall transition to the DFPDMAQ9: DataXmitWrite state. DFPDMAQ8: DataXmitRead: This state is entered after the device has completed transmission of a DMA Setup FIS for a READ FPDMA QUEUED command. When in this state, the device transmits a Data FIS to the host. Transition DFPDMAQ8:1: If the transfer count for the previous DMA Setup FIS is not exhausted and no error is encountered, the device remains in the DFPDMAQ8: DataXmitRead state. Transition DFPDMAQ8:2: If the transfer count for the previous DMA Setup FIS is exhausted, and the data transfer for this command is not complete, and no error is encountered, the device shall transition to the DI0: Device_idle state. This condition requires that non-zero buffer offsets be supported and enabled. The transition also applies if a device switches between multiple active commands and is performing partial data transfers for the multiple outstanding commands Transition DFPDMAQ8:3: If the device has completed the data transfer for this command, and no error is encountered, the device shall transition to the DI0: Device_idle state. Transition DFPDMAQ8:4: If the device determines that an unrecoverable error has occurred, the device shall transition to the DI0: Device_idle state. DFPDMAQ9: DataXmitWrite: This state is entered after the device has completed transmission of a DMA Setup FIS for a WRITE FPDMA QUEUED command. When in this state, the device receives a Data FIS from the host. Serial ATA Revision 3.0 Gold Revision page 462 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transition DFPDMAQ9:1: After the data FIS reception is complete, and if the transfer count for the previous DMA Setup FIS is not exhausted and no error is encountered, the device shall transition to the DFPDMAQ7: DataPhase_XmitActivate state. Transition DFPDMAQ9:2: If the transfer count for the previous DMA Setup FIS is exhausted, and the data transfer for this command is not complete, and no error is encountered, the device shall transition to the DI0: Device_idle state. This condition requires that non-zero buffer offsets be supported and enabled. The transition also applies if a device switches between multiple active commands and is performing partial data transfers for the multiple outstanding commands Transition DFPDMAQ9:3: If the device has completed the data transfer for this command, and no error is encountered, the device shall transition to the DI0: Device_idle state. Transition DFPDMAQ9:4: If the device determines that an unrecoverable error has occurred, the device shall transition to the DI0: Device_idle state. DFPDMAQ10: SendStatus: This state is entered when the data transfer for this command, or aggregated commands, is completed and the device is ready to send status. When in this state, the device transmits a Set Device Bits FIS to the host with ERR bit cleared to zero, Interrupt bit set to one, and bit n in ACT field set to one where n = TAG for each command TAG value that has completed since the last status return. Transition DFPDMAQ10:1: When the device completes the transmission of the Set Device Bits FIS, the device shall transition to the DI0: Device_idle state. DFPDMAQ11: ERROR: This state is entered when the device has encountered an unrecoverable error. When in this state, the device halts command processing and transmits a Set Device Bits FIS to the host with ERR bit set to one, Interrupt bit set to one, ATA error code set in the Error field, and bits in ACT field cleared to zero for any outstanding queued commands (including the erring command) and bits set to one for any successfully completed queued command for which a completion notification has not yet been provided to the host. Transition DFPDMAQ11:1: When the device completes the transmission of the Set Device Bits FIS, the device shall transition to the DFPDMAQ13: WaitforClear state. DFPDMAQ12: BrokenHost_ClearBusy: This state is entered when the device has received a READ FPDMA QUEUED or WRITE FPDMA QUEUED command with a TAG that already exists in its command queue, or when the received command is a not a READ FPDMA QUEUED; and not a WRITE FPDMA QUEUED; and not a DEVICE RESET; and there are native queued command(s) outstanding. When in this state, the device halts command processing and transmits a Register FIS to the host with ERR set to one in the Status field, Interrupt bit set to one, BSY bit cleared to zero, DRQ bit cleared to zero, and ATA error code set in the Error field. If error condition was due to reception of an Unload request and the device supports Unload when NCQ commands are outstanding, the device shall unload/park the heads. Transition DFPDMAQ12:1: When the device completes the transmission of the Register FIS, the device shall transition to the DFPDMAQ13: WaitforClear state. Serial ATA Revision 3.0 Gold Revision page 463 of 663 DFPDMAQ13: WaitforClear: This state is entered when the device has transmitted an error FIS to the host and is awaiting a command to read the Queued Error Log (see 13.7) or a soft reset. Any other commands return Register – Device to Host FIS with the ERR bit set to one in the Status field. Transition DFPDMAQ13:1: If the device receives a READ LOG EXT command to read the Queued Error Log, the device shall transition to the DFPDMAQ14: SendQueue_CleanACK state. Transition DFPDMAQ13:2: If the device receives a READ LOG DMA EXT command to read the Queued Error Log, and IDENTIFY DEVICE word 76 bit 15 is set to one, the device shall transition to the DFPDMAQ15: SendQueue_CleanACKDMA state. Transition DFPDMAQ13:3: If the device receives a SRST, the device shall transition to the DSR0: Software_reset_asserted state. Transition DFPDMAQ13:4: If the device receives any other command, the device shall transition to the DFPDMAQ12: BrokenHost_ClearBusy state. DFPDMAQ14: SendQueue_CleanACK: This state is entered when the host has responded to an error FIS to a command to read the Queued Error Log. The device shall discard all commands in the pending queue and transmit a Set Device Bits FIS with ERR bit in the Status field cleared to zero, Error field set to 00h, ACT field = FFFFFFFFh, and Interrupt bit cleared to zero. Transition DFPDMAQ14:1: when the Set Device Bits FIS transmission is complete, the device shall transition to the DPIOI0: PIO_in state. DFPDMAQ15: SendQueue_CleanACKDMA: This state is entered when the host has responded to an error FIS to a command to read the Queued Error Log . The device shall discard all commands in the pending queue and transmit a Set Device Bits FIS with ERR bit in the Status field cleared to zero, Error field set to 00h, ACT field = FFFFFFFFh, and Interrupt bit cleared to zero. Transition DFPDMAQ14:1: when the Set Device Bits FIS transmission is complete, the device shall transition to the DDMAI0: DMA_in state. Serial ATA Revision 3.0 Gold Revision page 464 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 12 Host Command Layer protocol 12.1 FPDMA QUEUED command protocol This high-level state machine describes the behavior of the host for the Native Command Queuing command protocol. The host behavior described by the state machine may be provided by host software and/or host hardware and the intent of the state machines is not to indicate any particular implementation. This class includes: READ FPDMA QUEUED WRITE FPDMA QUEUED NCQ QUEUE MANAGEMENT HFPI0: Idle 1. Free TAG location and command waiting to have TAG assigned 2. Command with assigned TAG awaiting issue and BSY bit cleared to zero and not First-party DMA Data Phase 3. Interrupt received from device. HFPDMAQ2: PresetACTBit HFPDMAQ3: IssueCommand HFPDMAQ4: DeviceINT 4. Default HFPI0: Idle NOTE: 1. If more than one condition is true, the host may apply a vendor specific priority HFPDMAQ1: AddCommandToQueue 1. Unconditional Append command to internal host command queue HFPI0: Idle HFPDMAQ2: Assign free TAG value to command. Write SActive register with PresetACTBit value that has bit set in bit position corresponding to assigned TAG value 1. TAG value assigned to command and SActive register HFPI0: Idle written with new TAG bitmask HFPDMAQ3: If not First-party DMA Data Phase, transmit Register FIS to device IssueCommand with new command and assigned TAG value 1. Register FIS transmission complete (command issued) HFPI0: Idle 2. Register FIS transmission deferred (command not issued) HFPI0: Idle HFPDMAQ4: DeviceINT 1. Unconditional Read Status register to clear pending interrupt flag and save value as SavedStatus HFPDMAQ5: CompleteRequests1 Serial ATA Revision 3.0 Gold Revision page 465 of 663 HFPDMAQ5: Compare SActive register with stored SActive register from last CompleteRequests1 interrupt to identify completed commands 1. SActive comparison indicates one or more commands HFPDMAQ6: are completed CompleteRequests2 2. SActive comparison indicates no commands are HFPDMAQ7: completed CompleteRequests3 HFPDMAQ6: CompleteRequests2 1. Unconditional Retire host requests associated with TAG values corresponding to newly cleared bits in the SActive register and update stored SActive with new value HFPDMAQ7: CompleteRequests3 HFPDMAQ7: CompleteRequests3 Test ERR bit in SavedStatus value 1. ERR bit cleared to zero 2. ERR set to one HFPI0: Idle HFPDMAQ8: ResetQueue HFPDMAQ8: Issue a command to read the Queued Error Log to device ResetQueue 1. READ LOG EXT command was accepted HFPDMAQ9: CleanupACK 2. READ LOG DMA EXT command was accepted HFPDMAQ12: RetrieveRequest_ SenseDMA 3. Command was not accepted HFPDMAQ8: ResetQueue HFPDMAQ9: Wait for DRQ bit set to one and BSY bit cleared to zero 1 CleanupACK 1. DRQ bit set to one and BSY bit cleared to zero HFPDMAQ10: RetrieveRequest_ Sense 2. DRQ cleared to zero or BSY set to one HFPDMAQ9: CleanupACK NOTE: 1. The host may wait for this condition using any means including awaiting an interrupt and checking the DRQ bit and BSY bit status, spinning, or periodic timer. HFPDMAQ10: Receive PIO Data FIS with Queued Error Log contents RetrieveRequest_Sense 1. PIO Data FIS reception complete HFPDMAQ11: ErrorFlush Serial ATA Revision 3.0 Gold Revision page 466 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization HFPDMAQ11: Retire failed queued command with status set to error condition ErrorFlush reported by device. Flush all allocated native queued command tags. Flush pending native queued commands from host command queue with system-specific error condition or re-issue pending queued commands. 1. Unconditional HFPI0: Idle HFPDMAQ12: Receive Data FIS with Queued Error Log contents RetrieveRequest_ SenseDMA 1. Data FIS reception complete HFPDMAQ13: SendStatus HFPDMAQ11: Request transmission of a Register FIS to the host ErrorFlush 1. Register FIS transmitted HFPDMAQ11: ErrorFlush HFPI0: Idle: When in this state, if queuing is supported and enabled, the Command layer is awaiting a READ FPDMA QUEUED, WRITE FPDMA QUEUED or NCQ QUEUE MANAGEMENT command from the higher level protocol, or awaiting an interrupt from the Device indicating completion of previously queued commands, or waiting for a TAG location to become available for a command waiting in the command queue. Transition HFPI0:1: If a READ FPDMA QUEUED, WRITE FPDMA QUEUED or NCQ QUEUE MANAGEMENT command is pending that has not had a TAG value assigned to it and there is a free TAG location available for assignment then a transition shall be made to the HFPDMAQ2: PresetACTBit state. Transition HFPI0:2: If a command with assigned TAG value is awaiting issue to the device and BSY bit cleared to zero and the interface is not in the First-party DMA Data Phase, then a transition shall be made to the HFPDMAQ3: IssueCommand state. Transition HFPI0:3: If an interrupt is received from the device, indicating status is available for a previously queued command, it shall transition to the HFPDMAQ4: DeviceINT state. Transition HFPI0:4: If the queuing is supported and enabled, and the Command layer is awaiting a free TAG, a new command, or an interrupt for a previously queued command, it shall transition to the HFPI0: Idle state. HFPDMAQ1: AddCommandToQueue: The Command layer enters this state when it has received a READ FPDMA QUEUED, WRITE FPDMA QUEUED or NCQ QUEUE MANAGEMENT command from the higher level protocol, and adds it to the internal host command queue. Transition HFPDMAQ1:1: After the Command Layer has added the command to the internal host command queue, it shall transition to the HFPI0: Idle state. HFPDMAQ2: PresetACTBit: When in this state, the Command layer assigns a free TAG value to the previously queued command and writes the SActive register with the bit position corresponding to the assigned TAG value. Transition HFPDMAQ2:1: After the Command layer has assigned a TAG value and written the corresponding bit to the SActive register, it shall transition to the HFPI0: Idle state. Serial ATA Revision 3.0 Gold Revision page 467 of 663 HFPDMAQ3: IssueCommand: When in this state, the Command layer attempts to issue a command with preassigned TAG to the device by transmitting a Register FIS to the device with the new command and assigned TAG value if the interface state permits it. Transition HFPDMAQ3:1: After the Command layer has transmitted the Register FIS, it shall mark the corresponding command as issued and transition to the HFPI0: Idle state. Transition HFPDMAQ3:2: After the Command layer has deferred transmission of the Register FIS due to the interface state not permitting it to be delivered, it shall transition to the HFPI0: Idle state. The corresponding command is still considered as not having been issued. HFPDMAQ4: DeviceINT: When in this state, the Command layer reads the Device Status Register to reset the pending interrupt flag and save the value as SavedStatus. Transition HFPDMAQ4:1: After the Command layer has read the Device Status Register, it shall transition to the HFPDMAQ5: CompleteRequests1 state. HFPDMAQ5: CompleteRequests1: When in this state, the Command layer compares the SActive Register with the SavedStatus SActive Register value that resulted from the last interrupt to identify completed commands. Transition HFPDMAQ5:1: If the SActive comparison indicates one or more commands have completed, it shall transition to the HFPDMAQ6: CompleteRequests2 state. Transition HFPDMAQ5:2: If the SActive comparison indicates no commands have completed, it shall transition to the HFPDMAQ7: CompleteRequests3 state. HFPDMAQ6: CompleteRequests2: When in this state, the Command layer retires commands in its internal host command queue that are associated with TAG values corresponding to newly cleared bits in the SActive Register and updates the stored SActive register with the new value. Transition HFPDMAQ6:1: After updating the stored SActive value, it shall transition to the HFPDMAQ7: CompleteRequests3 state. HFPDMAQ7: CompleteRequests3: When in this state, the Application layer tests the ERR bit in the SavedStatus value to determine whether the queue should be maintained or reset. Transition HFPDMAQ7:1: If the SavedStatus value ERR bit cleared to zero, the queue is maintained and it shall transition to the HFPI0: Idle state. Transition HFPDMAQ7:2: If the SavedStatus value ERR bit set to one, an error has been reported by the Device and the Command layer shall transition to the HFPDMAQ8: ResetQueue state. HFPDMAQ8: ResetQueue: When in this state, the Application layer issues a command to read the Queued Error Log (see 13.7) to the device. Transition HFPDMAQ8:1: After a READ LOG EXT command has been accepted, it shall transition to the HFPDMAQ9: CleanupACK state. Transition HFPDMAQ8:2: After a READ LOG DMA EXT command has been accepted, it shall transition to the HFPDMAQ12: RetrieveRequest_SenseDMA . Serial ATA Revision 3.0 Gold Revision page 468 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transition HFPDMAQ8:3: If the command was not accepted, the host shall transition to the HPFDMAQ8: ResetQueue state. HFPDMAQ9: CleanupACK: When in this state, the Command layer tests the Device for DRQ bit set to one and BSY bit cleared to zero in preparation for a PIO data FIS transfer. Transition HFPDMAQ9:1: If DRQ bit is set to one and BSY bit is cleared to zero, it shall transition to the HFPDMAQ10: ReceiveRequestSense state. Transition HFPDMAQ9:2: If DRQ bit is cleared to zero or BSY bit is set to one, it shall transition to the HFPDMAQ9: CleanupACK state. HFPDMAQ10: RetrieveRequest_Sense: When in this state, the Command layer completes the PIO Data FIS that retrieves the Queued Error Log contents. Transition HFPDMAQ10:1: After the completion of the PIO Data FIS, it shall transition to the HFPDMAQ11: ErrorFlush state. HFPDMAQ11: ErrorFlush: When in this state, the Command layer retires the failed queued command with the error status set to the error condition reported by the device. It flushes all allocated native queued command tags, and flushes pending native commands from the host command queue with system-specific error condition or re-issue pending queued commands Transition HFPDMAQ11:1: After the error flush actions have been completed, it shall transition to the HFPI0: Idle state. HFPDMAQ12: RetrieveRequest_SenseDMA: This state is entered when the device has the data ready to transfer a data FIS to the host containing the Queued Error Log contents. When in this state, the device shall request that the Transport layer transmit a data FIS containing the data. The device command layer shall request a Data FIS size of no more than 2048 Dwords . Transition HFPDMAQ13:1: When the FIS has been transmitted, the device shall transition to the HFPDMAQ13: SendStatus state. HFPDMAQ13: SendStatus: This state is entered when the device has transferred all of the data requested by the command or has encountered an error that causes the command to abort before completing the transfer of the requested data. When in this state, the device shall request that the Transport layer transmit a Register FIS with register content as described in the command description in the ATA8-ACS standard and the Interrupt bit set to one. Transition DDMAI2:1: When the FIS has been transmitted, the device shall transition to the HFPDMAQ11: ErrorFlush state. Serial ATA Revision 3.0 Gold Revision page 469 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 13 Application Layer 13.1 Parallel ATA Emulation Emulation of parallel ATA device behavior as perceived by the host BIOS or software driver, is a cooperative effort between the device and the Serial ATA host adapter hardware. The behavior of Command and Control Block registers, PIO and DMA data transfers, resets, and interrupts are all emulated. The host adapter contains a set of registers that shadow the contents of the traditional device registers, referred to as the Shadow Register Block. All Serial ATA devices behave like Device 0 devices. Devices shall ignore the DEV bit in the Device field of received Register – Host to Device FISes, and it is the responsibility of the host adapter to gate transmission of Register – Host to Device FISes to devices, as appropriate, based on the value of the DEV bit. After a reset or power-on, the host bus adapter emulates the behavior of a traditional ATA system during device discovery. Immediately after reset, the host adapter shall place the value 7Fh in its Shadow Status register and shall place the value FFh in all the other Shadow Command Block registers (FFFFh in the Data register). In this state the host bus adapter shall not accept writes to the Shadow Command Block Registers. When the Phy detects presence of an attached device, the host bus adapter shall place the value FFh or 80h in the Shadow Status register, and the host bus adapter shall now allow writes to the Shadow Command Block Registers. If a device is present, the Phy shall take no longer than 10 ms to indicate that it has detected the presence of a device, and has set the BSY bit to one in the Shadow Status register. Placing the value 80h in the Shadow Status register is recommended as it provides the highest level of BIOS compatibility. Note that when the BSY bit is set to one in the Shadow Status register all other bits in that register have indeterminate values. When the attached device establishes communication with the host bus adapter, it shall send a Register – Device to Host FIS to the host, resulting in the Shadow Command Block Registers being updated with values appropriate for the attached device. BIOS and system software writers should be aware of the 10 ms latency the interface may incur in determining device presence, and either ensure the Shadow Status register is read no sooner than 10 ms after initialization or ensure the Shadow Status register is re-read 10 ms after having read a value of 7Fh in order to positively determine presence of a device. The host adapter may present a Master-only emulation to host software, that is, each device is a Device 0, and each Device 0 is accessed at a different set of host bus addresses. The host adapter may optionally present a Master/Slave emulation to host software, that is, two devices on two separate Serial ATA ports are represented to host software as a Device 0 and a Device 1 accessed at the same set of host bus addresses. 13.1.1 Software Reset According to the ATA/ATAPI-6 standard, issuing a software reset is performed by toggling the SRST bit in the Device Control register. The toggle period is stipulated as being no shorter than 5 us. As a result of the SRST bit changing in the Device Control register, Serial ATA host adapters shall issue at least two Register – Host to Device FISes to the device (one with the SRST bit set to one and a subsequent one with the SRST bit cleared to zero). See section 10.3.4 for a detailed definition of Register – Host to Device FIS. Although host software is required to toggle the SRST bit no faster than 5 us, devices may not rely on the inter-arrival time of received Register – Host to Device FISes also meeting this timing. Because of flow control, frame handshaking, and other protocol interlocks, devices may effectively receive the resulting Register – Host to Device FISes back-to-back. Serial ATA Revision 3.0 - Gold Revision Due to flow control, protocol interlocks, power management state, or other transmission latencies, the subsequent Register – Host to Device FIS transmission clearing the SRST bit to zero during a software reset may be triggered prior to the previous Register – Host to Device FIS transmission having been completed. Host adapters are required to allow host software to toggle the SRST bit with the minimum 5 us timing specified in the ATA/ATAPI-6 standard even if frame transmission latencies result in the first Register FIS transmission taking longer than 5 us. Host adapters are required to ensure transmission of the two resulting Register – Host to Device FISes to the device regardless of the transmission latency of each individual FIS. 13.1.2 Master-only emulation NOTE: Unlike the remainder of this specification, this section is based on the ATA/ATAPI-5 standard. A native Serial ATA host adapter behaves the same as if a legacy mode master only device were attached with no slave present. It is the responsibility of the host adapter to properly interact with host software and present the correct behavior for this type of configuration. All Serial ATA devices, therefore, need not be aware of master / slave issues and ignore legacy mode task file information that deal with a secondary device. When the DEV bit in the Device register is set to one, selecting the non-existent Device 1, the host adapter shall respond to register reads and writes as specified for a Device 0 with no Device 1 present, as defined in the ATA/ATAPI-5 standard. This includes not setting the BSY bit to one in the Shadow Status register when Device 1 is selected, as described in the ATA/ATAPI-5 standard. When Device 0 is selected, the host adapter shall execute the Serial ATA protocols for managing the Shadow Status register contents as defined in later sections. When Device 0 is selected and the Command register is written in the Shadow Register Block, the host adapter sets the BSY bit to one in its shadow Status register. The host adapter then transmits a Register – Host to Device FIS to the device containing the new register contents. When the Device Control register is written in the Shadow Register Block with a change of state of the SRST bit, the host adapter sets the BSY bit to one in its shadow Status register and transmit a Register – Host to Device FIS to the device containing the new register contents. Transmission of register contents when the Device Control register is written with any value that is not a change of state of the SRST bit shall not set the BSY bit to one in the shadow Status register, and transmission of a frame to the device containing new register contents is optional. Similarly, the host adapter sets the BSY bit in its shadow Status register to one when a COMRESET is requested or the SRST bit is set to one in the Device Control register. The expected timing for setting BSY bit to one is thereby preserved. The device updates the contents of the host adapter Shadow Register Block by transmitting a Register – Device to Host FIS. This allows the device to set the proper ending status in the host adapter Shadow Register Block at the completion of a command or control request. Specific support is added to ensure proper timing of the DRQ and BSY bits in the Status register for PIO transfers. Finally the host adapter cooperates with the device by providing an interrupt pending flag in the host adapter. This flag is set by the host adapter when the device sends a Register – Device to Host FIS with the Interrupt bit set to one. The host adapter asserts the interrupt to the host processor any time the interrupt pending flag is set, the DEV bit is cleared to zero in the shadow Device register, and the nIEN bit in the shadow Device Control register is cleared to zero. The host adapter clears the interrupt pending flag any time a COMRESET is requested, the SRST bit in the shadow Device Control register is set to one, the shadow Command register is written with DEV bit cleared to zero, or the Shadow Status register is read with DEV bit cleared to zero. This allows the emulation of the host interrupt and its proper timing. Serial ATA Revision 3.0 Gold Revision page 472 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 13.1.3 Master/Slave emulation (optional) NOTE: Unlike the remainder of this specification, this section is based on the ATA/ATAPI-5 standard. All devices behave as if they are Device 0 devices. However, the host adapter may optionally implement emulation of the behavior of a Master/Slave configuration by pairing two Serial ATA ports, and managing their associated shadow registers accordingly, as though they were a Device 0 and Device 1 at the same set of host bus addresses. A host adapter that emulates Master/Slave behavior shall manage the two sets of shadow registers (one set for each of the two devices) based on the value of the DEV bit in the shadow Device register. Based on the value of the DEV bit, the host adapter shall direct accesses to the Shadow Register Block Registers, and accesses to the Control Block Registers, to the appropriate set of shadow registers in the correct device. It is the responsibility of the host adapter to ensure that communication with one or both of the attached devices is handled properly, and that information gets routed to the devices correctly. Each device shall process any communication with the host adapter as if it is targeted for the device regardless of the value of the DEV bit. If a host adapter is emulating Master/Slave behavior, and there is no device attached to the cable designated as the Device 1 cable, the host adapter shall emulate Device 0 behavior with no Device 1 present as described in the ATA/ATAPI-5 standard. 13.1.3.1 Software reset Host adapters that emulate Master/Slave behavior shall emulate proper behavior for software reset. Based on the Phy initialization status, the host adapter knows whether a device is attached to each of the two ports used in a Master/Slave emulation configuration. Device Control register writes, that have the SRST bit set to one, shall result in the associated Shadow Device Control register being written for each port to which a device is attached. The frame transmission protocol for each associated port executed, results in a Register – Host to Device FIS being transmitted to each attached device. Similarly, the subsequent write to the Shadow Device Control register that clears the SRST bit to zero shall result in a Register – Host to Device FIS being sent to each attached device. The host adapter shall then await a response from each attached device (or timeout), and shall merge the contents of the Error and Status registers for the attached devices, in accordance with the ATA/ATAPI-5 standard, to produce the Error and Status register values visible to host software. 13.1.3.2 EXECUTE DEVICE DIAGNOSTICS Host adapters that emulate Master/Slave behavior shall emulate proper behavior for EXECUTE DEVICE DIAGNOSTICS. The host adapter shall detect the EXECUTE DEVICE DIAGNOSTIC command being written to the Command register. Detecting the EXECUTE DEVICE DIAGNOSTICS command shall result in the associated shadow register being written for each port to which a device is attached. The frame transmission protocol for each associated port executed, results in a Register – Host to Device FIS being transmitted to each attached device. The host adapter shall then await response from each attached device (or timeout), and shall merge the contents of the Error and Status registers for the attached devices, in accordance with the ATA/ATAPI-5 standard to produce the Error and Status register values visible to host software. 13.1.3.3 Restrictions and limitations Superset capabilities that are unique to Serial ATA and not supported by parallel ATA may not be supported in Master/Slave emulation mode. Such capabilities include but are not limited to support for First-party DMA, hot plug/unplug, interface power management, and superset Status Serial ATA Revision 3.0 Gold Revision page 473 of 663 and Control registers. Master/Slave emulation is recommended only in configurations where software written for parallel ATA is used and the number of attached devices exceeds the number of Shadow Command Block register interfaces that software supports. 13.1.3.4 Shadow Command Block Register Access Restrictions Host software should take measures to ensure that the access restrictions for the Command Block registers (see ATA/ATAPI-5) are observed when accessing the Shadow Command Block registers in order to avoid indeterminate behavior. Some of these measures include: a) Prior to writing the Shadow Command Block registers to issue a new command, host software should check the Shadow Status register to verify that both BSY and DRQ bits are cleared to zero. b) If DRQ bit is set to one when software expects it to be cleared to zero (e.g. when ERR bit is set to one), host software should perform an error recovery action (e.g., issue a software reset to the device) prior to writing the Shadow Command register to issue a new command. Note: Issuing a software reset by setting the SRST bit to one in the Device Control register to one while BSY bit and/or DRQ bit are set to one is legal behavior as described in the Serial ATA state machines, and completion of a software reset ensures that the device and interface are in a known state. The ATA/ATAPI-5 standard defines restrictions for writing to the Command Block registers. It is prohibited to write the Shadow Command register when BSY bit or DRQ bit is set to one except for the DEVICE RESET command. The Serial ATA access restrictions differ from parallel ATA where similar access to the Command register is indeterminate. However, the resultant indeterminate behavior may, in some Serial ATA implementations, not be as benign as in some parallel ATA implementations. This is because in Serial ATA the Shadow Command Block registers are cooperatively managed between the host and the device, and the defined coordination is based on the values of BSY and DRQ bits. An example situation where parallel ATA and Serial ATA behavior may differ is when the device sets both DRQ and ERR bits to one in the (Shadow) Status register in a PIO read operation. In parallel ATA, many device implementations allow software to issue a new command without transferring the data from the device. In Serial ATA, issuing a new command without transferring the data may lead to a hang condition. In Serial ATA, when DRQ bit is set to one there is an associated Data FIS that is being transferred on the Serial ATA interface. Until the Data FIS transfer is completed by the host reading the associated data from the Shadow Data register, the Data FIS remains on the interface in a HOLDP/ HOLDAP flow-controlled condition. While the Data FIS remains on the interface, a new command cannot be issued to the device. 13.1.3.5 Parallel ATA interoperability state diagrams Serial ATA Revision 3.0 Gold Revision page 474 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization This state diagram defines the protocol of the host adapter to emulate Master only parallel ATA devices as seen from the host BIOS or software driver. The interrupt pending flag (IPF) is an internal state bit in the host adapter that reflects whether or not the device has an interrupt pending to the host. HA0: HA_SEL/NOINTRQ The interrupt signal is not asserted to the host. 1. COMRESET requested by the host. HA_SEL/NOINTRQ 2. Device Control register written by the host with SRST bit cleared to zero and (nIEN bit set to one or IPF bit set to one). 3. Device Control register written by the host with SRST bit cleared to zero and (nIEN bit cleared to zero and IPF bit set to one). 4. Device Control register written by the host with SRST bit set to one. 5. Command register written by the host. HA_SEL/NOINTRQ HA_SEL/INTRQ HA_SEL/NOINTRQ HA_SEL/NOINTRQ 6. Device register written by the host with DEV bit set to one. 7. Any other register read or write by the host HA_NOTSEL HA_SEL/NOINTRQ 8. Transport layer indicates new register content from the device with the IPF bit cleared to zero. 9. Transport layer indicates new register content from the device with the IPF bit set to one and nIEN bit to one. 10. Transport layer indicates new register content from the device with the IPF bit set to one and nIEN bit cleared to zero. HA_SEL/NOINTRQ HA_SEL/NOINTRQ HA_SEL/INTRQ HA1: HA_SEL/INTRQ The interrupt signal is asserted to the host. 1. COMRESET requested by the host. 2. Device Control register written by the host with SRST bit cleared to zero and (nIEN bit set to one or IPF bit cleared to zero). 3. Device Control register written by the host with SRST bit cleared to zero and (nIEN bit cleared to zero and IPF bit set to one). 4. Device Control register written by the host with SRST bit set to one. 5. Command register written by the host. 6. Device register written by the host with DEV bit set to one. 7. Status register read by the host 8. Any other register write by the host 9. Any other register read by the host 10. Transport layer indicates new register content from the device. HA_SEL/NOINTRQ HA_SEL/NOINTRQ HA_SEL/INTRQ HA_SEL/NOINTRQ HA_SEL/NOINTRQ HA_NOTSEL HA_SEL/NOINTRQ HA_SEL/INTRQ HA_SEL/INTRQ HA_SEL/INTRQ Serial ATA Revision 3.0 Gold Revision page 475 of 663 HA2: HA_NOTSEL The interrupt signal is not asserted to the host. 1. COMRESET requested by the host. HA_SEL/NOINTRQ 2. Device Control register written by the host with SRST bit cleared to zero. 3. Device Control register written by the host with SRST bit set to one. 4. Command register written by the host with command other than EXECUTE DEVICE DIAGNOSTIC. 5. Command register written by the host with command EXECUTE DEVICE DIAGNOSTIC. 6. Device register written by the host with DEV bit cleared to zero and (nIEN bit set to one or IPF bit cleared to zero). 7. Device register written by the host with DEV bit cleared to zero and (nIEN bit cleared to zero and IPF bit set to one). 8. Any other register write by the host HA_NOTSEL HA_SEL/NOINTRQ HA_NOTSEL HA_SEL/NOINTRQ HA_SEL/NOINTRQ HA_SEL/INTRQ HA_NOTSEL 9. Read of Status or Alternate Status register by the host. 10. Read of any other register by the host. HA_NOTSEL HA_NOTSEL 11. Transport layer indicates new register content from the device. HA_NOTSEL HA0: HA_SEL/NOINTRQ state: This state is entered when Device 0 is selected and either IPF bit is cleared to zero or nIEN bit is set to one. When in this state, the interrupt signal to the host shall not be asserted. Transition HA0:1: When a COMRESET is requested by the host, the host adapter shall set BSY bit to one in the shadow Status register, clear IPF bit to zero, notify the Link layer to have a bus COMRESET asserted, and make a transition to the HA0: HA_SEL/NOINTRQ state. Transition HA0:2: When the Device Control register is written by the host with SRST bit cleared to zero and either nIEN bit set to one or IPF bit is cleared to zero, the host adapter shall notify the Transport layer to send a Register – Host to Device FIS with C bit cleared to zero with the current content of the shadow registers, and make a transition to the HA0: HA_SEL/NOINTRQ state. Transition HA0:3: When the Device Control register is written by the host with SRST bit cleared to zero, nIEN bit cleared to zero, and IPF bit is set to one, the host adapter shall notify the Transport layer to send a Register – Host to Device FIS with C bit cleared to zero with the current content of the shadow registers, and make a transition to the HA1: HA_SEL/INTRQ state. Transition HA0:4: When the Device Control register is written by the host with SRST bit set to one, the host adapter shall set BSY bit to one in the Shadow Status register, clear IPF bit to zero, notify the Transport layer to send a Register – Host to Device FIS with C bit cleared to zero with the current content of the shadow registers, and make a transition to the HA0: HA_SEL/NOINTRQ state. Transition HA0:5: When the Command register is written by the host, the host adapter shall set BSY bit to one in the Shadow Status register, clear IPF bit to zero, notify the Transport layer to send a Register – Host to Device FIS with C bit set to one with the current content of the shadow registers, and make a transition to the HA0: HA_SEL/NOINTRQ state. Serial ATA Revision 3.0 Gold Revision page 476 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transition HA0:6: When the Device register is written by the host with DEV bit set to one, the host adapter shall make a transition to the HA2: HA_NOTSEL state. Transition HA0:7: When any register is read or written by the host other than those described above, the host adapter shall make a transition to the HA0: HA_SEL/NOINTRQ state. Transition HA0:8: When the Transport layer indicates new register content from the device with IPF bit cleared to zero, the host adapter shall place the new register content into the shadow registers and make a transition to the HA0: HA_SEL/NOINTRQ state. Transition HA0:9: When the Transport layer indicates new register content from the device with IPF bit set to one and nIEN bit set to one, the host adapter shall set IPF bit to one, place the new register content into the shadow registers, and make a transition to the HA0: HA_SEL/NOINTRQ state. Transition HA0:10: When the Transport layer indicates new register content from the device with IPF bit set to one and nIEN bit is cleared to zero, the host adapter shall set IPF bit to one, place the new register content into the shadow registers, and make a transition to the HA1: HA_SEL/INTRQ state. HA1: HA_SEL/INTRQ state: This state is when Device 0 is selected, nIEN bit is cleared to zero, and IPF bit is set to one. When in this state, the interrupt signal to the host shall be asserted. Transition HA1:1: When a COMRESET is requested by the host, the host adapter shall set BSY bit to one in the Shadow Status register, clear IPF bit to zero, notify the Link layer to have a bus COMRESET asserted, and make a transition to the HA0: HA_SEL/NOINTRQ state. Transition HA1:2: When the Device Control register is written by the host with SRST bit cleared to zero, with nIEN bit set to one or IPF bit cleared to zero, the host adapter shall notify the Transport layer to send a Register – Host to Device FIS with C bit cleared to zero with the current content of the shadow registers, and make a transition to the HA0: HA_SEL/NOINTRQ state. Transition HA1:3: When the Device Control register is written by the host with SRST bit cleared to zero with nIEN bit cleared to zero and IPF bit set to one, the host adapter shall notify the Transport layer to send a Register – Host to Device FIS with C bit cleared to zero with the current content of the shadow registers, and make a transition to the HA1: HA_SEL/INTRQ state. Transition HA1:4: When the Device Control register is written by the host with SRST bit set to one, the host adapter shall set BSY bit to one in the Shadow Status register, clear IPF bit to zero, notify the Transport layer to send a Register – Host to Device FIS with C bit cleared to zero with the current content of the shadow registers, and make a transition to the HA0: HA_SEL/NOINTRQ state. Transition HA1:5: When the Command register is written by the host, the host adapter shall set BSY bit to one in the Shadow Status register, clear IPF bit to zero, notify the Transport layer to send a Register – Host to Device FIS with C bit set to one with the current content of the shadow registers, and make a transition to the HA0: HA_SEL/NOINTRQ state. Transition HA1:6: When the Device register is written by the host with DEV bit set to one, the host adapter shall make a transition to the HA2: HA_NOTSEL state. Transition HA1:7: When the Status register is read by the host, the host adapter shall clear IPF bit to zero and make a transition to the HA0: HA_SEL/NOINTRQ state. Serial ATA Revision 3.0 Gold Revision page 477 of 663 Transition HA1:8: When any register is written by the host other than those described above, the host adapter shall make a transition to the HA1: HA_SEL/INTRQ state. Transition HA1:9: When any register is read by the host other than that described above, the host adapter shall make a transition to the HA1: HA_SEL/INTRQ state. Transition HA1:10: When the Transport layer indicates new register content from the device, the host adapter shall place the new register content into the shadow registers and make a transition to the HA1: HA_SEL/INTRQ state. HA2: HA_NOTSEL state: This state is entered when Device 1 is selected. When in this state, the interrupt signal to the host shall not be asserted. Transition HA2:1: When a COMRESET is requested by the host, the host adapter shall set BSY bit to one in the Shadow Status register, clear DEV bit to zero in the Shadow Device register, clear IPF bit to zero, notify the Link layer to have a bus COMRESET asserted, and make a transition to the HA0: SEL/NOINTRQ state. Transition HA2:2: When the Device Control register is written by the host with SRST bit cleared to zero, the host adapter shall notify the Transport layer to send a Register – Host to Device FIS with C bit cleared to zero with the current content of the shadow registers, and make a transition to the HA2: HA_NOTSEL state. Transition HA2:3: When the Device Control register is written by the host with SRST bit set to one, the host adapter shall set BSY bit to one in the Shadow Status register, clear DEV bit to zero in the Shadow Device register, clear IPF bit to zero, notify the Transport layer to send a Register – Host to Device FIS with C bit cleared to zero with the current content of the shadow registers, and make a transition to the HA0: HA_ SEL/NOINTRQ state. Transition HA2:4: When the Command register is written by the host with any command code other than EXECUTE DEVICE DIAGNOSTIC, the host adapter shall not set BSY bit in the Shadow Status register and shall make a transition to the HA2: HA_NOTSEL state. Transition HA2:5: When the Command register is written by the host with the EXECUTE DEVICE DIAGNOSTIC command code, the host adapter shall set BSY bit to one in the Shadow Status register, clear DEV bit to zero in the Device register, clear IPF bit to zero, notify the Transport layer to send a Register – Host to Device FIS with C bit set to one with the current content of the shadow registers, and make a transition to the HA0: HA_SEL/INTRQ state. Transition HA2:6: When the Device register is written by the host with DEV bit cleared to zero and either nIEN bit set to one or IPF bit cleared to zero, the host adapter shall make a transition to the HA0: HA_SEL/NOINTRQ state. Transition HA2:7: When the Device register is written by the host with DEV bit cleared to zero, nIEN bit cleared to zero, and IPF bit set to one, the host adapter shall make a transition to the HA1: HA_SEL/INTRQ state. Transition HA2:8: When any register is written by the host other than those described above, the host adapter shall make a transition to the HA2: HA_NOTSEL state. Transition HA2:9: When the Status or Alternate Status register is read by the host, the host shall return register content 00h to the host and make a transition to the HA2: HA_NOTSEL state. Serial ATA Revision 3.0 Gold Revision page 478 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Transition HA2:10: When any register is read by the host other than that described above, the host adapter shall return the current shadow register content to the host and make a transition to the HA2: HA_NOTSEL state. Transition HA2:11: When the Transport layer indicates new register content from the device, the host adapter shall place the new register content into the shadow registers and make a transition to the HA2: HA_NOTSEL state. 13.2 IDENTIFY (PACKET) DEVICE In the IDENTIFY DEVICE command various parameters are communicated to the host from the device. The following sections define those words that are different from and additions to the ATA8-ACS standard definition of the data contents. Serial ATA features and capabilities include a means by which their presence and support may be determined, and a means for enabling them if optionally supported. The IDENTIFY (PACKET) DEVICE settings requirements shall be implemented by native Serial ATA devices. The IDENTIFY (PACKET) DEVICE settings requirements are optional for parallel ATA devices with an external Serial ATA bridge attached. 13.2.1 IDENTIFY DEVICE Word 0-46 47 48 49 50-52 53 54-62 63 Table 75 – IDENTIFY DEVICE information O/M F/V Set as indicated in ATA8-ACS M Multiple Count F 15-8 80h R 7-0 00h = Reserved 01h-10h = Maximum number of sectors that shall be transferred per interrupt on READ/WRITE MULTIPLE commands 11h-FFh = Reserved Set as indicated in ATA8-ACS M Capabilities 15-12 Set as indicated in ATA8-ACS F 11 Shall be set to one F 10 Shall be set to one 9-0 Set as indicated in ATA8-ACS Set as indicated in ATA8-ACS M Field validity R 15-3 Reserved F 2 1=the fields reported in word 88 are valid 0=the fields reported in word 88 are not valid F 1 1=the fields reported in words (70:64) are valid 0=the fields reported in words (70:64) are not valid F 0 Obsolete Set as indicated in ATA8-ACS M Multiword DMA transfer 15-3 Set as indicated in ATA8-ACS F 2 1= Multiword DMA mode 2 and below are supported F 1 1= Multiword DMA mode 1 and below are supported F 0 1= Multiword DMA mode 0 is supported Serial ATA Revision 3.0 Gold Revision page 479 of 663 Word 64 65 66 67 68 69-74 75 76 77 78 79 O/M F/V M PIO transfer modes supported 15-2 Set as indicated in ATA8-ACS F 1-0 PIO modes 3 and 4 supported M Minimum Multiword DMA transfer cycle time per word F 15-0 Cycle time in nanoseconds M Manufacturer’s recommended Multiword DMA transfer cycle time F 15-0 Cycle time in nanoseconds M Minimum PIO transfer cycle time without flow control F 15-0 Cycle time in nanoseconds M Minimum PIO transfer cycle time with IORDY flow control F 15-0 Cycle time in nanoseconds Set as indicated in ATA8-ACS O Queue depth R 15-5 Reserved F 4-0 Maximum queue depth - 1 O Serial ATA capabilities F 15 Supports READ LOG DMA EXT as equivalent to READ LOG EXT F 14 Supports Device Automatic Partial to Slumber transitions F 13 Supports Host Automatic Partial to Slumber transitions F 12 Supports Native Command Queuing priority information F 11 Supports Unload while NCQ commands outstanding F 10 Supports Phy event counters F 9 Supports receipt of host-initiated interface power management requests F 8 Supports Native Command Queuing R 7-4 Reserved for future Serial ATA signaling speed grades F 3 1 = Supports Serial ATA Gen3 signaling speed (6.0 Gbps) F 2 1 = Supports Serial ATA Gen2 signaling speed (3.0 Gbps) F 1 1 = Supports Serial ATA Gen1 signaling speed (1.5 Gbps) F 0 Shall be cleared to zero O Serial ATA Additional capabilities R 15-6 Reserved F 5 Supports NCQ Queue Management Command F 4 Supports NCQ Streaming V 3-1 Coded value indicating current negotiated Serial ATA signal speed F 0 Shall be cleared to zero O Serial ATA features supported R 15-7 Reserved F 6 1 = Supports software settings preservation R 5 Reserved F 4 1 = Supports in-order data delivery F 3 1 = Device supports initiating interface power management F 2 1 = Supports DMA Setup Auto-Activate optimization F 1 1 = Supports non-zero buffer offsets in DMA Setup FIS F 0 Shall be cleared to zero O Serial ATA features enabled R 15-8 Reserved V 7 1 = Device Automatic Partial to Slumber transitions enabled V 6 1 = Software settings preservation enabled R 5 Reserved V 4 1 = In-order data delivery enabled Serial ATA Revision 3.0 Gold Revision page 480 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Word O/M F/V V 3 1 = Device initiating interface power management enabled V 2 1 = DMA Setup Auto-Activate optimization enabled V 1 1 = Non-zero buffer offsets in DMA Setup FIS enabled F 0 Shall be cleared to zero 80-87 Set as indicated in ATA8-ACS 88 15-6 Set as indicated in ATA8-ACS F 5 1=Ultra DMA mode 5 and below are supported F 4 1=Ultra DMA mode 4 and below are supported F 3 1=Ultra DMA mode 3 and below are supported F 2 1=Ultra DMA mode 2 and below are supported F 1 1=Ultra DMA mode 1 and below are supported F 0 1=Ultra DMA mode 0 is supported 89-92 Set as indicated in ATA8-ACS 93 V COMRESET result. The contents of this word shall be cleared to zero. 94-221 Set as indicated in ATA8-ACS 222 Transport Major Revision 0000h or FFFFh = device does not report version Bits Description F 15:12 Transport Type 0h = Parallel 1h = Serial 2h - Fh = Reserved 223 224-255 11:6 F5 F4 F3 F2 F1 F0 Reserved SATA Rev 3.0 SATA Rev 2.6 SATA Rev 2.5 SATA II: Extensions SATA 1.0a ATA8-AST F Transport Minor Revision Set as indicated in ATA8-ACS Key: M = Support of the word is mandatory. O = Support of the word is optional. F = the content of the word is fixed and does not change. For removable media devices, these values may change when media is removed or changed. V = the contents of the word is variable and may change depending on the state of the device or the commands executed by the device. X = the content of the word is vendor specific and may be fixed or variable. R = the content of the word is reserved and shall be zero. 13.2.1.1 Word 0 - 46: Set as indicated in ATA8-ACS 13.2.1.2 Word 47: Multiword PIO transfer Bits 15 through 8 of word 47 shall be set as indicated in ATA8-ACS. Serial ATA Revision 3.0 Gold Revision page 481 of 663 Bits 7 through 0 are used to indicate the maximum number of sectors that shall be transferred per interrupt on READ/WRITE MULTIPLE commands. This field shall be set to 16 or less. See section 10.3.10.1. 13.2.1.3 Word 48: Set as indicated in ATA8-ACS 13.2.1.4 Word 49: Capabilities Bits 15 through 12 of word 49 shall be set as indicated in ATA8-ACS. Bit 11 of word 49 is used to determine whether a device supports IORDY. This bit shall be set to one, indicating the device supports IORDY operation. Bit 10 of word 49 is used to indicate a device’s ability to enable or disable the use of IORDY. This bit shall be set to one, indicating the device supports the disabling of IORDY. Disabling and enabling of IORDY is accomplished using the SET FEATURES command. Bits 9 - 0 of word 49 shall be set as indicated in ATA8-ACS. 13.2.1.5 Words 50 - 52: Set as indicated in ATA8-ACS 13.2.1.6 Word 53: Field validity Bit 0 shall be set to one. Bit 1 of word 53 shall be set to one, the values reported in words 64 through 70 are valid. Any device that supports PIO mode 3 or above, or supports Multiword DMA mode 1 or above, shall set bit 1 of word 53 to one and support the fields contained in words 64 through 70. Bit 2 of word 53 shall be set to one indicating the device supports Ultra DMA and the values reported in word 88 are valid. Bits 15-3 are reserved. 13.2.1.7 Word 54 - 62: Set as indicated in ATA8-ACS 13.2.1.8 Word 63: Multiword DMA transfer Bits 2 - 0 of word 63 shall be set to one indicating that the device supports Multiword DMA modes 0, 1, and 2. Bits 15 – 3 shall be set as indicated in ATA8-ACS. 13.2.1.9 Word 64: PIO transfer modes supported Bits 1 - 0 of word 64 shall be set to one indicating that the device supports PIO modes 3 and 4. Bits 15 – 2 shall be set as indicated in ATA8-ACS. 13.2.1.10 Word 65: Minimum Multiword DMA transfer cycle time per word Shall be set to indicate 120 ns. 13.2.1.11 Word 66: Device recommended Multiword DMA cycle time Shall be set to indicate 120 ns. 13.2.1.12 Word 67: Minimum PIO transfer cycle time without flow control Shall be set to indicate 120 ns. Serial ATA Revision 3.0 Gold Revision page 482 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 13.2.1.13 Word 68: Minimum PIO transfer cycle time with IORDY Shall be set to indicate 120 ns. 13.2.1.14 Words 69-74: Set as indicated in ATA8-ACS 13.2.1.15 Word 75: Queue depth This word is as defined in the ATA8-ACS standard. The Native Command Queuing protocol supports at most 32 queued commands. With Native Command Queueing, the host shall issue only unique tag values for queued commands that have a value less than or equal to the value reflected in this field (e.g., for device reporting a value in this field of 15, corresponding to a maximum of 16 outstanding commands, the host shall never use a tag value greater than 15 when issuing Native Command Queueing commands). 13.2.1.16 Word 76: Serial ATA capabilities If not 0000h or FFFFh, the device claims compliance with the Serial ATA specification and supports the signaling speed indicated in bits 1-3. Since Serial ATA supports generational compatibility, multiple bits may be set. Bit 0 is reserved and shall be cleared to zero (thus a Serial ATA device has at least one bit cleared in this field and at least one bit set providing clear differentiation). If this field is not 0000h or FFFFh, words 77 through 79 shall be valid. If this field is 0000h or FFFFh the device does not claim compliance with the Serial ATA specification and Words 76 through 79 are not valid and shall be ignored. Bit 0 shall be cleared to zero. Bit 1 when set to one indicates that the device is a Serial ATA device and supports the Gen1 signaling speed of 1.5 Gbps. Bit 2 when set to one indicates that the device is a Serial ATA device and supports the Gen2 signaling speed of 3.0 Gbps. Bit 3 when set to one indicates that the device is a Serial ATA device and supports the Gen3 signaling speed of 6.0 Gbps. Bit 4-7 are reserved for future Serial ATA signaling speed grades and shall be cleared to zero. Bit 8 when set to one indicates that the Serial ATA device supports the Native Command Queuing scheme defined in section 13.6. Bit 9 when set to one indicates that the Serial ATA device supports the Partial and Slumber interface power management states when initiated by the host. Bit 10 when set to one indicates that the Serial ATA device supports Phy event counters. If the device supports Phy event counters, it shall support the Phy Event Counter Log (see 13.9.3) Bit 11 when set to one indicates that the device supports performing an unload/park of the heads upon reception of the IDLE IMMEDIATE command with the Unload Feature specified while NCQ commands are outstanding. This bit shall only be set to one if the device supports NCQ as shown in bit 8 of Word 76. Bit 12 when set to one indicates that the device supports the Priority field in the READ FPDMA QUEUED and WRITE FPDMA QUEUED commands and optimization based on this information. This bit shall only be set to one if the device supports NCQ as shown in bit 8 of Word 76. Serial ATA Revision 3.0 Gold Revision page 483 of 663 Bit 13 indicates that the device supports host Automatic Partial to Slumber transitions. The device shall tolerate a Partial exit latency up to the max Slumber exit latency. This allows the host to asynchronously transition from Partial to Slumber. If Word 76, bit 9 (supports receipt of host-initiated interface power management requests) is cleared to zero, then bit 13 shall be cleared to zero. Bit 14 indicates that the device supports Automatic Partial to Slumber transitions and may asynchronously transition from Partial to Slumber when enabled. If Word 78, bit 3 (supports initiating interface power management) is cleared to zero, then Word 76 bit 14 shall be cleared to zero. Bit 15 when set to one indicates that either the READ LOG DMA EXT and READ LOG EXT commands may be used in all cases with identical results (see 13.7). If IDENTIFY DEVICE word 119 bit 3 is cleared to zero, this bit shall be cleared to zero. If bit 15 is cleared to zero and the host issues the READ LOG DMA EXT command to read the Queued Error Log or the Phy Event Counters log, the device shall return command aborted. 13.2.1.17 Word 77: Serial ATA Additional capabilities Word 77 reports additional optional capabilities supported by the device. Support for this word is optional and if not supported, the word shall be zero indicating the device has no support for additional Serial ATA capabilities. Bit 0 shall be cleared to zero Bits 1-3 are a coded value that indicates the Serial ATA Phy speed at which the device is currently communicating. Table 76 defines these values: Coded Values Bit 3 Bit 2 Bit 1 0 0 0 0 0 1 0 1 0 0 1 1 All Non-Defined Values Description Signaling speed is not reported Gen1 signaling speed of 1.5 Gbps Gen2 signaling speed of 3.0 Gbps Gen3 signaling speed of 6.0 Gbps Reserved for future Serial ATA signaling speeds Table 76 - Coded Values for Negotiated Serial ATA Signaling Speed Note: In the case of system configurations that have more than one Phy link in the data path (eg. port multiplier), the indicated speed is only relevant for the link between the device Phy and its immediate host Phy. It is possible for each link in the data path to negotiate a different Serial ATA signaling speed. Bit 4, when set to one, indicates that the device supports NCQ Streaming. See the use of the ICC field by the READ FPDMA QUEUED and WRITE FPDMA QUEUED commands. This bit shall only be set to one if the device supports NCQ as shown in bit 8 of Word 76. Bit 5, when set to one indicates that the device supports use of the NCQ QUEUE MANAGEMENT command by the host. This bit shall only be set to one if the device supports NCQ as shown in bit 8 of Word 76. Bit 6-15 are reserved and shall be cleared to zero 13.2.1.18 Word 78: Serial ATA features supported Serial ATA Revision 3.0 Gold Revision page 484 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Word 78 reports the optional features supported by the device. Support for this word is optional and if not supported the word shall be zero indicating the device has no support for new Serial ATA capabilities. Bit 0 shall be cleared to zero. Bit 1 indicates whether the device supports the use of non-zero buffer offsets in the DMA Setup FIS. When set to one, the device supports transmission and reception of DMA Setup FISes with a non-zero value in the Buffer Offset field of the FIS. When cleared to zero, the device supports transmission and reception of the DMA Setup FIS only with the Buffer Offset field cleared to zero. Bit 2 indicates whether the device supports the use of the DMA Setup FIS Auto-Activate optimization as described in section 10.3.8.3.1. When set to one the device supports use of the Auto-Activate optimization and when cleared to zero the device does not support the AutoActivate optimization. Bit 3 indicates whether the device supports initiating power management requests to the host. When set to one the device supports initiating interface power management requests and when cleared to zero the device does not support initiating power management requests. A device may support reception of power management requests initiated by the host as described in the definition of bit 9 of Word 76 without supporting initiating such power management requests as indicated by this bit. Bit 4 indicates whether the device supports guaranteed in-order data delivery when non-zero buffer offsets are used in the DMA Setup FIS. When set to one, the device guarantees in-order data delivery for READ FPDMA QUEUED or WRITE FPDMA QUEUED commands when nonzero buffer offsets are used with multiple DMA Setup FIS. Target data is delivered in order, starting with the first LBA through command completion. When Bit 4 is cleared to zero, the device does not guarantee in-order data delivery when non-zero buffer offsets are enabled. In this case, data may be interleaved both within a command and across multiple commands. By default this field shall be zero. Bit 5 is reserved and shall be cleared to zero. Bit 6 indicates whether the device supports software settings preservation as defined in section 13.5. When set to one the device supports software settings preservation across COMRESET. When cleared to zero the device clears all software settings when a COMRESET occurs. Bit 7-15 are reserved and shall be cleared to zero 13.2.1.19 Word 79: Serial ATA features enabled Word 79 reports which optional features supported by the device are enabled. This word shall be supported if optional Word 78 is supported and shall not be supported if optional Word 78 is not supported. Bit 0 shall be cleared to zero. Bit 1 indicates whether device support for use of non-zero buffer offsets in the DMA Setup FIS is enabled. When set to one, device transmission of DMA Setup FISes with a non-zero value in the Buffer Offset field of the FIS is enabled. When cleared to zero, the device is permitted to transmit DMA Setup FIS only with the Buffer Offset field cleared to zero. By default this field shall be zero. Bit 2 indicates whether device support for use of the DMA Setup FIS Auto-Activate optimization as described in section 10.3.8.3.1 is enabled. When set to one, the device may utilize the Auto- Serial ATA Revision 3.0 Gold Revision page 485 of 663 Activate optimization. When cleared to zero the device shall not utilize the Auto-Activate optimization. By default, this field shall be zero. Bit 3 indicates whether device support for initiating power management requests to the host is enabled. When set to one the device may initiate power management transition requests. When cleared to zero the device shall not initiate interface power management requests to the host. This field shall be zero by default. Bit 4 indicates whether device support for guaranteed in-order data delivery when non-zero buffer offsets are used in the DMA Setup FIS is enabled. When set to one and non-zero buffer offset is enabled, the device may satisfy a READ FPDMA QUEUED or WRITE FPDMA QUEUED command by transmitting multiple DMA Setup FISes with non-zero buffer offset values where appropriate, provided that the target data is delivered in order, starting with the first LBA through command completion. When Bit 4 is cleared to zero, the device may interleave data both in a command and across multiple commands using non-zero buffer offsets if non-zero buffer offsets are enabled. By default this field shall be zero. Bit 5 is reserved and shall be cleared to zero. Bit 6 indicates whether device support for software settings preservation is enabled. When set to one the device shall preserve software settings across COMRESET. When cleared to zero the device shall clear software settings when COMRESET occurs. If the device supports software settings preservation this field shall be one by default. If the device does not support software settings preservation this field shall be zero by default. Bit 7 indicates whether or not device Automatic Partial to Slumber transitions are enabled. When enabled the device may asynchronously transition from Partial to Slumber. If Word 76, bit 14 (Supports Device Automatic Partial to Slumber transitions) is cleared to zero, then bit 7 shall be cleared to zero. If Word 79, bit 3 (Device initiating interface power management enabled) is cleared to zero, then bit 7 shall be cleared to zero. Bits 8-15 are reserved and shall be cleared to zero. 13.2.1.20 Words 80-87: Set as indicated in ATA8-ACS 13.2.1.21 Word 88: Ultra DMA modes Bits 5 - 0 of Word 88 shall be set to one indicating that the device supports Ultra DMA modes 0, 1, 2, 3, 4, and 5. Bits 15 – 5 shall be set as indicated in ATA8-ACS. 13.2.1.22 Words 89 - 92: Set as indicated in ATA8-ACS 13.2.1.23 Word 93: Hardware configuration test results Word 93 shall be set to 0000h indicating that the word is not supported. 13.2.1.24 Words 94-221: Set as indicated in ATA8-ACS. 13.2.1.25 Word 222: Transport Major Revision Bits (15:12) shall be set to 1h. 13.2.1.26 Word 223: Transport Minor Revision Set as indicated in ATA8-ACS. Serial ATA Revision 3.0 Gold Revision page 486 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 13.2.1.27 Words 224-255: Set as indicated in ATA8-ACS. 13.2.2 IDENTIFY PACKET DEVICE Word 0-48 49 50-52 53 54-62 63 64 65 66 67 68 69-75 76 Table 77 – IDENTIFY PACKET DEVICE information O/M F/V Set as indicated in ATA8-ACS M Capabilities 15-12 Set as indicated in ATA8-ACS F 11 Shall be set to one F 10 Shall be set to one 9-0 Set as indicated in ATA8-ACS Set as indicated in ATA8-ACS M Field validity R 15-3 Reserved F 2 1=the fields reported in word 88 are valid 0=the fields reported in word 88 are not valid F 1 1=the fields reported in words (70:64) are valid 0=the fields reported in words (70:64) are not valid F 0 Obsolete Set as indicated in ATA8-ACS M Multiword DMA transfer 15-3 Set as indicated in ATA8-ACS F 2 1= Multiword DMA mode 2 and below are supported F 1 1= Multiword DMA mode 1 and below are supported F 0 1= Multiword DMA mode 0 is supported M PIO transfer modes supported 15-2 Set as indicated in ATA8-ACS F 1-0 PIO modes 3 and 4 supported M Minimum Multiword DMA transfer cycle time per word F 15-0 Cycle time in nanoseconds M Manufacturer’s recommended Multiword DMA transfer cycle time F 15-0 Cycle time in nanoseconds M Minimum PIO transfer cycle time without flow control F 15-0 Cycle time in nanoseconds M Minimum PIO transfer cycle time with IORDY flow control F 15-0 Cycle time in nanoseconds Set as indicated in ATA8-ACS O Serial ATA capabilities F 15 Reserved F 14 Supports Device Automatic Partial to Slumber transitions F 13 Supports Host Automatic Partial to Slumber transitions R 12-11 Reserved F 10 Supports Phy event counters F 9 Supports receipt of host-initiated interface power management requests F 8 Reserved R 7-4 Reserved for future Serial ATA signaling speed grades F 3 1 = Supports Serial ATA Gen3 signaling speed (6.0 Gbps) F 2 1 = Supports Serial ATA Gen2 signaling speed (3.0 Gbps) F 1 1 = Supports Serial ATA Gen1 signaling speed (1.5 Gbps) Serial ATA Revision 3.0 Gold Revision page 487 of 663 Word 77 78 79 80-87 88 89-92 93 94-221 222 O/M F/V F 0 Shall be cleared to zero O Serial ATA Additional capabilities R 15-4 Reserved V 3-1 Coded value indicating current negotiated Serial ATA signal speed F 0 Shall be cleared to zero O Serial ATA features supported R 15-7 Reserved F 6 1 = Supports software settings preservation F 5 1 = Supports asynchronous notification R 4 Reserved F 3 1 = Device supports initiating interface power management F 2-1 Reserved F 0 Shall be cleared to zero O Serial ATA features enabled R 15-7 Reserved V 6 1 = Software settings preservation enabled V 5 1 = Asynchronous notification enabled R 4 Reserved V 3 1 = Device initiating interface power management enabled R 2-1 Reserved F 0 Shall be cleared to zero Set as indicated in ATA8-ACS 15-6 Set as indicated in ATA8-ACS F 5 1=Ultra DMA mode 5 and below are supported F 4 1=Ultra DMA mode 4 and below are supported F 3 1=Ultra DMA mode 3 and below are supported F 2 1=Ultra DMA mode 2 and below are supported F 1 1=Ultra DMA mode 1 and below are supported F 0 1=Ultra DMA mode 0 is supported Set as indicated in ATA8-ACS V COMRESET result. The contents of this word shall be cleared to zero. Set as indicated in ATA8-ACS Transport Major Revision 0000h or FFFFh = device does not report version Bits Description F 15:12 Transport Type 0h = Parallel 1h = Serial 2h - Fh = Reserved 223 224-255 11:6 F5 F4 F3 F2 F1 F0 Reserved SATA Rev 3.0 SATA Rev 2.6 SATA Rev 2.5 SATA II: Extensions SATA 1.0a ATA8-AST F Transport Minor Revision Set as indicated in ATA8-ACS Serial ATA Revision 3.0 Gold Revision page 488 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Key: M = Support of the word is mandatory. O = Support of the word is optional. F = the content of the word is fixed and does not change. For removable media devices, these values may change when media is removed or changed. V = the contents of the word is variable and may change depending on the state of the device or the commands executed by the device. X = the content of the word is vendor specific and may be fixed or variable. R = the content of the word is reserved and shall be zero. 13.2.2.1 Word 0 - 48: Set as indicated in ATA8-ACS 13.2.2.2 Word 49: Capabilities Bits 15 through 12 of word 49 shall be set as indicated in ATA8-ACS. Bit 11 of word 49 is used to determine whether a device supports IORDY. This bit shall be set to one, indicating the device supports IORDY operation. Bit 10 of word 49 is used to indicate a device’s ability to enable or disable the use of IORDY. This bit shall be set to one, indicating the device supports the disabling of IORDY. Disabling and enabling of IORDY is accomplished using the SET FEATURES command. Bits 9 - 0 of word 49 shall be set as indicated in ATA8-ACS. 13.2.2.3 Words 50 - 52: Set as indicated in ATA8-ACS 13.2.2.4 Word 53: Field validity Bit 0 shall be set to one. Bit 1 of word 53 shall be set to one, the values reported in words 64 through 70 are valid. Any device that supports PIO mode 3 or above, or supports Multiword DMA mode 1 or above, shall set bit 1 of word 53 to one and support the fields contained in words 64 through 70. Bit 2 of word 53 shall be set to one indicating the device supports Ultra DMA and the values reported in word 88 are valid. Bits 15-3 are reserved. 13.2.2.5 Word 54 - 62: Set as indicated in ATA8-ACS 13.2.2.6 Word 63: Multiword DMA transfer Bits 2 - 0 of word 63 shall be set to one indicating that the device supports Multiword DMA modes 0, 1, and 2. Bits 15 – 3 shall be set as indicated in ATA8-ACS. 13.2.2.7 Word 64: PIO transfer modes supported Bits 1 - 0 of word 64 shall be set to one indicating that the device supports PIO modes 3 and 4. Bits 15 – 2 shall be set as indicated in ATA8-ACS. 13.2.2.8 Word 65: Minimum Multiword DMA transfer cycle time per word Shall be set to indicate 120 ns. 13.2.2.9 Word 66: Device recommended Multiword DMA cycle time Shall be set to indicate 120 ns. Serial ATA Revision 3.0 Gold Revision page 489 of 663 13.2.2.10 Word 67: Minimum PIO transfer cycle time without flow control Shall be set to indicate 120 ns. 13.2.2.11 Word 68: Minimum PIO transfer cycle time with IORDY Shall be set to indicate 120 ns. 13.2.2.12 Words 69-75: Set as indicated in ATA8-ACS 13.2.2.13 Word 76: Serial ATA capabilities Word 76 shall have the content described for IDENTIFY DEVICE data word 76 13.2.2.14 Word 77: Serial ATA Additional capabilities Support for this word is optional and if not supported, the word shall be zero indicating the device has no support for additional Serial ATA capabilities. Bit 0 shall be cleared to zero Bit 1-3 are a coded value to indicate the current Serial ATA phy speed that device is communicating at. Table 76 defines these values. Note: In the case of system configurations that have more than one Phy link in the data path (eg. port multiplier), the indicated speed is only relevant for the link between the device Phy and its immediate host Phy. It is possible for each link in the data path to negotiate a different Serial ATA signaling speed. Bit 4-15 are reserved and shall be cleared to zero 13.2.2.15 Word 78: Serial ATA features supported Word 78 reports the optional features supported by the device. Support for this word is optional and if not supported the word shall be zero indicating the device has no support for new Serial ATA capabilities. Bit 0 shall be cleared to zero. Bit 1-2 are reserved and shall be cleared to zero. Bit 3 indicates whether the device supports initiating power management requests to the host. When set to one the device supports initiating interface power management requests and when cleared to zero the device does not support initiating power management requests. A device may support reception of power management requests initiated by the host as described in the definition of bit 9 of Word 76 without supporting initiating such power management requests as indicated by this bit. Bit 4 is reserved and shall be cleared to zero. Bit 5 indicates whether the device supports asynchronous notification to indicate to the host that attention is required. When set to one the device supports initiating notification events and when cleared to zero the device does not support initiating notification events. An example of an event Serial ATA Revision 3.0 Gold Revision page 490 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization that the device may need attention for includes a media change. notification is described in section 13.8. Asynchronous device Bit 6 indicates whether the device supports software settings preservation as defined in section 13.5. When set to one the device supports software settings preservation across COMRESET. When cleared to zero the device clears all software settings when a COMRESET occurs. Bit 7-15 are reserved and shall be cleared to zero. 13.2.2.16 Word 79: Serial ATA features enabled Word 79 shall have the content described for IDENTIFY DEVICE data word 79. 13.2.2.17 Words 80-87: Set as indicated in ATA8-ACS 13.2.2.18 Word 88: Ultra DMA modes Bits 5 - 0 of Word 88 shall be set to one indicating that the device supports Ultra DMA modes 0, 1, 2, 3, 4, and 5. Bits 15 – 5 shall be set as indicated in ATA8-ACS. 13.2.2.19 Word 89 - 92: Set as indicated in ATA8-ACS 13.2.2.20 Word 93: Hardware configuration test results Word 93 shall be set to 0000h indicating that the word is not supported. 13.2.2.21 Words 94-221: Set as indicated in ATA8-ACS. 13.2.2.22 Word 222: Transport Major Revision Bits (15:12) shall be set to 1h. 13.2.2.23 Word 223: Transport Minor Revision Set as indicated in ATA8-ACS. 13.2.2.24 Words 224-255: Set as indicated in ATA8-ACS. 13.2.3 Determining Support for Serial ATA Features Software should verify a device’s Serial ATA capabilities by reading the relevant bits in Words 7679 of the IDENTIFY (PACKET) DEVICE data. A device claims compliance with the Serial ATA specification by setting IDENTIFY (PACKET) DEVICE Word 76 appropriately. Although Serial ATA was first introduced in the ATA/ATAPI specification material in the ATA/ATAPI-7 revision, it cannot be assumed that when Word 80 (Major version number) of the IDENTIFY (PACKET) DEVICE data is read with support of ATA/ATAPI-7 or later that the device supports Serial ATA or any specific Serial ATA features. Serial ATA Revision 3.0 Gold Revision page 491 of 663 13.3 SET FEATURES Devices are informed of host capabilities and have optional features enabled/disabled through the SET FEATURES command defined in the ATA8-ACS standard. Serial ATA features are controlled using a features value as defined in Table 78. Table 78 - Features enable/disable values Features(7:0) Value 10h 90h Description Enable use of Serial ATA feature Disable use of Serial ATA feature Count(7:0) contains the specific Serial ATA feature to enable or disable. The specific Serial ATA features in which SET FEATURES is applicable are defined in Table 79. Count(7:0) Value 00h 01h 02h 03h 04h 05h 06h 07h 08h - FFh Table 79 - Feature identification values Description Reserved Non-zero buffer offset in DMA Setup FIS DMA Setup FIS Auto-Activate optimization Device-initiated interface power state transitions Guaranteed In-Order Data Delivery Asynchronous Notification Software Settings Preservation Device Automatic Partial to Slumber transitions Reserved for future Serial ATA definition 13.3.1 Enable/Disable Non-Zero Offsets in DMA Setup A Count(7:0) value of 01h is used by the host to enable or disable non-zero buffer offsets in the DMA Setup FIS when the device utilizes the First-party DMA mechanism (see section 13.6.1.2). By default, non-zero buffer offsets in the DMA Setup FIS are disabled. Enabling non-zero buffer offsets in the DMA Setup FIS is useful for performing out of order data delivery within commands, e.g. delivering the last half of the data before the first half of the data, or to support segmentation of large First-party DMA operations into multiple data phases, i.e. to effectively allow sharing of the SATA link during Data I/O, e.g. to provide a mechanism for the host to transmit additional READ FPDMA QUEUED or WRITE FPDMA QUEUED commands to the device for re-order consideration. The enable/disable state for non-zero offsets in DMA Setup FISes shall be preserved across software reset. The enable/disable state for non-zero offsets in DMA Setup FISes shall be reset to its default state upon COMRESET. 13.3.2 Enable/Disable DMA Setup FIS Auto-Activate Optimization A Count(7:0) value of 02h is used by the host to enable or disable the DMA Setup FIS optimization for automatically activating transfer of the first host-to-device Data FIS following a DMA Setup FIS with a host-to-device transfer direction. For transfers from the host to the device, First-party DMA transfers require a sequence of DMA Setup FIS followed by a DMA Activate FIS to initiate the transfer. The Auto-Activate optimization allows the DMA Setup FIS operation to imply immediate activation thereby eliminating the need for the additional separate DMA Activate FIS to start the transfer. Enabling the optimization notifies the device that the host bus adapter implementation allows the DMA Setup FIS to include the Auto-Activate bit to trigger immediate transfer following receipt and processing of the DMA Setup FIS. By default, the optimization is disabled. See section 10.3.8.3.1 for additional details. The enable/disable state for the auto- Serial ATA Revision 3.0 Gold Revision page 492 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization activate optimization shall be preserved across software reset. The enable/disable state for the auto-activate optimization shall be reset to its default state upon COMRESET. 13.3.3 Enable/Disable Device-Initiated Interface Power State Transitions A Count(7:0) value of 03h is used by the host to enable or disable device initiation of interface power state transitions. By default, the device is not permitted to attempt interface power state transitions by issuing PMREQ_P or PMREQ_S to the host. The host may enable device P P initiation of such interface power state transitions for such cases where it may be desirable for the device to attempt initiating such transitions. The enable/disable state for device initiated power management shall persist across software reset. The enable/disable state shall be reset to its default disabled state upon COMRESET. If device initiated interface power management is enabled, the device shall not attempt to initiate an interface power state transition between reset and the delivery of the device reset signature. 13.3.4 Enable/Disable Guaranteed in-Order Data Delivery A Count(7:0) value of 04h is used by the host to enable or disable guaranteed in-order data delivery when the device utilizes the First-party DMA mechanism and non-zero buffer offsets in the DMA Setup FIS. By default, guaranteed in-order data delivery is disabled. Enabling guaranteed in-order data delivery is useful for segmenting large I/O processes into multiple atomic data phases using non-zero buffer offsets in the DMA Setup FIS, while minimizing the complexity that may be imposed on the host with out-of-order data delivery. The enable/disable state for guaranteed in-order data delivery shall be preserved across software reset. The enable/disable state for guaranteed in-order data delivery shall be reset to its default state upon COMRESET. 13.3.5 Enable/Disable Asynchronous Notification A Count(7:0) value of 05h is used by the host to enable or disable asynchronous notification. By default, asynchronous notification is disabled. The host may enable asynchronous notification in order to allow the device to request attention without the host polling. As an example, this may be useful to avoid polling for media change events in ATAPI devices. The enable/disable state for asynchronous notification shall be preserved across software reset. The enable/disable state for asynchronous notification shall be reset to its default state upon COMRESET. 13.3.6 Enable/Disable Software Settings Preservation A Count(7:0) value of 06h is used by the host to enable or disable software settings preservation, as defined in section 13.5. By default, if the device supports software settings preservation the feature is enabled on power-up. The enable/disable state for software settings preservation shall persist across software reset. The enable/disable state for software settings preservation shall be reset to its default state upon COMRESET. The host may disable software settings preservation in order to not preserve software settings across COMRESET (and make COMRESET equivalent to hardware reset in Parallel ATA). 13.3.7 Enable/Disable Device Automatic Partial to Slumber Transitions A Count(7:0) value of 07h is used by the host to enable or disable Device Automatic Partial to Slumber transitions. By default, if the device supports Device Automatic Partial to Slumber transitions the feature is disabled on power-up. The enable/disable state for Device Automatic Partial to Slumber transitions shall persist across software reset. The enable/disable state for Automatic Partial to Slumber transitions shall be reset to its default state upon COMRESET. Device Automatic Partial to Slumber transitions shall not be enabled if Device-Initiated Interface Power State transitions are disabled. Attempting to enable Automatic Partial to Slumber Serial ATA Revision 3.0 Gold Revision page 493 of 663 transitions while Device-Initiated Interface Power State transitions are disabled will result in the device aborting the Set Features command. Attempting to disable Device Automatic Partial to Slumber transitions when it is already disabled will have no effect and the device shall return successful completion of the Set Features command. 13.4 Device Configuration Overlay 13.4.1 Device Configuration Overlay Identify Figure 202 defines additional features and capabilities that support may be controlled for using the DEVICE CONFIGURATION IDENTIFY command in the ATA8-ACS standard. The device is only required to support setting these features if the device reports support for Device Configuration Overlay in either IDENTIFY DEVICE or IDENTIFY PACKET DEVICE, respectively. Word Description 0-7 As defined in the ATA8-ACS standard 8 Serial ATA command / feature sets supported 15-7 Reserved (0) 6 1 = Reporting support for NCQ QUEUE MANAGEMENT1 is allowed is changeable 5 1 = Reporting support for Automatic Partial to Slumber transitions is changeable 4 1 = Reporting support for software settings preservation is changeable 3 1 = Reporting support for asynchronous notification is changeable 2 1 = Reporting support for interface power management is changeable 1 1 = Reporting support for non-zero buffer offsets in DMA Setup FIS1 is changeable 0 1 = Reporting support for Native Command Queuing1 is changeable 9 Reserved for Serial ATA 10-255 As defined in the ATA8-ACS standard NOTE: 1. Applicable to non-PACKET devices only – i.e. IDENTIFY DEVICE. Figure 202 –DEVICE CONFIGURATION IDENTIFY data structure WORD 8: Serial ATA command / feature sets supported This word describes which features for which support is changeable. A feature may be supported but not be changeable. If bit 0 of word 8 is set to one, then support for Native Command Queuing is changeable. The setting of this bit is applicable to non-PACKET devices only. If bit 1 of word 8 is set to one, then support for non-zero buffer offsets in the DMA Setup FIS is changeable. The setting of this bit is applicable to non-PACKET devices only. If bit 2 of word 8 is set to one, then suport receiving host initiated power management requests and/or sending device initiated power management requests is changeable. If bit 3 of word 8 is set to one, then support for asynchronous notification is changeable. Serial ATA Revision 3.0 Gold Revision page 494 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization If bit 4 of word 8 is set to one, then support for software settings preservation is changeable. If bit 5 of word 8 is set to one, then support for Automatic Partial to Slumber transitions is changeable. If bit 6 of word 8 is set to one, then support for the NCQ QUEUE MANAGEMENT command is changeable. Bits 7-15 are reserved and shall be cleared to zero. WORD 9: Reserved for Serial ATA This word is reserved for Serial ATA and all bits shall be cleared to zero. 13.4.2 Device Configuration Overlay Set Figure 203 defines additional features and capabilities that support may be controlled for using the DEVICE CONFIGURATION SET command in the ATA8-ACS standard. The device is only required to support setting these features if the device reports support for Device Configuration Overlay in either IDENTIFY DEVICE or IDENTIFY PACKET DEVICE, respectively. Word Description 0-7 As defined in the ATA8-ACS standard 8 Serial ATA command / feature sets supported 15-7 Reserved 6 1 = Reporting support for the NCQ QUEUE MANAGEMENT command1 is allowed 5 1 = Reporting support for Automatic Partial to Slumber transitions is allowed 4 1 = Reporting support for software settings preservation is allowed 3 1 = Reporting support for asynchronous notification is allowed 2 1 = Reporting support for interface power management is allowed 1 1 = Reporting support for non-zero buffer offsets in DMA Setup FIS1 is allowed 0 1 = Reporting support for Native Command Queuing1 is allowed 9 Reserved for Serial ATA 10-255 As defined in the ATA8-ACS standard NOTE: 1. Applicable to non-PACKET devices only – i.e. IDENTIFY DEVICE. Figure 203 - DEVICE CONFIGURATION SET data structure WORD 8: Serial ATA command / feature sets supported This word enables configuration of command sets and feature sets. If bit 0 of word 8 is cleared to zero, then the device shall: a) disable support for Native Command Queuing; b) clear word 76 bits 8,11,and 12 in the IDENTIFY DEVICE data to zero; c) clear word 78 bits 1, 2, and 4 in the IDENTIFY DEVICE data to zero; d) clear word 79 bits 1, 2 and 4 in the IDENTIFY DEVICE data to zero; and Serial ATA Revision 3.0 Gold Revision page 495 of 663 e) if NCQ is disabled and READ FPDMA QUEUED or WRITE FPDMA QUEUED is issued to the device, the device shall abort the command with the ERR bit set to one in the Status field and the ABRT bit set to one in the Error field. The setting of this bit is applicable to non-PACKET devices only. If bit 1 of word 8 is cleared to zero, then the device shall a) disable support for non-zero buffer offsets in the DMA Setup FIS; b) clear word 78 bits 1 and 4 in the IDENTIFY DEVICE data to zero; c) clear word 79 bits 1 and 4in the in the IDENTIFY DEVICE data to zero; and d) if non-zero buffer offsets in the DMA Setup FIS are disabled, the device shall only issue a DMA Setup FIS that has the DMA Buffer Offset field cleared to zero. The setting of this bit is applicable to non-PACKET devices only. If bit 2 of word 8 is cleared to zero, then the device shall: a) disable support for receiving host initiated power management requests and shall not support device initiated power management requests; b) clear word 76 bit 9 of IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data to zero; c) clear word 78 bit 3 of IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data to zero; d) clear word 79 bit 3 of IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data to zero; and e) if interface power management requests are disabled, the device shall respond with PMNAKP to any interface power management requests and the device shall not issue PMREQ_PP or PMREQ_SP to the host. If bit 3 of word 8 is cleared to zero, then the device shall: a) disable support for asynchronous notification; b) clear word 78 bit 5 of IDENTIFY PACKET DEVICE data to zero; c) clear word 79 bit 5 of IDENTIFY PACKET DEVICE data to zero; and d) when asynchronous notification is disabled, the device shall not initiate a Set Device Bits FIS with the Notification bit set to one. If bit 4 of word 8 is cleared to zero, then the device shall: a) disable support for software settings preservation; b) clear word 78 bit 6 of IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data to zero; c) clear word 79 bit 6 of IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data to zero; and d) when software settings preservation is disabled, the device shall not preserve any software settings that are normally cleared following a COMRESET. If bit 5 of word 8 is cleared to zero, then the device shall: a) disable support for Automatic Partial to Slumber transitions; b) clear word 76 bits 13 and 14 of IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data to zero; c) clear word 79 bit 7 of IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data to zero; and d) when Automatic Partial to Slumber transitions are disabled neither the device nor host may transition to Slumber from Partial without first entering Active. If bit 5 of word 8 is set to one and bit 2 or word 8 is cleared to zero, then the device shall return command aborted. If bit 6 of word 8 is cleared to zero, then the device shall: a) disable support for the NCQ QUEUE MANAGEMENT command; Serial ATA Revision 3.0 Gold Revision page 496 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization b) clear word 77 bit 5 of IDENTIFY DEVICE data to zero; and c) if an NCQ QUEUE MANAGEMENT command is issued to the device, the device shall return command aborted. Bits (15:7) of word 8 are reserved and shall be cleared to zero. WORD 9: Reserved for Serial ATA This word is reserved for Serial ATA and all bits shall be cleared to zero. 13.5 Software Settings Preservation (Optional) When a device is enumerated, software configures the device using SET FEATURES and other commands. These software settings are often preserved across software reset but not necessarily across COMRESET. In Parallel ATA, only commanded hardware resets may occur, thus legacy mode software only reprograms settings that are cleared for the particular type of reset it has issued. In Serial ATA, COMRESET is equivalent to hardware reset and a noncommanded COMRESET may occur if there is an asynchronous loss of signal. Since COMRESET is equivalent to hardware reset, in the case of an asynchronous loss of signal some software settings may be lost without legacy mode software knowledge. In order to avoid losing important software settings without legacy mode driver knowledge, the software settings preservation ensures that the value of important software settings is maintained across a COMRESET. Software settings preservation may be enabled or disabled using SET FEATURES with a subcommand code of 06h (refer to section 13.3.6). If a device supports software settings preservation, the feature shall be enabled by default. The software settings that shall be preserved across COMRESET are listed below. The device is only required to preserve the indicated software setting if it supports the particular feature/command the setting is associated with. INITIALIZE DEVICE PARAMETERS: Device settings established with the INITIALIZE DEVICE PARAMETERS command. This command is obsolete in the ATA8-ACS standard, and was last defined in the ATA/ATAPI-5 standard. Power Management Feature Set Standby Timer: The Standby timer used in the Power Management feature set. Read/Write Stream Error Log: The Read Stream Error Log and Write Stream Error Logs (accessed using the GPL feature set commands). Security mode state: The security mode state established by Security Mode feature set commands (refer to the ATA8-ACS standard). The device shall not transition to a different security mode state based on a COMRESET. For example, the device shall not transition from the SEC5: Unlocked / not Frozen state to state SEC4: Security enabled / Locked when a COMRESET occurs, instead the device shall remain in the SEC5: Unlocked / not Frozen state. SECURITY FREEZE LOCK: The Frozen mode setting established by the SECURITY FREEZE LOCK command. SECURITY UNLOCK: The unlock counter that is decremented as part of a failed SECURITY UNLOCK command attempt. SET MAX ADDRESS (EXT): The maximum LBA specified in SET MAX ADDRESS or SET MAX ADDRESS EXT. SET FEATURES (Write Cache Enable/Disable): The write cache enable/disable setting established by the SET FEATURES command with subcommand code of 02h or 82h. SET FEATURES (Set Transfer Mode): PIO, Multiword, and UDMA transfer mode settings established by the SET FEATURES command with subcommand code of 03h. Serial ATA Revision 3.0 Gold Revision page 497 of 663 SET FEATURES (Advanced Power Management Enable/Disable): The advanced power management enable/disable setting established by the SET FEATURES command with subcommand code of 05h or 85h. The advanced power management level established in the Count(7:0) register when advanced power management is enabled (SET FEATURES subcommand code 05h) shall also be preserved. SET FEATURES (Read Look-Ahead): The read look-ahead enable/disable setting established by the SET FEATURES command with subcommand code of 55h or AAh. SET FEATURES (Release Interrupt): The release interrupt enable/disable setting established by the SET FEATURES command with a subcommand code of 5Dh or DDh. SET FEATURES (SERVICE Interrupt): The SERVICE interrupt enable/disable setting established by the SET FEATURES command with a subcommand code of 5Eh or DEh. SET FEATURES (Reverting to Defaults): The reverting to power-on defaults enable/disable setting established by the SET FEATURES command with a subcommand code of CCh or 66h. SET MULTIPLE MODE: The block size established with the SET MULTIPLE MODE command. NCQ QUEUE MANAGEMENT (Deadline Handling): The state of WDNC and RDNC. Write-Read-Verify feature set: The contents of IDENTIFY DEVICE data word 120 bit 1, words 210-211, and word 220 bits (7:0). The device shall not return to its Write-Read-Verify factory default setting after processing a COMRESET. 13.5.1 Warm Reboot Considerations (Informative) During a system reboot, the security settings maintained by software settings preservation may cause an error condition. Some system implementations choose to reboot the system by sending a COMRESET to the device. When the device has software settings preservation enabled, the security settings remain in the Unlock / Frozen State (SEC6). When in the Unlock / Frozen State (SEC6), system software sending a SECURITY UNLOCK command with the password is aborted by the device. System software should implement recommendations in this section to avoid the password entered by the user being aborted. It is recommended that system software not prompt for the user password during a warm reboot. If system software detects that the device is in the SEC5 state during the warm reboot, the SECURITY FREEZE command may be issued by system software to enter the Unlock / Frozen State (SEC6). The SEC states and SECURITY commands are described in ATA8-ACS. Note that these recommendations do not apply for external SATA devices. 13.6 Native Command Queuing (Optional) This section defines a simple and streamlined command queuing model for Serial ATA. The native queuing definition utilizes the reserved 32-bit field in the Set Device Bits FIS to convey the pending status for each of up to 32 outstanding commands. The BSY bit in the Status register conveys only the device’s readiness to receive another command, and does not convey the completion status of queued commands. Upon receipt of a new command, the device clears the BSY bit to zero before proceeding to execute received commands. The 32 protocol specific bits in the Set Device Bits FIS are handled as a 32-element array of active command bits (referred to as ACT bits), one for each possible outstanding command, and the array is bit significant such that bit “n” in the array corresponds to the pending status of the command with tag “n.” Serial ATA Revision 3.0 Gold Revision page 498 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Data returned by the device (or transferred to the device) for queued commands use the First Party DMA mechanism to cause the host controller to select the appropriate destination/source memory buffer for the transfer. The memory handle used for the buffer selection is the same as the tag that is associated with the command. For traditional desktop host controllers, the handle may be used to index into a vector of pointers to pre-constructed scatter/gather lists (often referred to as physical region descriptor tables or simply PRD tables) in order to establish the proper context in the host’s DMA engine. The First-party DMA Data Phase is defined as the period from reception of a DMA Setup FIS until either the associated transfer count is exhausted or the ERR bit in the shadow Status register is set. During this period the host may not issue new commands to the device nor may the device signal new command completions to the host. Status is returned by updating the 32-element bit array in the Set Device Bits FIS for successful completions. For failed commands, the device halts processing commands allowing host software or controller firmware to intervene and resolve the source of the failure, by using the general purpose logging feature set, before processing is again explicitly restarted. Devices supporting Native Command Queuing shall implement, and report support for, the general purpose logging feature set as defined in ATA8-ACS. In addition, the device shall implement the Queued Error Log. 13.6.1 Definition 13.6.1.1 Command Issue Mechanism The Serial ATA transmission protocol is sensitive to the state of the BSY bit in the Shadow Status register that provides write protection to the shared Shadow Command Block registers. Since the Shadow Command Block registers may be safely written only when the BSY bit is cleared to zero, the BSY bit conventions defined in the Transport layer shall be adhered to, and issuing a new command shall only be attempted when the BSY bit is cleared to zero. When the BSY bit in the Shadow Status register is cleared to zero, another command may be issued to the device. The state of the BSY bit in the Shadow Status register shall be checked prior to attempting to issue a new queued command. If the BSY bit is set to one, issuing the next command shall be deferred until the BSY bit is cleared to zero. It is desirable to minimize such command issue deferrals, so devices should clear the BSY bit to zero in a timely manner. Host controllers may have internal designs that mitigate the need for host software to block on the state of the BSY bit. The native queuing commands include a tag value that identifies the command. The tag value is in the range 0 through 31 inclusive, and is conveyed in the Register – Host to Device FIS when the command is issued. For devices that report a value less than 31 in their IDENTIFY DEVICE word 75, the host shall issue only unique tag values that are less than or equal to the value reported. Upon issuing a new native queued command, the bit in the SActive register corresponding to the tag value of the command being issued shall be set to one by the HBA prior to the command being transmitted to the device. Section 14.1.4 describes the SActive register and the access conventions for it. Upon accepting the command, the device shall clear the BSY bit to zero when it is prepared to receive another command by transmitting a Register – Device to Host FIS to the host with the BSY bit cleared in the Status field of the FIS, and the Interrupt bit cleared to zero. 13.6.1.2 Data Delivery Mechanism The First-party DMA mechanism is used by the device to transmit (or receive) data for an arbitrary queued command. The command’s tag value shall also be the DMA Buffer Identifier used to uniquely identify the source/destination memory buffer for the transfer. Serial ATA Revision 3.0 Gold Revision page 499 of 663 The DMA Setup FIS is used by the device to select the proper transfer buffer prior to each data transfer. Only a single DMA Setup FIS is required at the beginning of each transfer and if the transfer spans multiple Data FISes a new DMA Setup FIS is not required before each Data FIS. Serial ATA host controller hardware shall account for the DMA Setup FIS buffer identifier being a value between 0 and 31 and the host controller shall select the proper transfer buffer based on such an index. For data transfers from the host to the device, an optimization to the First-party DMA mechanism is included to eliminate one transaction by allowing the requested data to immediately be transmitted to the device following such a request without the need for a subsequent DMA Activate FIS for starting the flow of data. This optimization to the First-party DMA mechanism is defined in section 10.3.8.3.1. If non-zero buffer offsets in the DMA Setup FIS are not enabled (see section 13.3.1) or not supported (see section 13.2.1), the data transfer for a command shall be satisfied to completion following a DMA Setup FIS before data transfer for a different command may be started. Host controllers are not required to preserve DMA engine context upon receipt of a new DMA Setup FIS, and if non-zero buffer offsets are not enabled or not supported, a device cannot resume data transfer for a previously abandoned context at the point where it left off. If the host controller hardware supports non-zero buffer offsets in the DMA Setup FIS and use of non-zero offsets is enabled, and if guaranteed in-order data delivery is either not supported by the device (see section 13.2.1) or is disabled (see section 13.3.4), the device may return (or receive) data for a given command out of order (i.e. returning data for the last half of the command first). In this case the device may also interleave partial data delivery for multiple commands provided the device keeps track of the appropriate buffer offsets. For example, data for the first half of command 0 may be delivered followed by data for the first half of command 1 followed by the remaining data for command 0. By default use of non-zero buffer offsets is disabled. See section 13.3.1 for information on enabling non-zero buffer offsets for the DMA Setup FIS. If the host controller hardware supports non-zero buffer offsets in the DMA Setup FIS and use of non-zero offsets is enabled, and if the device supports guaranteed in-order data delivery and guaranteed in-order data delivery is enabled, the device may use multiple DMA Setup FISes to satisfy a particular I/O process, but if multiple DMA Setup FISes are used, the data shall be delivered in-order, starting at the first LBA. In this case the device may not interleave partial data delivery for either individual or multiple commands. For example, data for the first half of a command may be delivered using one DMA Setup FIS and one or more subsequent Data FISes, followed by the remaining data for that command, delivered using a second DMA Setup FIS and one or more subsequent Data FISes. Non-zero buffer offsets are used as in the more general out-of-order data delivery case described above. By default use of guaranteed in-order data delivery is disabled. For selecting the memory buffer for data transfers, the DMA Setup FIS is issued by the device. The DMA Setup FIS fields are defined in Figure 204 (see also section 10.3.8). Serial ATA Revision 3.0 Gold Revision page 500 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 0 Reserved (0) Reserved (0) A I D Reserved (0) 1 0h 2 0h 3 Reserved (0) 4 DMA Buffer Offset 5 DMA Transfer Count 6 Reserved (0) FIS Type (41h) TAG Figure 204 – DMA Setup FIS definition for memory buffer selection Field Definitions FIS Type As defined in section 10.3.8. D As defined in section 10.3.8. Since the DMA Setup FIS is only issued by the device for the queuing model defined here, the value in the field is defined as 1 = device to host transfer (write to host memory), 0 = host to device transfer (read from host memory). A As defined in section 10.3.8, including additional details in section 10.3.8.3.1. For DMA Setup with transfer direction from device to host, this bit shall be zero. TAG This field is used to identify the DMA buffer region in host memory to select for the data transfer. The low order 5 bits of the DMA Buffer Identifier Low field shall be set to the TAG value corresponding to the command TAG for which data is being transferred. The remaining bits of the DMA Buffer Identifier Low/High shall be cleared to zero. The 64-bit Buffer Identifier field defined in the DMA Setup FIS in section 10.3.8 is used to convey a TAG value that occupies the five leastsignificant bits of the field. DMA Buffer Offset As defined in section 10.3.8. The device may specify a non-zero value in this field only if the host indicates support for it through the SET FEATURES mechanism defined in section 13.3. Data is transferred to/from sequentially increasing logical addresses starting at the specified offset in the specified buffer. DMA Transfer Count As defined in section 10.3.8. The value shall accurately reflect the length of the data transfer to follow. Refer to section 10.3.11.2 for special considerations if the transfer count is for an odd number of words. Devices shall not set this field to 0h; a value of 0h for this field is illegal and results in indeterminate behavior. I Interrupt Native Command Queuing does not make use of an interrupt following the data transfer phase (after the transfer count is exhausted). The Interrupt bit shall be cleared to zero. R/Reserved All reserved fields shall be cleared to zero. 13.6.1.3 Status Return Mechanism Serial ATA Revision 3.0 Gold Revision page 501 of 663 For maximum efficiency, the status return mechanism is not interlocked (does not include a handshake) while at the same time ensuring no status notifications are lost or overwritten (i.e. status notifications are race-free). The status return mechanism relies on an array of ACT bits – one ACT bit to convey the active status for each of the 32 possible outstanding commands, resulting in a 32-bit ACT status field. The 32-bit reserved field in the Set Device Bits FIS as defined in section 10.3.6 is defined as the SActive field and is used to convey command completion information for updating the ACT bit array. The zero bit position in the 32-bit field corresponds to the ACT bit for the command with tag value of zero. Host software shall check the SActive register (containing the ACT bit array) when checking status in order to determine which command(s) have completed since the last time the host processed a command completion. It is possible for multiple commands to indicate completion by the time the host checks the status due to the software latencies in the host (i.e. by the time the host responds to one completion notification, another command may have completed). Only successfully completed commands indicate their status using this mechanism – failed commands use an additional mechanism described in 13.6.3.3.1.1 and 13.6.3.7.1.2 to convey error information as well as the affected command tag. The Queued Error Log is used to convey additional queued command error information as outlined in 13.7. 13.6.1.4 Priority Host knowledge of I/O priority may be transmitted to the device as part of the command. There are two priority values for NCQ commands, normal and high. When the host marks an NCQ command as high priority, the host is requesting a better quality of service for that command than commands issued with normal priority. The classes are forms of soft priority. The device may choose to complete a normal priority command before an outstanding high priority command, although preference should be given to the high priority commands. One example where a normal priority command may be completed before a high priority command is when the normal priority command is a cache hit, whereas the high priority command requires access of the device media. The priority class is specified in the PRIO bit for NCQ commands (READ FPDMA QUEUED and WRITE FPDMA QUEUED). This bit may specify either the normal priority or high priority value. If a command is marked by the host as high priority, the device should attempt to provide better quality of service for the command. It is not required that devices process all high priority requests before satisfying normal priority requests. The device should complete high priority requests in a more timely fashion than normal and isochronous requests. The device should complete isochronous requests prior to its associated deadline. 13.6.1.5 Unload When using Native Command Queuing in a laptop environment, the host needs to be able to park the head due to excessive movement (e.g. the laptop being dropped). This section defines a mechanism that the host may use to park the heads when NCQ commands are outstanding in the device. The typical time for completion of the unload operation is defined in ATA/ATAPI-7 clause 6.20.10. When NCQ commands are outstanding, the device is able to accept the IDLE IMMEDIATE command with the Unload Feature defined in ATA/ATAPI-7 clause 6.20. Upon reception of this command with the Unload Feature specified, the device shall: 1. Unload/park the heads immediately. 2. Respond to the host with a Register – Device to Host FIS with the ERR bit set to one in the Status register since this is a non-queued command. Serial ATA Revision 3.0 Gold Revision page 502 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization When the host receives the error indication, it should proceed to read the Queued Error Log (see 13.7). In the Queued Error Log, the device shall indicate whether the error was due to receiving an UNLOAD and whether the UNLOAD was executed. The device shall not load the heads to the media when reading the Queued Error Log. The Queued Error Log indicates whether the device has accepted the Unload and is in the process of executing the command. To get a definitive indication of Unload completion (and success), the IDLE IMMEDIATE command with the Unload Feature needs to be issued again after the Queued Error Log has been read. After the Queued Error Log has been read, there are no NCQ commands outstanding and the NCQ error is cleared such that the IDLE IMMEDIATE command with the Unload Feature will be processed normally and a successful status will be returned when the unload process completes successfully. There may be a delay in issuing the IDLE IMMEDIATE command with the Unload feature to the device if the device is currently performing a data transfer for a previously issued NCQ command. If the device happens to be executing extensive data error recovery procedures, this delay could be longer than acceptable. However, this same issue may occur when a non-queued data command is outstanding and the device is performing error recovery procedures. 13.6.2 Intermixing Non-Native Queued Commands and Native Queued Commands The host shall not issue a non-native queued command while a native queued command is outstanding. Upon receiving a non-native queued command while a native queued command is outstanding, the device shall signal the error condition to the host by transmitting a Register FIS to the host with the ERR and ABRT bits set to one and the BSY bit cleared to zero in the Status field of the FIS and halt command processing as described in section 13.6.3.4 except as noted below. Non-native queued commands include all commands other than the READ FPDMA QUEUED, WRITE FPDMA QUEUED, and NCQ QUEUE MANAGEMENT commands defined in 13.6.3.1, 13.6.3.5 and 13.6.3.8. Reception of a command to read the Queued Error Log (see 13.7) after an error has occurred shall cause any outstanding Serial ATA native queued commands to be aborted, and the device shall perform necessary state cleanup to return to a state with no commands pending. The device shall clear all bits in the SActive register by transmitting a Set Device Bits FIS to the host with all the bits in the SActive field set to one (i.e. FFFFFFFFh). After reading the Queued Error Log, the device shall be prepared to execute subsequently issued queued commands regardless of any previous errors on a queued command. In the case that a command to read the Queued Error Log is issued while a native queued command is outstanding AND no error was previously reported by the device, the device shall signal an error condition. The receipt of this command when no error is outstanding shall be handled as any other non-native queued command when a native queued command is outstanding. In this case, a subsequent command to read the Queued Error Log is required to recover from the error. Serial ATA Revision 3.0 Gold Revision page 503 of 663 13.6.3 Command Definitions 13.6.3.1 READ FPDMA QUEUED Queued native read commands make use of a new command. The new command supports LBA mode only and uses 48-bit addressing only. The format of the new command is defined in Figure 205. Register Features(7:0) Features(15:8) Count(7:0) Count(15:8) LBA(7:0) LBA(31:24) LBA(15:8) LBA(39:32) LBA(23:16 LBA(47:40) ICC Device Command 7 6 PRIO(1:0) FUA 1 5 4 3 2 1 0 Sector Count 7:0 Sector Count 15:8 TAG Reserved Reserved LBA 7:0 LBA 31:24 LBA 15:8 LBA 39:32 LBA 23:16 LBA 47:40 ICC(7:0) Res 0 Reserved 60h Figure 205 – READ FPDMA QUEUED command definition TAG The TAG value shall be assigned by host software to be different from all other TAG values corresponding to outstanding commands. The assigned TAG value shall not exceed the value specified in IDENTIFY DEVICE word 75. PRIO ICC The Priority (PRIO) value is assigned by the host based on the priority of the command issued. The device should complete high priority requests in a more timely fashion than normal and isochronous requests. The device should complete isochronous requests prior to its associated deadline. 00b Normal Priority 01b Isochronous – deadline dependent priority 10b High priority 11b Reserved The Isochronous Command Completion (ICC) field is valid when PRIO is set to a value of 01b. It is assigned by the host based on the intended deadline associated with the command issued. When a deadline has expired, the device shall continue to complete the command as soon as possible. This behavior may be modified by the host if the device supports the NCQ QUEUE MANAGEMENT command (see 13.6.3.8) and supports the Deadline Handling subcommand (see 13.6.3.8.2). This subcommand allows the host to set whether the device shall abort (or continue processing) commands that have exceeded the time set in ICC. There are several parameters encoded in the ICC field: Fine or Coarse timing, Interval and the Max Time. The Interval indicates the time units of the Time Limit parameter. If ICC Bit 7 is cleared to zero, then Serial ATA Revision 3.0 Gold Revision page 504 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization • The time interval is fine-grained. • Interval = 10 msec • Time Limit = (ICC[6:0] + 1) * 10 msec • Max Fine Time = 128 * 10 msec = 1.28 sec If ICC Bit 7 is set to one (coarse encoding), then • The time interval is coarse-grained • Interval = 0.5 sec; • Time Limit = (ICC[6:0] + 1) * 0.5 sec • Max Coarse Time = 128 * 0.5 sec = 64 sec FUA When set to one forces the data to be retrieved from the storage media regardless of whether the storage device holds the requested information in its buffers or cache. If the device holds a modified copy of the requested data as a result of having cached writes, the modified data is first written to the media before being retrieved from the storage media as part of this operation. When cleared to zero the data may be retrieved either from the device’s storage media or from buffers/cache that the device may include. Others All other registers have contents consistent with the READ DMA QUEUED EXT command defined in the ATA8-ACS standard, including the Sector Count 15:0 convention where a value of zero specifies that 65,536 sectors are to be transferred. 13.6.3.2 Success Outputs Upon successful completion of one or more outstanding commands, the device shall transmit a Set Device Bits FIS with the Interrupt bit set to one and one or more bits set to one in the ACT field corresponding to the bit position for each command TAG that has completed since the last status notification was transmitted. The ERR bit in the Status register shall be cleared to zero and the value in the Error register shall be zero. The ACT field occupies the last 32 bits of the Set Device Bits FIS as defined in Figure 190 below. 0 Error 0 R Status Hi R Status Lo N I R Reserved (0) 01 FIS Type (A1h) 1 ACT 31:0 Figure 190 – Set Device Bits FIS for successful READ FPDMA QUEUED command completion ACT Error Status The ACT field of the Set Device Bits FIS communicates successful completion notification for each of up to 32 queued commands. The field is bit-significant and the device sets bit positions to one for each command tag it is indicating successful completion notification for. The device may set more than one bit to one if it is explicitly aggregating successful status returns. The Error register shall be cleared to zero. As defined in section 10.3.6. The ERR bit shall be cleared to zero indicating successful command completion. Serial ATA Revision 3.0 Gold Revision page 505 of 663 I Interrupt bit. The interrupt bit shall be set to one. All other fields as defined in section 10.3.6. NOTE: Devices should be aware that if choosing to aggregate status to the point where many of the outstanding commands have actually completed successfully without notification to the host, that an error may cause the final completion status of those commands to be failure. A device should be selective when using status aggregation for outstanding queued commands to ensure the host is made aware of successful completion for outstanding commands in a way that an error would not force a high number of unnecessary command retries. 13.6.3.3 Error Outputs 13.6.3.3.1.1 Upon receipt of a command If the device has received a command that has not yet been acknowledged by clearing the BSY bit to zero and an error is encountered, the device shall transmit a Register FIS (see Figure 206) to the host with the ERR bit set to one and the BSY bit cleared to zero in the Status field, the ATA error code in the Error field. Register Error Count(7:0) Count(15:8) LBA(7:0) LBA(31:24) LBA(15:8) LBA(39:32) LBA(23:16 LBA(47:40) Device Status 7 6 5 BSY DRDY DF 4 3 2 ERROR na na na na na na na na na na DRQ na 1 0 na ERR Figure 206 – READ FPDMA QUEUED error on command receipt ERROR BSY DRDY DF DRQ ERR ATA error code for the failure condition of the failed command 0 1 0 0 1 Following transmission of the Register FIS, the device shall stop processing any outstanding or new commands until the Queued Error Log (see 13.7) has been read before continuing to abort all outstanding commands. 13.6.3.3.1.2 During execution of a command If all commands have been acknowledged by clearing the BSY bit to zero and an error condition is detected, the device shall transmit a Set Device Bits FIS (see Figure 191 below) to the host with the ERR bit set to one in the Status field, the ATA error code in the Error field, and the Interrupt bit set to one. All outstanding commands at the time of an error shall be aborted as part of the error response and may be re-issued as appropriate by the host. For any commands that Serial ATA Revision 3.0 Gold Revision page 506 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization have not completed successfully or have resulted in error, the device shall clear the corresponding ACT bits to zero in the Set Device Bits FIS. 0 Error R Status Hi R Status Lo N I R Reserved (0) 1 1 FIS Type (A1h) 1 ACT 31:0 Figure 207 - Set Device Bits FIS with error notification, and command completions SActive The ACT field of the Set Device Bits FIS communicates successful completion notification for each of up to 32 queued commands. The field is bit-significant and the device sets bit positions to one for each command tag it is indicating successful completion notification for. The device may set more than one bit to one if it is explicitly aggregating successful status returns. Error The Error register shall contain the ATA error code. Status As defined in section 10.3.6. The ERR bit shall be set to one indicating an NCQ error has occurred. I Interrupt bit. The interrupt bit shall be set to one. All other fields as defined in section 10.3.6. Only the registers that are updated as part of the Set Device Bits FIS are modified if the device signals an error condition when the BSY bit in the Shadow Status register is cleared to zero, leaving the other Shadow Register Block Registers unchanged. If the device signals an error condition when the BSY bit in the shadow Status register is set to one, the device clears the BSY bit to zero with a Register FIS which updates all registers in the Shadow Register Block, but the corresponding error information for the command is still retrieved by reading the Queued Error Log. Following transmission of the Set Device Bits FIS, the device shall stop processing any outstanding or new commands until the Queued Error Log has been read before continuing to abort all outstanding commands. See 13.6.3.4 for more details. 13.6.3.4 Queue abort Following transmission of the Register FIS or Set Device Bits FIS in response to an NCQ error condition, the device shall stop processing any outstanding or new commands until the Queued Error Log (see 13.7) is read using the General Purpose Logging (GPL) feature set. When a command to read the Queued Error Log is received, the device shall perform any necessary cleanup before returning detailed error information for the last failed command including the tag value for the failed command as described in 13.7. In response to a received command to read the Queued Error Log the device shall transmit a Set Device Bits FIS (see Figure 208 below) to the host with all the bits in the ACT field set to one. This policy avoids the host inadvertently completing a failed command with successful status. The exception to this policy is if the host reads the Queued Error Log for information which is not directly tied to a specific error reported by the device. In the case where a device receives a command to read the Queued Error Log which is not in direct response to an error reported by the device as well as no queued commands being outstanding, it is not required that a Set Device Bits FIS is delivered in response as it is not a necessity to abort any commands at that time. Serial ATA Revision 3.0 Gold Revision page 507 of 663 0 Error 0 R Status Hi R Status Lo N I R Reserved (0) 0 1 FIS Type (A1h) 1 ACT 31:0 11111111111111111111111111111111 Figure 208 - Set Device Bits FIS aborting all outstanding command ACT The entire ACT field shall be set to one as an indication that all outstanding commands are being aborted. Error The Error register shall be cleared to zero. Status As defined in 10.3.6. The ERR bit shall be cleared to zero indicating clean up of all previously outstanding commands. I Interrupt bit. The interrupt bit shall be set to one. All other fields as defined in 10.3.6. When an error is indicated, the host shall treat any outstanding commands that do not have their corresponding SActive register bit cleared as failed. Serial ATA Revision 3.0 Gold Revision page 508 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 13.6.3.5 WRITE FPDMA QUEUED Queued native write commands make use of a new command. The format of the new command is defined in Figure 209. Register Features(7:0) Features(15:8) Count(7:0) Count(15:8) LBA(7:0) LBA(31:24) LBA(15:8) LBA(39:32) LBA(23:16 LBA(47:40) ICC Device Command 7 6 PRIO(1:0) FUA 1 5 4 3 2 1 0 Sector Count 7:0 Sector Count 15:8 TAG Reserved Reserved LBA 7:0 LBA 31:24 LBA 15:8 LBA 39:32 LBA 23:16 LBA 47:40 ICC(7:0) 0 0 Reserved 61h Figure 209 – WRITE FPDMA QUEUED command definition TAG PRIO ICC The TAG value shall be assigned by host software to be different from all other TAG values corresponding to outstanding commands. The assigned TAG value shall not exceed the value specified in IDENTIFY DEVICE word 75. The Priority (PRIO) value is assigned by the host based on the priority of the command issued. The device should complete high priority requests in a more timely fashion than normal and isochronous requests. The device should complete isochronous requests prior to its associated deadline. 00b Normal Priority 01b Isochronous – deadline dependent priority 10b High priority 11b Reserved The Isochronous Command Completion (ICC) field is valid when PRIO is set to a value of 01b. It is assigned by the host based on the intended deadline associated with the command issued. When a deadline has expired, the device shall continue to complete the command as soon as possible. This behavior may be modified by the host if the device supports the NCQ QUEUE MANAGEMENT command (see 13.6.3.8) and supports the Deadline Handling subcommand (see 13.6.3.8.2). This subcommand allows the host to set whether the device shall abort (or continue processing) commands that have exceeded the time set in ICC. There are several parameters encoded in the ICC field: Fine or Coarse timing, Interval and the Max Time. The Interval indicates the time units of the Time Limit parameter. If ICC Bit 7 is cleared to zero, then • The time interval is fine-grained. • Interval = 10 msec Serial ATA Revision 3.0 Gold Revision page 509 of 663 FUA Others • Time Limit = (ICC[6:0] + 1) * 10 msec • Max Fine Time = 128 * 10 msec = 1.28 sec If ICC Bit 7 is set to one (coarse encoding), then • The time interval is coarse-grained • Interval = 0.5 sec; • Time Limit = (ICC[6:0] + 1) * 0.5 sec Max Coarse Time = 128 * 0.5 sec = 64 sec When set to one forces the data to be written to the storage media before completion status is indicated. When cleared to zero the device may indicate completion status before the data is committed to the media. All other registers as specified for the WRITE DMA QUEUED EXT command defined in the ATA8-ACS standard, including the Sector Count 15:0 convention where a value of zero specifies that 65,536 sectors are to be transferred. 13.6.3.6 Success Outputs Upon successful completion of one or more outstanding commands, the device shall transmit a Set Device Bits FIS with the Interrupt bit set to one and one or more bits set to one in the ACT field corresponding to the bit position for each command TAG that has completed since the last status notification was transmitted. The ERR bit in the Status register shall be cleared to zero and the value in the Error register shall be zero. The ACT field occupies the last 32 bits of the Set Device Bits FIS as defined in Figure 210 below. 0 Error 0 R Status Hi R Status Lo N I R Reserved (0) 01 FIS Type (A1h) 1 ACT 31:0 Figure 210 - Set Device Bits FIS for successful WRITE FPDMA QUEUED command completion ACT The ACT field of the Set Device Bits FIS communicates successful completion notification for each of up to 32 queued commands. The field is bit-significant and the device sets bit positions to one for each command tag it is indicating successful completion notification for. The device may set more than one bit to one if it is explicitly aggregating successful status returns. Error The Error register shall be cleared to zero. Status As defined in 10.3.6. The ERR bit shall be cleared to zero indicating successful command completion. I Interrupt bit. The interrupt bit shall be set to one. All other fields as defined in 10.3.6. NOTE: Devices should be aware that if choosing to aggregate status to the point where many of the outstanding commands have actually completed successfully without notification to the host, that an error may cause the final completion status of those commands to be failure. A device should be selective when using status aggregation for outstanding queued commands to ensure the host is made aware of successful completion for outstanding commands in a way that an error would not force a high number of unnecessary command retries. Serial ATA Revision 3.0 Gold Revision page 510 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 13.6.3.7 Error Outputs 13.6.3.7.1.1 Upon receipt of a command If the device has received a command that has not yet been acknowledged by clearing the BSY bit to zero and an error is encountered, the device shall transmit a Register FIS (see Figure 211 below) to the host with the ERR bit set to one and the BSY bit cleared to zero in the Status field, the ATA error code in the Error field. Register Error Count(7:0) Count(15:8) LBA(7:0) LBA(31:24) LBA(15:8) LBA(39:32) LBA(23:16 LBA(47:40) Device Status 7 6 5 BSY DRDY DF 4 3 2 ERROR na na na na na na na na na na DRQ na 1 0 na ERR Figure 211 – WRITE FPDMA QUEUED error on command receipt ERROR BSY DRDY DF DRQ ERR ATA error code for the failure condition of the failed command 0 1 0 0 1 Following transmission of the Register FIS, the device shall stop processing any outstanding or new commands until the Queued Error Log (see 13.7) has been read before continuing to abort all outstanding commands. See 13.6.3.4 for more details. 13.6.3.7.1.2 During execution of a command If all commands have been acknowledged by clearing the BSY bit to zero and an error condition is detected, the device shall transmit a Set Device Bits FIS (see Figure 212 below) to the host with the ERR bit set to one in the Status field, the ATA error code in the Error field, and the Interrupt bit set to one. All outstanding commands at the time of an error shall be aborted as part of the error response and may be re-issued as appropriate by the host. For any commands that have not completed successfully or have resulted in error, the device shall clear the corresponding ACT bits to zero in the Set Device Bits FIS. Serial ATA Revision 3.0 Gold Revision page 511 of 663 0 Error R Status Hi R Status Lo N I R Reserved (0) 1 1 FIS Type (A1h) 1 ACT 31:0 Figure 212 - Set Device Bits FIS with error notification, and command completions ACT The ACT field of the Set Device Bits FIS communicates successful completion notification for each of up to 32 queued commands. The field is bit-significant and the device sets bit positions to one for each command tag it is indicating successful completion notification for. The device may set more than one bit to one if it is explicitly aggregating successful status returns. Error The Error register shall contain the ATA error code. Status As defined in 10.3.6. The ERR bit shall be set to one indicating an NCQ error has occurred. I Interrupt bit. The interrupt bit shall be set to one. All other fields as defined in 10.3.6. Only the registers that are updated as part of the Set Device Bits FIS are modified if the device signals an error condition when the BSY bit in the shadow Status register is cleared to zero, leaving the other Shadow Register Block Registers unchanged. If the device signals an error condition when the BSY bit in the shadow Status register is set to one, the device clears the BSY bit to zero with a Register FIS which updates all registers in the Shadow Register Block. Following transmission of the Set Device Bits FIS, the device shall stop processing any outstanding or new commands until the Queued Error Log (see 13.7) has been read before continuing to abort all outstanding commands. See 13.6.3.4 for more details. Serial ATA Revision 3.0 Gold Revision page 512 of 663 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 13.6.3.8 NCQ QUEUE MANAGEMENT The NCQ Queue Management feature allows the host to manage the outstanding NCQ commands and/or affect the processing of NCQ commands. The NCQ QUEUE MANAGEMENT command is a non-data NCQ command. Only specified NCQ QUEUE MANAGEMENT subcommands are executed as Immediate NCQ commands. If NCQ is disabled and an NCQ QUEUE MANAGEMENT command is issued to the device, then the device shall abort the command with the ERR bit set to one in the Status register and the ABRT bit set to one in the Error register. This command is prohibited for devices that implement the PACKET feature set. The queueing behavior of the device depends on which subcommand is specified. Register Features(7:0) Features(15:8) Count(7:0) Count(15:8) LBA(7:0) LBA(31:24) LBA(15:8) LBA(39:32) LBA(23:16 LBA(47:40) Device Command 7 6 5 4 3 Subcommand Specific Reserved TAG Reserved Subcommand Specific (TTAG) Reserved Reserved Reserved Reserved Reserved Res 1 Res 0 63h 2 1 0 Subcommand Reserved Reserved Reserved Figure 213 - NCQ QUEU