DYNAMIC
NBTI
OF
PMOS
TRANSISTORS
ITS
IMPACT
ON
AND
DEVICE
LIFETIME
G. Chen,
K. Y.
Chuah, M.
F.
Li, Dailiel SH Chan, C.
H.
Ang’,
J.
Z.
Zhcng’,
Y.
Jin’ and
D.
L.
Kwon2
SNDL and CICFAR, Dept.
of
Electrical
&
Computer Engineering, National University of Singapore, Singapore I19260
T e I 6 5 6874 2559, Fax: 65 6779
1103,
E-mail: elelimf@nus.edu.sg
Chartered Semiomductor Manufachuing Ltd, Singapore 738406
Dept. of Electrical
&
Computer Engineering, The University ofTexas at Austin, TX 78752, USA
’
ABSTRACT
We report
a
new NBTl phenomenon for the first time for the
p-
MOSFETs with ultra thin gate oxides. We demonstrate that
in
a
CMOS inverter circuit, the interface traps generated under the
NBTl stressing in a p-MOSFET (corresponding to the
“high”
output state
o f
the inverter) are subsequently passivated when the
gate to drain voltage switches
to
positive (corresponding to the
LLlowx’
output state of the invetter). As a result,
it
was found that
this “Dynamic” NBTl (DNBTI) operatipg in
a
CMOS inverter
circuit
prolongs
significantly the device lifetime while the
conventional “static”
NBTl
(SNBTI) underestimates the device
lifetime. Furthermore, the DNBTI
effect
is depsndent of
temperature and gate oxide thickness
,
however independent
of
operation frequency. A physical model is proposed for DNBTl that
involves the interaction between hydrogen and silicon dangling
bonds.
This
finding has significant impact
on
the determination of
maximum operation voltage as well as lifetime prqiection for
future scaling
of
CMOS devices.
P-MOSFETs were fabricated using standard dual-gate CMOS
technology. Gate oxides with thicknesses
of
1.3nm, 1.4nm.
1.7nm
and 2.lnm were grown by Rapid Thermal Oxidation followed by
an
exposure to high-density nitrogen plasma. TEM and CV
measurement and simulation
[7]
confirmed the thickness of these
ultrathin gate oxides. Carrier separation measurement fits well to
tunneling simulation [XI, indicating that the leakage is mainly
caused
by direct tunneling. DClV technique
[9,10]
was improved
in this work (Appendix) to accurately monitor interface trap
formation during bath stressing and passivation phases. By proper
treatment ofthe measured hulk current in
a
gate controlled bipolar-
junction-transistor configuration, the electron-hole-recombination
current
IDclv
that is proportional
to
the interface trap concentration
N;,,
successfully obtained far devices with gate oxide
as
thin
as
is
1.3nm.
EXPERIMENTAL
RESULTS:
THE
DNBTI
PHENOMENON
The SNBTI stress was first applied to p-MOSFETs at
a
temperature
of
100
“C. The threshold voltage shift AV,b and DClV
current
lmlV
were monitored and the relationship between them
was investigated.
Fig.1
shows
an
excellent correlation between
AV,h and ANN,,(AIDclv)under
SNBTI stress.
INTRODUCTION
With the continuom shrinking of the transistor dimensions, new
reliabilitv issues emerge. among which negative bias t8:muerahue
instability (NBTI)
of
i-MOSFfT has been-identified as a critical
.
limiting factor that ultimately determines the lifetime of
rhc
devices
11-31.
However,
as
will
be
shown,
the Conventional
NBTI
based
on
. .
static experimental data, overestimate the degradation
of
the p-
MOSFET
in
digital CMOS circuits
by
overlooking the electric
oassivatian (EP) effect durine normal ooemtions of diaital circuits.
~,
”
During the operation of a p-MOSFET in a CMOS iwerter, the
applied gate bias (input signal) is switching between “high” and
“low” voltages, while the drain bias (output signal) is altemating
between “low” and “ h i g h voltages, correspondingly. Therefore, it
is critically important
to
investigate
NBTI
under such dynamic
stress conditions. During “low” (low output) phase of
im
inverter,
the EP effect effectively reduces the interface traps generated
during “high” (high output) phase, and consequently,
II:COWTS
the
degradations of device parameters
to
a
certain degree.
I
2 0 1 p ’ ~
7”-
S ~
’
~ T
.
T””Z1
~
,“A-
I.“,,,,,
’
2,
J
’
lo
tvg:
Although the electric passivation
or
annealing
of
interface traps
N,, has been studied for hat carrier degradations
[4-61,
there has
been
no
study
on
its effects
on
p-MOS NBTI under realistic circuit
operation.
In
this paper, we will show that the DNBTI effect
greatly prolongs the lifetime of p-MOSFETs operating
in
a digital
clrcuit, while the conventional SNBTI measurement
underestimates the p-MOSFET lifetime.
FIGURE CORRELATION
BETWEEN
DCIV
CURRENT
AND THRESHOLD
1,
VOLTAGE
CHANGES.
INTERFACE
TRAP
GENERATION PLAYS A
MAJOR
ROLE
IN
NBTI. THE
INSET
SHOWS
THE
TYPICAL
DClV
SPECTRA FOR
1.3
Nh4
GATE
OXIDE
P-MOSFET.
Interestingly, when
reversing
the electric field to the opposite
polarity (the passivation mode) during SNBTI stressing,
a
reduction of AN,,and thus AVvth -A&% was observed
(Fig.2).
It
and
is shown in Fig.2 that the ANN,,,
AVvth, -A&%
are
increasing and
and
decreasing simultaneously during the stress-passivation-stress
DEVICE
FA~RICATION
AND
DEGRADATION
CHARACTERIZATION
0-7803-7649-81031$17.00
02003
IEEE
196
IEEE
03CH37400.4151
Annual
International
Reliability
Physics
Symposium.
Dallas, Texas,
2003
sequence. Therefore,
the
degradations
of
N,,, Vlh
and
g,
are
probably
due
to
the
same
origin
of interface trap generation. The
relations between
AVu,
vs.
ANi,
and
A&%
are plotted in
Fig.2
(b).
It
is
shown
that the linearity among these three parameters
is
excellent and
the
slope
of
AV*
YS.
AN,,
plot
is
exactly the
same
as
that in Fig.1.
3o
7s
'
Stress
' V p 2 . 7
V
'
P85sivalion
Vg=+0.2 V
1
L
0
'
stress
v g = - 2 . 7
v
30
25
20
!
-
stress
vg=-2.7
V
Passivation
V g = + 2 V
:
j
1
StrpPassivatioy?Gls'
10:
i
1
L.
-
-
5 -
0
lim
(s)
(4
Time
(s)
FIGURE
VARIATION V,,
3.
OF
~ O E STRESS-PASSIVATION-STRESS.
R
THE
STRESS CONDlTlONS
ARE
SIMILAR AS
IN
F1G.2
.
PASSNATION
RATE INCREASES WITH INCREASING OF PSSNATION GATE VOLTAGE
(AND
THE
ELECTRIC FIELD).
25
P
5
40
I
Stress
V9=-2.7 V,
Othertermianls
ground
Passivation
Vd=-2.7
V,
other termianls ground
a
5-
0-
-
E
0 -
2
/Stress
'
5
>
d
1
10
-
I
"I
!
pMOSFET
T=10O0C
w / L = ~
2um
OO/O.I
T0,=l.3nm
,
'.
--.
'
IPassivationj
.'
Stress
.
I000 2 0 0 0 .
SOO!
Time
(s)
FIGURE
(a)
VARIATIONS
V,
2.
OF
STRESS-PASSIVATION-STRESS
v m
SHIFT,
DCIV
CURRENT
AND
g
VARIATIONS
I
()
,
N
a.
AIm,v
SLOPE IS EXACTLY THE SAME AS
IN
FIG.
1
DClV
CUWNT,
AND
g
UNDER
,
PROCESS.
(b)
CORRELATION
BETWEEN
THEAV,-
FIGURE
4.
ILLUSTRATION
OF
DYNAMIC
NBTI,
DURING
HIGH-LOW
OPERATION O F A P - M O S F E T
IN
A DIGlT4L
CMOS
INVERTER.
DUE
TO
THE
ELECTRIC-PASSIVATION
EFFECT,
THE CONVENTIONAL
SNBTI
OVERESTIMATES THE DEGRADATION.
197
We
also
found that the passivation rate is electric field
dependent, i.e., the larger the field applied, the more rapid the
passivation. Fig.3
shows
AVs
under the
stress-passi~ation-stress
sequence where the stress conditions remain the same except
changing the passivation gate voltage. The data indicates that
a
higher electric field favors the passivation process.
To
simulate
a
p-MOSFET
during
the
"low"
phase in
a
CMOS
invener,
a
non-uniform electric field is applied during the
"passivation" period,
i.e.,
a
negative drain bias is applied while the
other terminals are kept go-ounded.
As
shown in Fig.4, the
EP
effect
is similar to that
seen
under
uniform
electric field Passivation.
In
digital circuits, the devices are operated undcr dynamic
conditions. For
a
p-MOSFET in
an
inverter (FigS), the input signal
V,
and
the
output signal
V,,
are
opposite in terms of phase.
To
simulate the stressing condition,
we
deliberately apply a train
of
square
wave to the gate and
an
opposite phase signal to the drain,
as
shown in Fig.6.
p
MOSFET
W/L=100/1um
T = l
00
OC
20
D N
B T I L
p
MOSFET
Tox=1.3nm
W/L=100/0.12un
T=100
OC
200
400 600
800
1000
Stressing Time
(s)
(Annealing &e excluded)
r/
FIGURE
10
p-MOSFET
5
FIGURE
COMPARISON BETWEEN
SNBTl
AND
DNBTl
FOR
(a)
LONG
7.
CHANNEL AND
(b)
SHORT CHANNEL
P-MOSFETS. FOR DNBTI,
THE
STRESSMG TIME IS HALF THE NOMINAL STRESS TIME (OPERATION
TIME), G N E N
THE
50%
DUTY CYCLE.
THE
M T I
STRESS FREQUENCY
D
I
5.
A
P-MOSFET
W
A
-0.sHz.
INVERTER ACTUALLY
CMOS
UNDERGOES DYNAMIC STRESSING.
Under
such dynamic stress conditions, it
is
found that the
interfacc
trap
generation
and
passivation take
place
mainly near
the
vg
Jl
drain-channel comer, and therefore devices with shorter channel
benefit more from the EP effect than longer channel
ones,
as
confirmed by Figs.7
(a)
and (b).
"-well
G
0.13um
p
MOSFET
W/L=10/0.12
pMOSFET
6
-
%
3 0
0
8
7
a
-40
,
.-
E
SNBTI
1000s
N B T l
1000s
DutyCycle=50%
0
'
i
1'0
1bO
i k
I b k
ldok
M
!
Frequency
f
(Hz)
FIGURE
To
SIMULATE
THE
P-MOSFET
STRESSLVCCONDITION,
TWO
6.
OPPOSITE PHASE SQUARE WAVE TRAINS ARE APPLIED
TO
ITS
GATE AND
DRAIN ELECTRODES, RESPECTIVELY.
FIGURE
THE
FREQUENCY DEPENDENCY
OF
DNBTI,
WITH THE
8.
SAME STRESS
AND
PASSIVATIONVOLTAGES AS
M
FIG.7.
DIFFERENT
SYMPOLS FOR DIFFERENT SAMPLES
198
The frequency dependency
of
DNBTl
was studied in the
range
of 0.5 to
lOOk
Nz,
as
shown
in
Fig. 8.
As
can
bc
seen,
the DNBTl
is frequency independent in this frequency range with significantly
lower degradation than
SNBTI.
The V,, degradations under thc same stress condition but
different temperatures were plotted
in
Fig.9.
It
is
shown that
although bath SNBTI and DNBTl degradations
are
smaller at
lower temperatures, the
EP
effect is obvious
even
under room
temperahre, indicating that the passivation is not due to thermal
activation effect.
-0-
10'0
0
0
Static
Dynamic
SNBTl
'Q
,
"4.0
1.5
,,
v
2.0
2.5
(V)
3.0
FIGURE
II.
SNBTl
AND
DNBTI
LIFETIME
(30
M V
V,
SHIFT)
PROJECTIONS
FOR
P-MOSFETS.
THE
PRDECTED
IO-YEAR
LIFETIME
OPERATING VOLTAGE
v,,y
IS
1.2V
FOR
DNBTl
STRESS, AND IS
0.9V
FOR
SNBTl
STRESS WHICH OYERESTIMATES THE DEGRADATION
M
20
40
60
80 100 120 140
Temperature T
("C)
REAL DIGITAL OPERATION.
FIGURE THE
9.
TEMPERATURE
DEPENDENCY
OF
SNBTl
AND
DNBTI,
NlTH THE STRESS
VOlllAGE SAME
AS
M
FlG.7.
Because of the significant
EP
effect of interface traps
on
p-
MOSFET
operating
in
a CMOS
inverter,
the device lifetime under
DNBTI stress can be much
longer
than that projected under the
conventional SNBTl stress. The lifetime projection for both
DNBTI and SNBTI was compared and the
10-year
lifetime
operation voltages were extracted
in
Fig.1
I .
It is shown that V,ou is
0.9
V for SNBTl degradation while it is I ~ 2 V for DNBTl
degradation. Under the same stress voltage, the lifetime predicted
by DNBTl
is
almost
one
order of magnitude longer than predicted
by SNBTI.
DISCUSSION
As
first proposed
in
1965 by
P.
Balk at IBM
[ll],
and now
widely accepted
[12-141,
interface
traps
are related to Si dangling
bonds whcn hydrogen is released from a Si-H bond. Sah
et
al
have
proposed in 1983 the
reverse process:
passivation of interface trap
by the absorbtion of hydrogen at the dangling bond site
[15].
The
excellent correlation among AV,,,, Agm and AN,, (AIocIv) under
NBTl mess, as shown
in
Figs.1-3, indicates that for ultrathin gate
oxide deviccs, the device parameter degradation is mainly caused
by the interface trap generation. Based
on
the interface trap
generation and passivation mechanisms proposed
in
[ I I]
and
[15],
and the recent diffusion-reaction model proposed for the
electrochemical reaction of interface trap generation during NBTl
degradation
[16],
we propose
the
following reactions for interface
trap generation and passivation in DNBTI (eqs (1) and
(2),
and
Fig.
12):
I10,O
12 13 14 15 16
17
18
19
20
21
Gate thickness
Tox
(A)
I
.
,
I
.
I
.
I.
.
,
.
,
I
.
I
.
FIGURE
THE
OXIDE-THICKNESS
DEPENDENCY
OF
SNBTI
AND
10.
DNBTl
UNDER THE SAME STRESS VOLTAGE AS
I
FIG.7.
N
(Si,
-Si-H)
and
+
h'
tf
Si,
Si'
+
Xjnkrram
(1)
The device degradations for different oxide thicknesses were
also compared. Fig.
10
shows that far thinner gate oxide, the
passivation effect in DNBTI
is
larger.
Here Si,
S i - H
is the
precursor
for the Si-H bond. When it
interacts with
a
hole h' in the inversion layer
or
the sourceidrain
extension
region
under the NBTl stress, the hole breaks the
Si-H
bond and creates
an
interface trap by releasing hydrogen species
199
X,n,,+ef,,
the Si/Si02 interface. One thing remaining uncertain is
at
how the holes accelerated by operating voltage
as law as
2.7
V
in
this work can break the Si-H bond and generate the interface traps.
This is
a
big unsolved issue and probably more complicated
processes
such
as
the
Auger mechanism may be involved
[
17,
181.
We therefore consider
(1)
as
a more generalized reaction in that
some detailed reaction mechanism has not been shown explicitly.
The produced hydrogen species denoted as
X
in
eq
(I),
sither
in
the
form
of
molecules
or
neutral atoms or ions, will diffusddrift to the
gate electrode through the bulk gate oxide,
as
expressed by
eq
(2)
(Fig.lZa).
In
this process, the interface acts as a hydrogen source.
The
major
symptom of NBTI is the shift of threshold viiltage
AVlb.
For ultrathin gate oxide MOSFETs, thc AVth is mainly induced by
interface traps building up along the silicon-gate oxide interface, as
oxide charges
arc
easily detrapped by tunneling and thus makes a
smallcr contribution [19].
The
EP
effect is interpreted by
the
reverse interaction between
N,, and hydrogen species
as
shown in Fig. 12b. Whcn the gate bias
polarity is reversed from the negative lo positive, the channel
inversion layer disappears and depletion layers
are
formed at
sourceidrain. The breaking of Si-H bond stops due to lack
of
holes.
On
the other hand, the
reverse
reaction
occurs
when the hydrogen
moves back to the Si0,iSi interface and passivates the Si dangling
bands, resulting in AN,, reduction.
In
this,period, the interface actS
as
a hydrogen sink.
Finally,
as
proposed in
[16],
the NBTI degradation is diffusion-
controlled
rather
than
reaction-controlled. As can be
seen
in Fig.
13,
a
slope
of 0.25 is observed in the time dependence of AV,h for
both stressing and passivation modes, supporting
the
theory that
both processes
under
DNBTI
are
diffusion-controlled.
w
@
P*
e
W
&
j
.....
.........
wxll
CONCLMSJON
Negartive bias temperahue instability (NBTI) under dynamic
operation that simulates
a
practical stress condition
for
a p-
MOSFET in
a
CMOS inverter was investigated and the electric
passivation effect of interface traps during positive bias was
demonstrated for the first time.
A
physical model involving the
@)+
................
interactions between hydrogen species and silicon dangling bonds
is proposed
to
explain this Dynamic NBTI phcnomenon. It is
shown that DNBTI suppresses
p-MOS
device degradation and
Rslli\ewltage
P*W-*
( d a t i m )
significantly prolongs the device lifetime and increase the IO-year
operation
voltage.
This finding has
a
significant impact
on
fuhlre
CMOS device scaling projections.
(imuim)
Appendix
FIGURE (a) N,,
FOP~MATION
HYDROGEN
DIFFUSIONTOWARDS
12.
AND
THE GATE ELECTRODE DURING NEGATIVE GATE BIAS STRESSING.
(b)
HYDROGEN RETURNING TO THE INTERFACE AND
N,,
PASSIVATION
DURMG POSITNE GATE
BIAS.
INTERFACE TRAPS MEASUREMENT BY IMPROVED
DCIV METHOD FOR TUNNELLING OXIDE
DEVICES
By proper biasing and signal processing, the DCIV method
[9,10] is able to effectively monitor the interface traps and oxide
charges in MOSFETs with gate oxide thicknesses down to
1.3
n
m
For
such tunneling
gale
oxide
in
DCIV
measurement, the
measured
bulk current
Ib
consists
of
the following components
(
Fig.Al)
:
x
STANDS FOR HYDROGEN SPECIES.
h
>
10
E
v
5
U
p
MOSFET
'
WlL=loO/l
urn
'1
10
100
1000
Time
(s)
FIGURE
THE
13.
VTH
SHIFT
VERSUS
TIME
CURVES
FOR
THE
STRESS-PASSIVATLON-STRESS
PROCEDURE.
THE-
0.25
SLOPES
LOG-LOG
FIGURE
A1
.
DIFFERENT
CURRENT COMPONENTS
n
E Q ( A ~ )
i
.
ELECTRON
CURENTS
MARKED
BY
SOLID LINES, HOLE
CURRENTS
MARKED
BY
DASHED LWES
INDICATE THAT THE PROCESSES
A R E
DIFFUSION-CONTROL1.ED.
.
200
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