5
4
3
2
1
SABRE Lite
D
D
INDEX
SCHEMATIC
01.CONVER PAGE
02.Schematic History
03.BLOCK DIAGRAM
04.CPU POWER
05.IMX6Q_DDR3
06.IMX6Q_SOC
C
PAGE
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
B
C
07.IMAX6_INTERFACE
08.DDR3
09.USB PORTS
10.LVDS/HDMI/CAMERA
11.MULTIMEDIA SGTL500
12.MMC/SATA/SPI FLASH
13.RGMII
14.DIAGNOSTIC/ALERT
15.RGB DISPLAY MIPI UART
16.CAN BUS
B
17.SYSTEM POWER
17
A
Design
Review
Authorize
Standardize
5
4
3
2
<design>
element14
Title
SABRE Lite
Size Doc Name
A3
01.CONVER PAGE
Date
Wednesday, October 31, 2012
1
A
<review>
<authorize>
<standardize>
Ver.
D
Sheet
1
of
17
5
4
3
2
1
Schematic History
2012-07-09 Changes from SABRE Lite RevC
1.REPLACED THE 1.2 VOLT POWER FOR "NVCC_PLL_OUT" WITH LINEAR REGULATOR U23
D
2.REPLACED THE CAN CONTROLLER WITH NXP TJA1040T U18
3.MODIFIED J24A TO SUPPORT GIGA BIT ETHERNET
D
C
C
B
B
A
Design
Review
Authorize
Standardize
5
4
3
2
<design>
element14
Title
SABRE Lite
Size Doc Name
A3
02.Schematic History
Date
Wednesday, October 31, 2012
1
A
<review>
<authorize>
<standardize>
Ver.
D
Sheet
2
of
17
5
4
3
2
1
SABER Lite REV-D
D
D
C
C
B
B
A
Design
Review
Authorize
Standardize
5
4
3
2
<design>
element14
Title
SABRE Lite
Size Doc Name
A3
03.BLOCK DIAGRAM
Date
Wednesday, October 31, 2012
1
A
<review>
<authorize>
<standardize>
Ver.
D
Sheet
3
of
17
5
4
3
2
1
VCC_1P2V
C528 C530
0.22UF 0.22UF
C115
0.22UF
C532
0.22UF
C4
10UF
C5
22UF
U1E
iMX6Q
H14
J14
K14
L14
M14
N14
P14
R14
VDDARM_IN_1
VDDARM_IN_2
VDDARM_IN_3
VDDARM_IN_4
VDDARM_IN_5
VDDARM_IN_6
VDDARM_IN_7
VDDARM_IN_8
i.MX6Q - POWER
VDDARM_CAP_1
VDDARM_CAP_2
VDDARM_CAP_3
VDDARM_CAP_4
VDDARM_CAP_5
VDDARM_CAP_6
VDDARM_CAP_7
VDDARM_CAP_8
VDDARM_CAP23_1
VDDARM_CAP23_2
VDDARM_CAP23_3
VDDARM_CAP23_4
VDDARM_CAP23_5
VDDARM_CAP23_6
VDDARM_CAP23_7
VDDARM_CAP23_8
H13
J13
K13
L13
M13
N13
P13
R13
H11
J11
K11
L11
M11
N11
P11
R11
C118
0.22UF
C119
0.22UF
C120
0.22UF
C122
0.01UF
C121
0.01UF
C123
0.01UF
C21
22UF
C125
10UF
C131
0.22UF
C130
0.22UF
C127
0.22UF
C128
0.01UF
C126
0.01UF
C129
0.01UF
C11
22UF
D
D
C25
C12
C26
0.22UF
C27
0.22UF
C28
22UF
0.22UF 0.22UF
L1
BLM21PG220SN1
K9
L9
M9
N9
P9
R9
T9
U9
VDDARM23_IN_1
VDDARM23_IN_2
VDDARM23_IN_3
VDDARM23_IN_4
VDDARM23_IN_5
VDDARM23_IN_6
VDDARM23_IN_7
VDDARM23_IN_8
VDDSOC_CAP
R3
C537
0.22UF
C538
0.22UF
C143 C536
0.22UF 0.22UF
C40
10UF
C14
22UF
2
C801
47UF
VDD_SNVS
R1
0
VDDHIGH_IN
C156
C
H16
J16
K16
L16
M16
N16
P16
R16
T16
U16
H9
J9
VDDSOC_IN_1
VDDSOC_IN_2
VDDSOC_IN_3
VDDSOC_IN_4
VDDSOC_IN_5
VDDSOC_IN_6
VDDSOC_IN_7
VDDSOC_IN_8
VDDSOC_IN_9
VDDSOC_IN_10
VDDHIGH_IN_1
VDDHIGH_IN_2
VDDSOC_CAP_1
VDDSOC_CAP_2
VDDSOC_CAP_3
VDDSOC_CAP_4
VDDSOC_CAP_5
VDDSOC_CAP_6
VDDSOC_CAP_7
VDDPU_CAP_1
VDDPU_CAP_2
VDDPU_CAP_3
VDDPU_CAP_4
VDDPU_CAP_5
VDDPU_CAP_6
VDDPU_CAP_7
VDD_CACHE_CAP
VDDHIGH_CAP_1
VDDHIGH_CAP_2
R10
T10
T13
T14
U10
U13
U14
H17
J17
K17
L17
M17
N17
P17
N12
H10
J10
G9
C135
0.22UF
C138
0.22UF
C137
0.22UF
C140
0.22UF
C139
0.01UF
C141
0.01UF
C136
0.01UF
C36
22UF
1
0
2
1
C147
0.22UF
C150
0.22UF
C152
0.22UF
C149
0.22UF
C45
0.01UF
C46
0.01UF
C47
0.01UF
C48
22UF
1
C53
0.22UF
C54
C159
10UF
0.01UF
0.01UF
C160
C158
0.22UF
C52
10UF
C
2
C56
10UF
0.22UF
G11
VDD_SNVS_IN
VDD_SNVS_CAP
R6
3P3V
2
C163
0.22UF
C59
10UF
R7
0.22UF
2P5V
C57
0.1UF
B
A13
A25
A4
A8
AA10
AA13
AA16
AA19
AA22
AA7
AB24
AB3
AD10
AD13
AD16
AD19
AD22
AD4
AD7
AE1
AE25
B4
C1
C10
C4
C6
D3
D6
D8
E5
E6
E7
F5
F6
F7
F8
G10
G19
G3
H12
H15
H18
H8
J12
J15
J18
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
1
C60
0
NVCC_LCD
NVCC_CSI
NVCC_MIPI
NVCC_EIM0
NVCC_EIM1
NVCC_EIM2
NVCC_ENET
NVCC_GPIO
NVCC_PLL_OUT
NVCC_RGMII
NVCC_SD1
NVCC_SD2
NVCC_SD3
NVCC_NANDF
NVCC_JTAG
GPANAIO
FA_ANA
VDD_FA
GND_107
GND_106
GND_105
GND_104
GND_103
GND_102
GND_101
GND_100
GND_99
GND_98
GND_97
GND_96
GND_95
GND_94
GND_93
GND_92
GND_91
GND_90
GND_89
GND_88
GND_87
GND_86
GND_85
GND_84
GND_83
GND_82
GND_81
GND_80
P19
N7
K7
1
C61
3P3V
R8
0
C62
0.22UF
0.22UF
0
2
VCC_1P2V
1
2P5V
R9
0
3P3V
L19
M19
C63
R19
P7
0.22UF
B
C64
C65
0.22UF
C66
0.22UF
2
K19
C800
47UF
C67
0.22UF
U23
E8
C68
C69
2P5V
C70
0.22UF
R10
0.22UF
3P3V
0.22UF
0
3P3V
1
G18
G16
G17
1
0
R328
2
C71
0.22UF
10UF
RGMII_1P2V
1
3
GND
VIN
VOUT
AP7217D
2
2
1
0.22UF
C73
3P3V
0.22UF
R
0
12
R12
C74
3P3V
R13
C75
0.22UF
G14
G15
J7
C8
A5
B5
TP1
TP2
TP3
1
C76
0
0.22UF
2
0.22UF
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
A
Design
Review
Authorize
Standardize
<design>
element14
Title
SABRE Lite
Size Doc Name
A3
04.CPU POWER
Date
Saturday, June 08, 2013
1
2
C72
C808
10UF
A
Y24
Y5
W19
W18
W17
W16
W15
W13
W12
W11
W10
W9
W8
W7
W3
V19
V8
U19
U8
U17
U15
U12
U11
T8
T19
T17
T15
T12
J2
J8
K10
K12
K15
K18
K8
L10
L12
L15
L18
L2
L5
L8
M10
M12
M15
M18
M8
N10
N15
N18
N8
P10
P12
P15
P18
P8
R12
R15
R17
R8
T11
<review>
<authorize>
<standardize>
Ver.
D
Sheet
4
of
17
5
4
3
2
5
4
3
2
1
DDR_1_5V
DDR_1_5V
DRAM_D[63:0]
DRAM_D[63:0]
U1J
iMX6Q
D
DRAM_A[15:0]
DRAM_A[15:0]
1
C627
0.22UF
C628
0.22UF
C629
0.22UF
C630
0.22UF
C631
0.22UF
2
1
2
i.MX6Q - DDR
DRAM_D0
AD2
DRAM_D1
AE2
DRAM_D2
AC4
DRAM_D3
AA5
DRAM_D4
AC1
DRAM_D5
AD1
DRAM_D6
AB4
DRAM_D7
AE4
DRAM_SDQS0
AE3
DRAM_SDQS0_B
AD3
DRAM_DQM0
AC3
DRAM_D8
AD5
DRAM_D9
AE5
DRAM_D10
AA6
DRAM_D11
AE7
DRAM_D12
AB5
DRAM_D13
AC5
DRAM_D14
AB6
DRAM_D15
AC7
DRAM_SDQS1
AD6
DRAM_SDQS1_B
AE6
DRAM_DQM1
AC6
DRAM_D16
AB7
DRAM_D17
AA8
DRAM_D18
AB9
DRAM_D19
Y9
DRAM_D20
Y7
DRAM_D21
Y8
DRAM_D22
AC8
DRAM_D23
AA9
DRAM_SDQS2
AD8
DRAM_SDQS2_B
AE8
DRAM_DQM2
AB8
DRAM_D24
AE9
DRAM_D25
Y10
DRAM_D26
AE11
DRAM_D27
AB11
DRAM_D28
AC9
DRAM_D29
AD9
DRAM_D30
AD11
DRAM_D31
AC11
DRAM_SDQS3
AC10
DRAM_SDQS3_B
AB10
DRAM_DQM3
AE10
DRAM_D32
AA17
DRAM_D33
AA18
DRAM_D34
AC18
DRAM_D35
AE19
DRAM_D36
Y17
DRAM_D37
Y18
DRAM_D38
AB19
DRAM_D39
AC19
DRAM_SDQS4
AD18
DRAM_SDQS4_B
AE18
DRAM_DQM4
AB18
DRAM_D40
Y19
DRAM_D41
AB20
DRAM_D42
AB21
DRAM_D43
AD21
DRAM_D44
Y20
DRAM_D45
AA20
DRAM_D46
AE21
DRAM_D47
AC21
DRAM_SDQS5
AD20
DRAM_SDQS5_B
AE20
DRAM_DQM5
AC20
DRAM_D48
AC22
DRAM_D49
AE22
DRAM_D50
AE24
DRAM_D51
AC24
DRAM_D52
AB22
DRAM_D53
AC23
DRAM_D54
AD25
DRAM_D55
AC25
DRAM_SDQS6
AD23
DRAM_SDQS6_B
AE23
DRAM_DQM6
AD24
DRAM_D56
DRAM_D57
DRAM_D58
DRAM_D59
DRAM_D60
DRAM_D61
DRAM_D62
DRAM_D63
DRAM_SDQS7
DRAM_SDQS7_B
DRAM_DQM7
1
DDR_VREF
R318
240
1
C778
0.1UF
DDR_1_5V
C622
C782
47UF
0.22UF
C623
0.22UF
C624
0.22UF
C625
0.22UF
C626
0.22UF
C641
0.22UF
D
DRAM_SDQS0
DRAM_SDQS0_B
DRAM_DQM0
DRAM_D0
DRAM_D1
DRAM_D2
DRAM_D3
DRAM_D4
DRAM_D5
DRAM_D6
DRAM_D7
DRAM_SDQS0
DRAM_SDQS0_B
DRAM_DQM0
DRAM_D8
DRAM_D9
DRAM_D10
DRAM_D11
DRAM_D12
DRAM_D13
DRAM_D14
DRAM_D15
DRAM_SDQS1
DRAM_SDQS1_B
DRAM_DQM1
DRAM_D16
DRAM_D17
DRAM_D18
DRAM_D19
DRAM_D20
DRAM_D21
DRAM_D22
DRAM_D23
DRAM_SDQS2
DRAM_SDQS2_B
DRAM_DQM2
DRAM_D24
DRAM_D25
DRAM_D26
DRAM_D27
DRAM_D28
DRAM_D29
DRAM_D30
DRAM_D31
DRAM_SDQS3
DRAM_SDQS3_B
DRAM_DQM3
DRAM_D32
DRAM_D33
DRAM_D34
DRAM_D35
DRAM_D36
DRAM_D37
DRAM_D38
DRAM_D39
DRAM_SDQS4
DRAM_SDQS4_B
DRAM_DQM4
DRAM_D40
DRAM_D41
DRAM_D42
DRAM_D43
DRAM_D44
DRAM_D45
DRAM_D46
DRAM_D47
DRAM_SDQS5
DRAM_SDQS5_B
DRAM_DQM5
DRAM_D48
DRAM_D49
DRAM_D50
DRAM_D51
DRAM_D52
DRAM_D53
DRAM_D54
DRAM_D55
DRAM_SDQS6
DRAM_SDQS6_B
DRAM_DQM6
DRAM_D56
DRAM_D57
DRAM_D58
DRAM_D59
DRAM_D60
DRAM_D61
DRAM_D62
DRAM_D63
DRAM_SDQS7
DRAM_SDQS7_B
DRAM_DQM7
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A14
DRAM_A15
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
AC14
AB14
AA14
Y14
W14
AE13
AC13
Y13
AB13
AE12
AA15
AC12
AD12
AC17
AA12
Y12
AC15
Y15
AB12
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A14
DRAM_A15
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
C637
0.22UF
C638 C639
0.22UF
0.22UF
C640
0.22UF
R319
240
1
2
2
C779
0.1UF
DDR_1_5V
Termination Options
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A15
DRAM_A14
R1067
R1064
R1063
R1066
R1060
R1059
R1056
R1055
R1054
R1061
R1073
R1062
R1065
R1057
R1069
R1058
R1071
R1068
R1070
R1075
R1077
R1076
R1072
R1074
R1078
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DDR_VTT
2
C607
0.22UF
C608
0.22UF
C617
0.22UF
C618
0.22UF
C229
47UF
C235
47UF
C247
22UF
C619
0.22UF
C620
0.22UF
C621
0.22UF
C643
0.22UF
C647
0.22UF
DDR_1_5V
C602
0.22UF
C603
0.22UF
C604
0.22UF
C605
0.22UF
C223
47UF
C241
47UF
C
DRAM_SDQS1
DRAM_SDQS1_B
DRAM_DQM1
DRAM_CS0
DRAM_CS1
DRAM_RAS
DRAM_CAS
DRAM_SDWE
DRAM_SDCKE0
DRAM_SDCKE1
DRAM_SDODT0
DRAM_SDODT1
Y16
AD17
AB15
AE16
AB16
Y11
AA11
AC16
AB17
DRAM_CS0_B
DRAM_CS0_B
C
DRAM_RAS_B
DRAM_CAS_B
DRAM_WE_B
DRAM_SDCKE0
DRAM_SDODT0
DRAM_SDQS2
DRAM_SDQS2_B
DRAM_DQM2
DRAM_RAS_B
DRAM_CAS_B
DRAM_WE_B
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_SDCKE0
DRAM_CS0_B
DRAM_RAS_B
DRAM_CAS_B
DRAM_SDODT0
DRAM_WE_B
DRAM_SDCKE0
DRAM_SDODT0
DDR_VTT supply requirements
400mA worst case
Supply needs to sink and
source DDR_VTT
(25 * (0.75V/51ohms)) = 368 mA
C606
0.22UF
C612 C613
0.22UF
0.22UF
C614
0.22UF
C615
0.22UF
C616
0.22UF
C642
0.22UF
Butler Tpoint routing area
T2
T1 T3
T T T
DRAM_RESET
Y6
DRAM_RESET_B
10K
R197
DRAM_RESET_B
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A14
DRAM_A15
T5
T4 T6
T T T
T8
T7 T9
T T T
T11
T14
T17
T20
T23
T26
T29
T32
T35
T38
T41
T44
T47
T10 T12 T13 T15 T16 T18 T19 T21 T22 T24 T25 T27 T28 T30 T31 T33 T34 T36 T37 T39 T40 T42 T43 T45 T46 T48
T T T
T T T
T T T
T T T
T T T
T T T
T T T
T T T
T T T
T T T
T T T
T T T
T T T
DRAM_SDQS3
DRAM_SDQS3_B
DRAM_DQM3
DRAM_SDCLK_0
DRAM_SDCLK_0_B
AD15
AE15
DRAM_SDCLK0
DRAM_SDCLK0_B
DRAM_SDCLK0
DRAM_SDCLK0_B
GND probe pad
TP65
Clock access points
AD14
AE14
DRAM_SDCLK1
DRAM_SDCLK1_B
DRAM_SDCLK1
DRAM_SDCLK1_B
B
DRAM_SDQS4
DRAM_SDQS4_B
DRAM_DQM4
B
DRAM_SDCLK_1
DRAM_SDCLK_1_B
Clock terminators
Place at each DDR pair
DRAM_SDCLK0
TP66
R199
200
1%
DDR_VREF
DRAM_SDCLK0_B
DRAM_SDCLK1
C266
0.1UF
R200
200
1%
DRAM_SDCLK1_B
R198
240
1%
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_CS0_B
DRAM_RAS_B
DRAM_CAS_B
DRAM_WE_B
DRAM_SDCKE0
DRAM_SDODT0
T50
T53
T56
T59
T62
T65
T68
T71
T74
T49 T51 T52 T54 T55 T57 T58 T60 T61 T63 T64 T66 T67 T69 T70 T72 T73 T75
T T T
T T T
T T T
T T T
T T T
T T T
T T T
T T T
T T T
DRAM_SDQS5
DRAM_SDQS5_B
DRAM_DQM5
DRAM_VREF
AC2
GND probe pads
TP67
ZQPAD
NVCC_DRAM_1
NVCC_DRAM_2
NVCC_DRAM_3
NVCC_DRAM_4
NVCC_DRAM_5
NVCC_DRAM_6
NVCC_DRAM_7
NVCC_DRAM_8
NVCC_DRAM_9
NVCC_DRAM_10
NVCC_DRAM_11
NVCC_DRAM_12
NVCC_DRAM_13
AE17
R18
T18
U18
V10
V11
V12
V13
V14
V15
V16
V17
V18
V9
DRAM_SDQS6
DRAM_SDQS6_B
DRAM_DQM6
A
NOTES:
Using bit swapping for DATA bus to allow easy pcb routing.
DDR_1_5V
DRAM_SDQS7
DRAM_SDQS7_B
DRAM_DQM7
AB25
AA21
Y25
Y22
AB23
AA23
Y23
W25
AA25
AA24
Y21
DDR_1_5V
C221
0.22UF
C222
C225
0.22UF 22UF
When using data bit swapping the low order bit of each
byte must reside at bit 0 of the byte. The remaining 7 data
bits can be swapped freely. This restriction is for write
leveling calibration.
Example D0 to D0 or D0 to D8, and D1-7 can be swapped.
When swapping byte lanes on 16-bit memories, remember
to move the DQMx, DQSx, and DQSx_B signals for that byte
lane.
3
Design
Review
Authorize
Standardize
2
<design>
element14
Title
SABRE Lite
Size Doc Name
A3
05.IMX6Q_DDR3
Date
Saturday, June 08, 2013
1
A
<review>
<authorize>
<standardize>
Ver.
D
Sheet
5
of
17
5
4
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