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DDR4协议-JESD79-4B

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标签：数字电路 PCB IC设计/制造

为DDR4的4b协议

JEDEC

STANDARD

DDR4 SDRAM

JUNE 2017

JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

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(Revision of JESD79-4A, November 2013)

JESD79-4B

NOTICE

JEDEC standards and publications contain material that has been prepared, reviewed, and

approved through the JEDEC Board of Directors level and subsequently reviewed and approved

by the JEDEC legal counsel.

JEDEC standards and publications are designed to serve the public interest through eliminating

misunderstandings between manufacturers and purchasers, facilitating interchangeability and

improvement of products, and assisting the purchaser in selecting and obtaining with minimum

delay the proper product for use by those other than JEDEC members, whether the standard is to

be used either domestically or internationally.

JEDEC standards and publications are adopted without regard to whether or not their adoption

may involve patents or articles, materials, or processes. By such action JEDEC does not assume

any liability to any patent owner, nor does it assume any obligation whatever to parties adopting

the JEDEC standards or publications.

The information included in JEDEC standards and publications represents a sound approach to

product specification and application, principally from the solid state device manufacturer

viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or

publication may be further processed and ultimately become an ANSI standard.

Published by

©JEDEC Solid State Technology Association 2017

3103 North 10th Street

Suite 240 South

Arlington, VA 22201-2107

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Inquiries, comments, and suggestions relative to the content of this JEDEC standard or

publication should be addressed to JEDEC at the address below, or refer to

www.jedec.org

under

Standards and Documents for alternative contact information.

Printed in the U.S.A.

No claims to be in conformance with this standard may be made unless all requirements stated in

the standard are met.

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This document is copyrighted by JEDEC and may not be

reproduced without permission.

For information, contact:

JEDEC Solid State Technology Association

3103 North 10th Street

Suite 240 South

Arlington, VA 22201-2107

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or refer to

www.jedec.org

under Standards-Documents/Copyright Information.

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JEDEC Standard No. 79-4B

DDR4 SDRAM STANDARD

1 Scope ............................................................................................................................................................................1

2 DDR4 SDRAM Package Pinout and Addressing ......................................................................................................2

2.1 DDR4 SDRAM Row for X4, X8 and X16.......................................................................................................................2

2.2 DDR4 SDRAM Ball Pitch ...............................................................................................................................................2

2.3 DDR4 SDRAM Columns for X4,X8 and X16..................................................................................................................2

2.4 DDR4 SDRAM X4/8 Ballout using MO-207 ................................................................................................................ 2

2.5 DDR4 SDRAM X16 Ballout using MO-207 ....................................................................................................................3

2.6 DDR4 SDRAM X32 Ballout using MO-XXX ...................................................................................................................4

2.7 Pinout Description ..........................................................................................................................................................6

2.8 DDR4 SDRAM Addressing.............................................................................................................................................7

2.9 DDP Single Rank(SR) x16 from two x8 .........................................................................................................................9

3 Functional Description .............................................................................................................................................11

3.1 Simplified State Diagram .......................................................................................................................................... 11

3.2 Basic Functionality .......................................................................................................................................................12

3.3 RESET and Initialization Procedure.............................................................................................................................12

3.3.1 Power-up Initialization Sequence ..............................................................................................................................12

3.3.2 VDD Slew rate at Power-up Initialization Sequence .................................................................................................13

3.3.3 Reset Initialization with Stable Power .......................................................................................................................14

3.4 Register Definition........................................................................................................................................................14

3.4.1 Programming the mode registers ..............................................................................................................................14

3.5 Mode Register..............................................................................................................................................................17

4 DDR4 SDRAM Command Description and Operation ...........................................................................................28

4.1 Command Truth Table..................................................................................................................................................28

4.2 CKE Truth Table ...........................................................................................................................................................29

4.3 Burst Length, Type and Order......................................................................................................................................30

4.3.1 BL8 Burst order with CRC Enabled ...........................................................................................................................30

4.4 DLL-off Mode & DLL on/off Switching procedure ........................................................................................................31

4.4.1 DLL on/off switching procedure .................................................................................................................................31

4.4.2 DLL “on” to DLL “off” Procedure ................................................................................................................................31

4.4.3 DLL “off” to DLL “on” Procedure ................................................................................................................................32

4.5 DLL-off Mode ...............................................................................................................................................................33

4.6 Input Clock Frequency Change ...................................................................................................................................34

4.7 Write Leveling ..............................................................................................................................................................35

4.7.1 DRAM setting for write leveling & DRAM termination function in that mode .............................................................36

4.7.2 Procedure Description................................................................................................................................................36

4.7.3 Write Leveling Mode Exit............................................................................................................................................37

4.8 Temperature controlled Refresh modes .......................................................................................................................38

4.8.1 Normal temperature mode ( 0°C =< TCASE =< 85°C ) ............................................................................................38

4.8.2 Extended temperature mode ( 0°C =< TCASE =< 95°C ) .........................................................................................38

4.9 Fine Granularity Refresh Mode ....................................................................................................................................39

4.9.1 Mode Register and Command Truth Table ................................................................................................................39

4.9.2 tREFI and tRFC parameters.......................................................................................................................................40

4.9.3 Changing Refresh Rate..............................................................................................................................................40

4.9.4 Usage with Temperature Controlled Refresh mode ...................................................................................................41

4.9.5 Self Refresh entry and exit .........................................................................................................................................41

4.10 Multi Purpose Register ................................................................................................................................................41

4.10.1 DQ Training with MPR..............................................................................................................................................41

4.10.2 MR3 definition .........................................................................................................................................................41

4.10.3 MPR Reads .............................................................................................................................................................42

4.10.4 MPR Writes .............................................................................................................................................................44

4.10.5 MPR Read Data format ...........................................................................................................................................47

4.11 Data Mask(DM), Data Bus Inversion (DBI) and TDQS................................................................................................52

Contents

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文档解析

JEDEC标准号79-4B是一份详细规定了DDR4 SDRAM的规格和操作的文档，它包括特性、功能、交流(AC)和直流(DC)特性、封装以及球/信号分配。该标准基于DDR3标准(JESD79-3)以及DDR和DDR2标准(JESD79, JESD79-2)的某些方面制定，旨在定义JEDEC兼容的2Gb至16Gb x4、x8和x16 DDR4 SDRAM设备的最小要求集。

文档涵盖了从电源初始化序列、模式寄存器设置、命令描述、操作到各种电气特性和时序参数的全面信息。它详细描述了DDR4 SDRAM的内部配置，如16个银行、4个银行组以及8n预取架构，这些设计使得DDR4 SDRAM能够实现高速操作。此外，还介绍了读/写操作的突发特性、命令真值表、时钟频率变化、写入均衡、温度控制的刷新模式、多用途寄存器(MPR)、数据掩码(DM)、数据总线反转(DBI)和TDQS等功能。

此外，标准还包括了ZQ校准命令、DQ Vref训练、每个DRAM地址的可寻址性、CAL模式、CRC功能、命令地址奇偶校验(CA Parity)、控制减速模式、DDR4核心时序、可编程前缀、后缀、激活命令、预充电命令、读操作、写操作、刷新命令、自刷新操作、低功耗自动自刷新、电源下降模式、最大电源节省模式、连接性测试模式、CLK到读DQS时序参数、后封装修复(hPPR)和软后封装修复(sPPR)等高级特性。

该文档适用于固态技术协会(JEDEC)的成员以及其他希望使用JEDEC标准的制造商和购买者，以确保产品规格和应用的正确性，促进产品的可交换性，并帮助购买者选择和获取适当的产品。

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