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T
AN-657
APPLICATION NOTE
ADN2812 Evaluation Board
By Kevin Buckley
3. It is unnecessary to make any connections to the I
2
C
interface of the ADN2812 for normal operation.
4. Apply a 3.3 V supply to vector pins VCC and GND, TP5
andTP4, respectively. No supply needs to be connected
to I
2
C_VCC and GND, TP11 and TP10, respectively, for
the ADN2812 to operate. Those pins are used in case
an external I
2
C interface requires power to be supplied
via the target (the ADN2812 evaluation board).
5. Connect PIN/NIN to a pattern generator that can supply
a differential input to the ADN2812. It is important to
use cables of matching length.
6. Connect CLKOUTP/N, DATAOUTP/N to measurement
equipment using cables of matching length.
7. Apply a single-ended or differential NRZ data pattern
to the inputs of the ADN2812.The frequency of the data
pattern can be set to any data rate from 10 Mbps to 2.7
Gbps. An amplitude of >100 mV p-p is recommended
for initial testing. The recovered clock and retimed data
will be present at the CLKOUTP/N and DATAOUTP/N
outputs, respectively.
INTRODUCTION
This application note describes the use of the
EVAL-ADN2812EB. The ADN2812 is a continuous rate clock-
recovery, data-retiming device based on a multiloop PLL
architecture. The ADN2812 can automatically lock to any
data rate from 10 Mbps to 2.7 Gbps, recover the clock,
and retime the data without programming and without
the need for an external reference clock as an acquisi-
tion aid. An I
2
C
“
interface is available to access special
features of the ADN2812; however, it is not required for
normal operation.
The EVAL-ADN2812EB is fabricated using standard FR-4
materials. All high speed differential signal traces are
matched to within 3 mils length and maintain a 50
characteristic impedance to preserve signal integrity.
QUICK START GUIDE FOR NORMAL OPERATING MODE
(NO REFCLK AND NO I
2
C PROGRAMMING REQUIRED)
1. Populate jumpers P2 and P3. This disables the SLICE
adjust function by tying those pins to GND.
2. Populate jumpers P4 and P6 to tie off the REFCLK
inputs. P4 connects REFCLKP to VCC and P6 connects
REFCLKN to GND. Note that a reference clock is not
required as an acquisition aid for the ADN2812. The
device will lock to any rate without the use of any
REFCLK.
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POWER SUPPLY
The ADN2812 evaluation board requires a single 3.3 V
nominal supply for basic operation.This supply is brought
on board through vector pins VCC (TP5) and GND (TP4)
PIN/NIN INPUTS
PIN/NIN inputs are brought onto the ADN2812 evaluation
board through SMA connectors J3 and J4. Capacitors C3,
C4 provide ac coupling to the on-chip 50
termination
resistors. The capacitors used are 1.5
F
X7R ceramic
,
chip capacitors. It is recommended that the inputs to the
ADN2812 are ac-coupled.
If dc coupling is required, C3 and C4 would need to be
replaced with 0
resistors.The common-mode level of the
input signal must be greater than 2.3 V and the maximum
input level cannot exceed 1 V p-p on either PIN or NIN.
CLOCK/DATA OUTPUTS
The CLKOUTP CLKOUTN and DATAOUTP DATAOUTN
,
,
outputs are CML type outputs. CLKOUTP and CLKOUTN
are brought out through 0.1
F
ac coupling caps to SMA
connectors J13 and J14, respectively. DATAOUTP and
DATAOUTN are brought out through 0.1
F
ac coupling
caps to SMA connectors J1 and J2, respectively.
There are 100
resistors to VCC placed at each of the
outputs, R1–R4. These are in parallel with on-chip 100
resistors to VCC to provide a 50
near-side termination
for the CML outputs.
R10, R11, R16, and R17 are resistive terminations to GND
that should not be populated for the CML output version
of the ADN2812.
SLICEP/SLICEN
SLICE allows the ADN2812's input quantizer decision level
to be adjusted to accommodate amplified spontaneous
emission (ASE) in long optical links that use fiber ampli-
fiers. The slicing level can be adjusted by up to
100
mV
by applying a differential input voltage of up to
1
V to
SLICEP/SLICEN.
The SLICEP and SLICEN inputs are brought onto the
ADN2812 evaluation board through SMA connectors J6
and J5, respectively. When not being used, the SLICEN/
SLICEP inputs should be tied to GND using the jumpers
P2 and P3.
LOOP FILTER CAPACITOR
The loop filter capacitor, C
F
, is connected between CF1
and CF2, pins 14 and 15. The C
F
capacitor needs to be a
low leakage, 0.47
F
ceramic chip capacitor, >6.3 V,
20%.
The leakage of the capacitor needs to be <10 nA. If a leak-
age specification is not available for the capacitor, the
leakage can be calculated using the insulation resistance
specification. Assuming a max voltage of 3 V across the
C
F
capacitor, the leakage will be equal to
3
V/I.R.
V
where
I.R.
is the capacitor’s insulation resistance.
The capacitor used on the ADN2812 evaluation board
is a 0.47
F
ceramic chip capacitor, X7R dielectric, 1G
insulation resistance.
LOSS OF SIGNAL DETECTOR
The ADN2812 has an on-chip loss of signal (LOS) detec-
tor. The LOS detector detects when the input level drops
below a user programmable threshold and asserts an
alarm on the SDOUT output pin. The threshold is set by
connecting a resistor between the THRADJ pin and VEE.
The ADN2812 comes populated with a 10 k THRADJ
resistor, R6, which corresponds to a LOS threshold of
~5 mV p-p. If the input level drops below this threshold,
the SDOUT pin will be asserted to a logic 1 by default.
Writing a 1 to I
2
C register bit CTRLC[2] will configure the
SDOUT pin to be active low.
There is an LED on the EVAL-ADN2812EB that will turn on
when the SDOUT pin signals a loss of signal condition.This
is only true if SDOUT is configured to be active high.
LOSS OF LOCK DETECTOR
The ADN2812 has a loss of lock (LOL) detector that signals
when the ADN2812 has lost lock. Detailed descriptions of the
various modes of operation of the LOL detector can be found
in the ADN2812 data sheet. The LOL pin will be asserted to
a logic 1 when a loss of lock condition has been detected.
There is an LED on the EVAL-ADN2812EB that will turn on
when the LOL pin signals a loss of lock condition.
I
2
C INTERFACE
The ADN2812 supports a 2-wire, I
2
C compatible serial bus
driving multiple peripherals.Two inputs, serial data (SDA)
and serial clock (SCK), carry information between any device
connected to the bus. There are two ways to interface to
the I
2
C. There is a 4-pin header that has the SCK, SDA, I
2
C
supply, VEE. There is also a Molex 15-83-0064 receptacle
available to the user. If the I
2
C controller interfacing with
the ADN2812 requires that the EVAL-ADN2812EB supply the
power, then a power supply can be attached to TP11.
The SCK and SDA pins are open collector outputs that
are pulled up to 3.3 V on the EVAL-ADN2812EB with 1.8 k
resistors, R9 and R22. The SDA and SCK pins should not
be connected to an I
2
C controller that has pull-ups to 5 V.
This could damage the device.
The slave address of the ADN2812 is a 7-bit word where
the MSB, SADDR6 is factory programmed to a 1; SADDR5
can be set to a 1 or a 0 by the SADDR5 jumper on the eval
board. SADDR[4...0] are all set to 0 on chip.
Detailed descriptions of the I
2
C programmability and func-
tionality can be found in the ADN2812 data sheet.
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AN-657
REFERENCE CLOCK (OPTIONAL)
There are two optional uses for a reference clock on the
ADN2812.The reference clock can be used to read back the
acquired data rate to within 100 ppm, and there is also a
lock-to-reference mode where the ADN2812 is programmed
to lock to a specific data rate using the reference clock as
an acquisition aid. There is a detailed description of the
reference clock modes in the ADN2812 data sheet.
The reference clock is brought onto the EVAL-ADN2812EB
on J9, REFCLKP and J8, REFCLKN. The ADN2812 refer-
ence clock input buffer accepts any differential signal
with a peak-to-peak differential amplitude of greater than
100 mV (e.g., LVPECL or LVDS) or a standard single-ended
low voltageTTL input, providing maximum system flexibil-
ity. Phase noise and duty cycle of the reference clock are not
critical and 100 ppm accuracy is sufficient. Reference clock
frequencies from 10 MHz to 160 MHz are supported.
When the reference clock is not being used, REFCLKP should
be tied to VCC with P4 and REFCLKN can be left floating
or tied to VEE with jumper P6. If a high speed reference
clock is used, a 100
differential characteristic impedance
should be maintained. R5 should then be populated with a
100
0603 chip resistor. The REFCLK PCB traces are 50
transmission lines.
TEST POINTS
Test points are supplied on a 10-pin, 5
2 header as
follows:
1
SQUELCH
SDOUT
LOL
SDA
SCK
9
10
2
SLICEN
SLICEP
VCC
SADDR5
VEE
resistors in the signal path must be considered. When a large
number of consecutive identical digits (CIDs) are applied,
the capacitor voltage can droop due to baseline wander,
causing pattern dependent jitter (PDJ).
The user must determine how much droop is tolerable and
choose an ac coupling capacitor based on that amount
of droop. The amount of PDJ can then be approximated
based on the capacitor selection. The actual capacitor
value selection may require some trade-offs between
droop and PDJ.
Assuming that 2% droop can be tolerated, the maximum
differential droop will be 4%. Normalizing to V p-p:
t/–
Droop
=
V
= 0.04
V
= 0.5
V p-p
(1–e
t/–t
)
V
therefore
t
= 12t
where:
t
= RC time constant
(C is the ac coupling cap, R = 100
seen by C)
t
= total discharge time =
nT
n
= number of CIDs
T
= bit period
The capacitor value can then be calculated by combining
the equations for
t
and t:
C = 12nT/
R
nT
nT/
Once the capacitor value is selected, the PDJ can be
approximated as
nT/RC
nT/RC)
PDJ
pspp
= 0.5
t
r
(1–e
(–nT/RC)
)/0.6
where:
PDJ
pspp
= amount of pattern dependent jitter allowed;
< 0.01 UI p-p typical
t
r
= rise time = 0.22/BW, where BW ~ 0.7(Bit Rate)
This expression for t
r
is accurate only for the inputs; the
output rise time for the ADN2812 is ~100 ps regardless
of data rate.
The EVAL-ADN2812EB comes populated with 1.5
F
ac
coupling capacitors on the inputs and 0.1
F
ac coupling
capacitors on the outputs. For lower data rates, e.g., in
the tens of MHz, and/or very high numbers of consecutive
identical digits, these values may not be optimum.
CHOOSING AC COUPLING CAPACITORS
The choice of ac coupling capacitors at the input (PIN, NIN)
and output (dataoutp, dataoutn) of the ADN2812 must be
chosen such that the device works properly over the full
range of data rates used in the application. When choosing
the capacitors, the time constant formed with the two 50
REV. 0
–3–
AN-657
C5
0.1F
C10
0.1F
C19
1.0nF
C23
0.1F
C22
1.0nF
C21
0.1F
C20
1.0nF
C6
1.0nF
C8
0.1F
C7
1.0nF
C25
22F
VCC
TP5
GND
GND
GND
R14
0
R15
0
GND
VCC
GND
GND
GND
BERG69157-102
1
2
GND
GND
R12
0
R13
0
GND
VCC
J5
J6
J3
C4
1.5F
J4
GND
GND
GND
C3
1.5F
GND
BERG69157-102
P3
GND
1
2
GND
C26
0.1F
VCC
C11
0.1F
R24
GND
10k
GND
J1
J2
GND
R6
10k
VEE1
SLICEN
PIN
VREF
SLICEP
VCC1
NIN
P4
GND GND
C17 VCC
J5 0.1F
BERG69157-102
9
10
11
VCC
GND
C18
0.47F
12
13
14
15
16
TEST1
C9
0.1F
2
1
C27
GND 0.1F
8
VCC
C14
0.1F
R10
169
C15
0.1F
R2
100
C1
0.1F
VCC
GND
R1
100
7
6
5
4
3
2
1
GND
PAD
32
31
30
29
28
27
26
25
R3
100
C2
0.1F
VCC
GND
R4
100
GND
R23
10k
GND
R11
169
PAD
THRADJ
REFCLKP
REFCLKN
VCC2
VEE2
CF2
CF1
SADDR5
LOL
VCC4
VEE4
SDOUT
TEST2
VCC3
VEE3
VCC
VCC
R5
100
GND
J8 C16
0.1F
GND
1
P6
2
BERG69157-102
LOL
RED
ADN2812
U1
DATAOUTP
DATAOUTN
SQUELCH
CLKOUTP
CLKOUTN
VCC5
VEE5
TP2
GND
TP4
R17
169
GND
TP8
GND
TP9
SQUELCH
C13
0.1F
GND
C28
22F
GND
SCK
GND
17 18 19 20 21 22 23 24
GND
GND
VCC
VCC
SADDR5
SCK
R9
1.8k
SDA
R22
1.8k
I2C_SUPPLY
VCC
LOS
R8
10k
LOS
RED
SADDR5
1
2
3
GND
MOLEX22-03-2031
SAMTECT5W10608G54PIN
SDA
R7
10k
LOL
GND
R16
169
GND
C12
0.1F
I2C_SUPPLY
TP11
VCC
VCC
J14
GND
GND
J13
GND
SQUELCH
SLICEN
LOS
SLICEP
LOL
VCC
SDA
SADDR5
SCK
GND
P1
P7
GND
1
2
3
4
5
6
SHIELD
PINS
1
2
3
4
MOLEX15-83-0064
P5
1
2
3
4
5
6
7
8
9
10
3M2510-5002UB
Figure 1. EVAL-ADN2812EB
–4–
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AN-657
Figure 2. Primary Layer
Figure 4. Secondary Layer
Figure 3. VEE Plane
Figure 5. VEE Plane
REV. 0
–5–
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