5
4
3
2
1
Cyclone III Starter Board
D
D
SCHEMATIC
TOP
EP3C25
IN/OUT
MEMORY
POWER
USB BLASTER
CONTENT
COVER PAGE, TOP
EP3C25 BANK1..BANK8, POWER, CONFIG
CLOCK, LEVEL SHIFT, KEY, CONNECT, HSMC
DDR, SSRAM, FLASH
POWER
USB BLASTER
PAGE
01 ~ 03
04 ~ 08
09 ~ 11
12 ~ 14
15 ~ 16
17 ~ 17
C
C
B
B
A
A
Title
Altera Cyclone III Eval Board
Size
B
Date:
5
4
3
2
Document Number
COVER PAGE
Tuesday, April 17, 2007
Sheet
1
Rev
1.2
1
of
17
5
4
3
2
1
D
D
C
C
B
B
A
A
Title
Altera Cyclone III Eval Board
Size
B
Date:
5
4
3
2
Document Number
PLACEMENT
Tuesday, April 17, 2007
Sheet
1
Rev
1.2
2
of
17
5
4
3
2
1
D
D
EP3C25
Memory
DDR_CLK_p
DDR_CLK_n
DDR_CKE
DDR_BA0
DDR_BA1
DDR_WE_n
DDR_CAS_n
DDR_RAS_n
DDR_CS_n
DDR_DM0
DDR_DM1
DDR_DQS0
DDR_DQS1
DDR_A[0..12]
PAGE 12-14
DDR_CLK_p
DDR_CLK_n
DDR_CKE
DDR_BA0
DDR_BA1
DDR_WE_n
DDR_CAS_n
DDR_RAS_n
DDR_CS_n
DDR_DM0
DDR_DM1
DDR_DQS0
DDR_DQS1
DDR_A[0..12]
DDR_DQ[0..15]
DDR_CLK_p
DDR_CLK_n
DDR_CKE
DDR_BA0
DDR_BA1
DDR_WE_n
DDR_CAS_n
DDR_RAS_n
DDR_CS_n
DDR_DM0
DDR_DM1
DDR_DQS0
DDR_DQS1
DDR_A[0..12]
DDR_DQ[0..15]
SRAM_CLK
SRAM_WE_n
SRAM_CE1_n
SRAM_OE_n
SRAM_ADSC_n
SRAM_BE_n[0..3]
FLASH_SRAM_A[1..25]
FLASH_SRAM_DQ[0..31]
PAGE 4-8
DDR_CLK_p
DDR_CLK_n
DDR_CKE
DDR_BA0
DDR_BA1
DDR_WE_n
DDR_CAS_n
DDR_RAS_n
DDR_CS_n
DDR_DM0
DDR_DM1
DDR_DQS0
DDR_DQS1
DDR_A[0..12]
DDR_DQ[0..15]
DDR_DQ[0..15]
Clock, LED, Tact SW, HSMC
PAGE 9-11
50MHZ
50MHZ
KEY[0..3]
nCONFIG
CPU_RST_n
CIII_TDI
TMS
TCK
HSMC_SCL
HSMC_CLKIN0
HSMC_CLKIN_p[1..2]
HSMC_CLKIN_n[1..2]
HSMC_TX_p[4..16]
HSMC_TX_n[4..16]
C
C
SRAM_CLK
SRAM_WE_n
SRAM_CE1_n
SRAM_OE_n
SRAM_ADSC_n
SRAM_BE_n[0..3]
FLASH_SRAM_A[1..25]
SRAM_CLK
SRAM_WE_n
SRAM_CE1_n
SRAM_OE_nFLASH_SRAM_DQ[0..31]
SRAM_ADSC_n
SRAM_BE_n[0..3]
FLASH_SRAM_A[1..25]
FLASH_CLK
FLASH_RESET_n
FLASH_WE_n
FLASH_CE_n
FLASH_OE_n
FLASH_ADV_n
FLASH_WAIT
FLASH_SRAM_DQ[0..31]
SRAM_CLK
SRAM_WE_n
SRAM_CE1_n
SRAM_OE_n
SRAM_ADSC_n
SRAM_BE_n[0..3]
FLASH_SRAM_A[1..25]
FLASH_SRAM_DQ[0..31]
LED[0..3]
KEY[0..3]
CPU_RST_n
LED[0..3]
KEY[0..3]
CPU_RST_n
LED[0..3]
CONF
LED[0..3]
CONF
KEY[0..3]
nCONFIG
CPU_RST_n
JTAG_TDO
HSMC_SCL
HSMC_SDA
HSMC_CLKIN0
HSMC_CLKIN_p[1..2]
HSMC_CLKIN_n[1..2]
HSMC_CLKOUT0
HSMC_CLKOUT_p[1..2]
HSMC_CLKOUT_n[1..2]
HSMC_TX_p[4..16]
HSMC_TX_n[4..16]
HSMC_RX_p[4..16]
HSMC_RX_n[4..16]
HSMC_D[0..19]
LF_TDI
LF_TDO
LF_TMS
LF_TCK
HSMC_SCL
HSMC_CLKIN0
HSMC_CLKIN_p[1..2]
HSMC_CLKIN_n[1..2]
HSMC_TX_p[4..16]
HSMC_TX_n[4..16]
FLASH_CLK
FLASH_RESET_n
FLASH_WE_n
FLASH_CE_n
FLASH_OE_n
FLASH_ADV_n
FLASH_WAIT
FLASH_CLK
FLASH_RESET_n
FLASH_WE_n
FLASH_CE_n
FLASH_OE_n
FLASH_ADV_n
FLASH_WAIT
HSMC_SCL
HSMC_SDA
FLASH_CLK
FLASH_RESET_n
FLASH_WE_n
FLASH_CE_n
FLASH_OE_n
FLASH_ADV_n
FLASH_WAIT
HSMC_CLKIN0
HSMC_CLKIN_p[1..2]
HSMC_CLKIN_n[1..2]
HSMC_CLKOUT0
HSMC_CLKOUT_p[1..2]
HSMC_CLKOUT_n[1..2]
HSMC_TX_p[4..16]
HSMC_TX_n[4..16]
HSMC_SDA
HSMC_CLKOUT0
HSMC_CLKOUT_p[1..2]
HSMC_CLKOUT_n[1..2]
HSMC_RX_p[4..16]
HSMC_RX_n[4..16]
HSMC_D[0..19]
HSMC_SDA
HSMC_CLKOUT0
HSMC_CLKOUT_p[1..2]
HSMC_CLKOUT_n[1..2]
HSMC_RX_p[4..16]
HSMC_RX_n[4..16]
HSMC_D[0..19]
B
USB BLASTER
CIII_TDO
FLASH_CE_n
PAGE 17
JTAG_TDO
TMS
TCK
nCE
CONF
CONF_DONE
nSTATUS
JTAG_TDI
FLASH_CE_n
JTAG_TDO
JTAG_TMS
JTAG_TCK
nCE
CONF
CONF_DONE
nSTATUS
CIII_TDI
CIII_TDO
TMS
TCK
nCE
nCONFIG
CONF_DONE
nSTATUS
LINK_D0
LINK_D1
LINK_D2
LINK_D3
50MHZ
CIII_TDI
CIII_TDO
CIII_TMS
CIII_TCK
nCE
nCONFIG
CONF_DONE
nSTATUS
LINK_D0
LINK_D1
LINK_D2
LINK_D3
50MHz
HSMC_RX_p[4..16]
HSMC_RX_n[4..16]
HSMC_D[0..19]
B
Power
PAGE 15-16
LINK_D3
LINK_D3
LINK_D0
LINK_D1
LINK_D2
LINK_D0
LINK_D1
LINK_D2
A
A
Title
Altera Cyclone III Eval Board
Size
B
Date:
5
4
3
2
Document Number
TOP LEVEL
Tuesday, April 17, 2007
Sheet
1
Rev
1.2
3
of
17
5
4
3
2
1
D
D
HSMC_TX_p[4..16]
HSMC_TX_n[4..16]
HSMC_RX_p[4..16]
HSMC_RX_n[4..16]
FLASH_SRAM_DQ[0..31]
HSMC_D[0..19]
KEY[0..1]
U1A
HSMC_RX_p5
C
U1B
HSMC_TX_p6
HSMC_TX_n6
HSMC_RX_p6
HSMC_TX_p8
HSMC_TX_p7
HSMC_TX_n7
HSMC_RX_p7
HSMC_RX_n7
HSMC_RX_p8
HSMC_RX_n8
HSMC_TX_p9
HSMC_RX_p9
HSMC_RX_n9
HSMC_D2
F2
F1
F3
KEY1
KEY0
HSMC_SCL
HSMC_RX_n6
HSMC_TX_n15
K2
K1
K5
M2
L2
L1
L4
L3
P2
P1
R2
T3
R3
M5
L5
R4
LVDSL_7P/DQ1L6
LVDSL_7N/DQ1L7
LVDSL_8P/DQ1L8
LVDSL_11P/DQS1L
LVDSL_9P/DQ3L0
LVDSL_9N/DQ3L1
LVDSL_10P/DQ3L2
LVDSL_10N/DQ3L3
LVDSL_12P/DQ3L4
LVDSL_12N/DQ3L5
LVDSL_13P/DQ3L6
LVDSL_14P/DQ3L7
LVDSL_14N/DQ3L8
DQS3L
LVDSL_8N/DM1L
LVDSL_15N/DM3L
EP3C25F324
CLK2/LVDSCLK1p
CLK3/LVDSCLK1n
IO/VREF0B2
LVDSL_11N
LVDSL_13N
LVDSL_15P
M1
R1
R5
HSMC_TX_n8
HSMC_TX_n9
HSMC_TX_p15
C
H2
B2
C1
D2
E1
G2
G1
D3
LVDSL_6P/DQS0L
LVDSL_1P/DQ1L0
LVDSL_2N/DQ1L1
LVDSL_3P/DQ1L2
LVDSL_4N/DQ1L3
LVDSL_5P/DQ1L4
LVDSL_5N/DQ1L5
DQS2L
HSMC_TX_p4
HSMC_RX_n4
FLASH_SRAM_DQ19
HSMC_SDA
HSMC_TX_p5
HSMC_TX_n5
HSMC_D1
BANK 1
IO/nRESET
C3
H6
FLASH_RESET_n
HSMC_D0
BANK 2
IO2_0
IO/RUP1
IO/RDN1
L6
T2
T1
N2
N1
M3
HSMC_D3
HSMC_D7
HSMC_D4
CPU_RST_n
HSMC_D5
HSMC_TX_n4
HSMC_RX_p4
FLASH_SRAM_DQ1
FLASH_CE_n
HSMC_RX_n5
B1
C2
D1
E2
H1
LVDSL_1N
LVDSL_2P
IO1_0
LVDSL_3N/DATA1
CLK0/LVDSCLK0p
LVDSL_4P/FLASH_nCE CLK1/LVDSCLK0n
LVDSL_6N
EP3C25F324
IO/VREF0B1
B
B
A
A
Title
Altera Cyclone III Eval Board
Size
B
Date:
5
4
3
2
Document Number
EP2C35 BANK1(I/O : 2.5V) and BANK 2(I/O : 2.5V)
Tuesday, April 17, 2007
Sheet
1
Rev
1.2
4
of
17
5
4
3
2
1
D
D
LED[0..3]
DDR_DQ[0..15]
DDR_A[0..12]
HSMC_RX_p[4..16]
HSMC_D[0..19]
HSMC_RX_n[4..16]
U1C
DDR_A6
DDR_A3
DDR_DQ7
DDR_DQ6
DDR_DQ5
DDR_DQ4
DDR_DQ2
DDR_DQ3
DDR_DQ1
DDR_DQ0
DDR_DQS0
DDR_DQS1
DDR_DM0
DDR_DM1
DDR_A0
DDR_CS_n
HSMC_RX_p15
HSMC_RX_n15
DDR_CAS_n
HSMC_D6
DDR_A1
DDR_A4
B
U1D
LVDSB_11P
U7
DDR_A2
DDR_CKE
LED1
DDR_A9
DDR_RAS_n
DDR_DQ13
DDR_DQ11
DDR_DQ15
DDR_DQ12
DDR_DQ14
DDR_DQ8
DDR_DQ9
DDR_DQ10
R13
P12
V13
V16
R11
V15
V14
U14
P10
U13
U12
U11
V11
V12
P11
U15
U16
N10
N11
U17
V17
P13
LVDSB_23N/DQS0B
DQS2B
LVDSB_16N/DQS4B
LVDSB_20N/DQ5B0
DQ5B1
LVDSB_19N/DQ5B2
LVDSB_18N/DQ5B3
LVDSB_18P/DQ5B4
LVDSB_17P/DQ5B5
LVDSB_16P/DQ5B6
LVDSB_14P/DQ5B7
LVDSB_13P/DQ5B8
LVDSB_13N
LVDSB_14N
LVDSB_17N
LVDSB_19P
LVDSB_20P
LVDSB_21P
LVDSB_21N
LVDSB_22P
LVDSB_22N
LVDSB_24P
EP3C25F324
CLK13/LVDSCLK7p
CLK12/LVDSCLK7n
PLL4_OUTp
PLL4_OUTn
IO/VREF0B4
IO/RUP2
IO/RDN2
T13
T14
U10
V10
U18
V18
T11
DDR_A8
DDR_A7
LINK_D1
LINK_D2
HSMC_CLKOUT_p2
HSMC_CLKOUT_n2
VCC125
B
P6
U8
V7
V6
U6
P9
R8
V5
V4
U4
U3
T8
V3
V8
U1
V1
M6
N6
T4
N7
U5
P8
DQS1B
LVDSB_12P/DQ3B0
LVDSB_11N/DQ3B1
LVDSB_10N/DQ3B2
LVDSB_10P/DQ3B3
LVDSB_9N/DQ3B4
LVDSB_8P/DQ3B5
LVDSB_7N/DQ3B6
LVDSB_6N/DQ3B7
LVDSB_6P/DQ3B8
LVDSB_5P/DQS3B
LVDSB_8N/DQS5B
LVDSB_5N/DM3B
BANK
LVDSB_12N/DM5B
LVDSB_1P
LVDSB_1N
LVDSB_2P
LVDSB_2N
LVDSB_3P
LVDSB_4N
LVDSB_7P
LVDSB_9P
EP3C25F324
LVDSB_24N
LVDSB_25P
LVDSB_25N
N12
M13
N13
LED2
HSMC_RX_p16
HSMC_RX_n16
C
C
3
DDR_BA0
DDR_BA1
HSMC_D18
IO3_0
IO3_1
IO3_2
N8
N9
P7
U9
V9
U2
V2
T6
HSMC_D8
LED3
DDR_A5
LINK_D0
50MHz
DDR_CLK_p
DDR_CLK_n
VCC125
DDR_WE_n
DDR_A12
HSMC_D12
HSMC_D14
DDR_A10
DDR_A11
LED0
BANK 4
CLK15/LVDSCLK6p
CLK14/LVDSCLK6n
PLL1_OUTp
PLL1_OUTn
IO/VREF0B3
LED3
TP
0
LINK_D3
VCC125
VCC125
BC1
0.001U
BC2
0.1U
BC3
0.001U
BC4
0.1U
A
A
Title
Altera Cyclone III Eval Board
Size
B
Date:
5
4
3
2
Document Number
EP2C35 BANK3(I/O : 2.5V) and BANK 4(I/O : 3.3V)
Tuesday, April 17, 2007
Sheet
1
Rev
1.2
5
of
17
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