AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
SPRS717B
–
OCTOBER 2011
–
REVISED JANUARY 2012
AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs)
Check for Samples:
AM3359, AM3358
1 Device Summary
1.1
1234567
Features
–
32KB of L1 Instruction Cache with
Single-Error Detection (parity)
–
32KB of L1 Data Cache with Single
Error-Detection (parity)
–
256KB of L2 Cache with Error Correcting
Code (ECC)
–
176KB of On-Chip Boot ROM
–
64KB of Dedicated RAM
–
Emulation/Debug
•
JTAG
•
Embedded Trace Buffer
–
Interrupt Controller (up to 128 interrupt
requests)
•
On-Chip Memory (Shared L3 RAM)
–
64 KB of General-Purpose On-Chip Memory
Controller (OCMC) RAM
–
Accessible to all Masters
–
Supports Retention for Fast Wake-Up
•
External Memory Interfaces (EMIF)
–
mDDR/DDR2/DDR3 Controller:
•
mDDR: 200-MHz Clock (400-MHz Data
Rate)
•
DDR2: 266-MHz Clock (532-MHz Data
Rate)
•
DDR3: 303-MHz Clock (606-MHz Data
Rate)
•
16-Bit Data Bus
•
1 GB of Total Addressable Space
•
Supports One x16 or Two x8 Memory
Device Configurations
•
Supports Retention for Fast Wake-Up
–
General-Purpose Memory Controller (GPMC)
•
Flexible 8/16-Bit Asynchronous Memory
Interface with Up to seven Chip Selects
(NAND, NOR, Muxed-NOR, SRAM, etc.)
•
Uses BCH Code to Support 4-Bit, 8-Bit, or
16-Bit ECC
•
Uses Hamming Code to Support 1-Bit
ECC
•
Highlights
–
275-MHz, 500-MHz, 600-MHz, or 720-MHz
ARM
®
Cortex™-A8 32-Bit RISC
Microprocessor
•
NEON™ SIMD Coprocessor
•
32KB/32KB of L1 Instruction/Data Cache
with Single-Error Detection (parity)
•
256KB of L2 Cache with Error Correcting
Code (ECC)
–
mDDR(LPDDR)/DDR2/DDR3 Support
–
General-Purpose Memory Support (NAND,
NOR, SRAM, etc.) Supporting Up to 16-bit
ECC
–
SGX530 Graphics Engine
–
LCD Controller With WXGA Resolution at
60-Hz Refresh Rate
–
Programmable Real-Time Unit Subsystem
–
Real-Time Clock (RTC)
–
Up to Two USB 2.0 High-Speed OTG Ports
with Integrated PHY
–
10/100/1000 Ethernet Switch Supporting Up
to Two Ports
–
Serial Interfaces Including:
•
Two Controller Area Network Ports (CAN)
•
Six UARTs, Two McASPs, Two McSPI,
and Three I2C Ports
–
12-Bit Successive Approximation Register
(SAR) ADC
–
Up to Three 32-Bit Enhanced Capture
Modules (eCAP)
–
Up to Three Enhanced High-Resolution PWM
Modules (eHRPWM)
–
Crypto Hardware Accelerators (AES, SHA,
PKA, RNG)
•
MPU Subsystem
–
275-MHz, 500-MHz, 600-MHz, or 720-MHz
ARM
®
Cortex™-A8 32-Bit RISC
Microprocessor
–
NEON™ SIMD Coprocessor
1
2
3
4
5
6
7
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SmartReflex, DSP/BIOS, XDS are trademarks of Texas Instruments.
Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.
ARM is a registered trademark of ARM Ltd or its subsidiaries.
EtherCAT is a registered trademark of EtherCAT Technology Group.
POWERVR SGX is a trademark of Imagination Technologies Limited.
All other trademarks are the property of their respective owners.
Copyright
©
2011–2012, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of
development. Characteristic data and other specifications are design goals. Texas
Instruments reserves the right to change or discontinue these products without notice.
PRODUCT PREVIEW
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717B
–
OCTOBER 2011
–
REVISED JANUARY 2012
www.ti.com
–
Error Locator Module (ELM)
•
Used in Conjunction with the GPMC to
Locate Addresses of Data Errors from
Syndrome Polynomials Generated Using
a BCH Algorithm
•
Supports 4-Bit, 8-Bit, and 16-Bit per
512-byte Block Error Location Based on
BCH Algorithms
•
Programmable Real-Time Unit Subsystem
(PRUSS)
–
Two Programmable Real-Time Units (PRUs)
•
32-Bit Load/Store RISC Processor
Capable of Running at 200 MHz
•
8 KB Instruction RAM with Single-Error
Detection (parity)
•
8 KB Data RAM with Single-Error
Detection (parity)
•
Single-Cycle 32-Bit Multiplier with 64-Bit
Accumulator
•
Enhanced GPIO Module Provides
Shift-In/Out Support and Parallel Latch on
External Signal
–
12 KB of Shared RAM with Single-Error
Detection (parity)
–
Three 120-byte Register Banks Accessible
by Each PRU
–
Interrupt Controller Module (INTC) for
Handling System Input Events
–
Local Interconnect Bus for Connecting
Internal and External Masters to the
Resources Inside the PRUSS
–
Peripherals Inside the PRUSS
•
One UART Port with Flow Control Pins,
Supports Up to 12 Mbps
•
Two MII Ethernet Ports that Support
Industrial Ethernet, such as EtherCAT
®
•
One MDIO Port
•
One Enhanced Capture (eCAP) Module
•
Power Reset and Clock Management (PRCM)
Module
–
Controls the entry and Exit of Stand-By and
Deep-Sleep Modes
–
Responsible for Sleep Sequencing, Power
Domain Switch-Off Sequencing, Wake-Up
Sequencing and Power Domain Switch-On
Sequencing
–
Clocks
•
Integrated 15-35 MHz High-Frequency
Oscillator Used to Generate a Reference
Clock for Various System and Peripheral
Clocks
•
Supports Individual Clock Enable/Disable
Control for Subsystems and Peripherals
to Facilitate Reduced Power
Consumption
2
Device Summary
Five ADPLLs to Generate System Clocks
(MPU Subsystem, DDR Interface, USB
and Peripherals [MMC/SD, UART, SPI,
I2C, etc.], L3, L4, Ethernet, GFX [SGX530],
LCD Pixel Clock)
–
Power
•
Two Non-Switchable Power Domains
(Real-Time Clock [RTC], Wake-Up Logic
[WAKE-UP])
•
Three Switchable Power Domains (MPU
Subsystem [MPU], SGX530 [GFX],
Peripherals and Infrastructure [PER])
•
Implements SmartReflex™ Class 2B for
Core Voltage Scaling Based On Die
Temperature, Process Variation and
Performance (Adaptive Voltage Scaling
[AVS])
•
Dynamic Voltage Frequency Scaling
(DVFS)
•
Real-Time Clock (RTC)
–
Real-Time Date (Day/Month/Year/Day of
Week) and Time (Hours/Minutes/Seconds)
Information
–
Internal 32.768-kHz Oscillator, RTC Logic
and 1.1-V Internal LDO
–
Independent Power-on-Reset
(RTC_PWRONRSTn) Input
–
Dedicated Input Pin (EXT_WAKEUP) for
External Wake Events
–
Programmable Alarm Can be Used to
Generate Internal Interrupts to the PRCM (for
Wake Up) or Cortex-A8 (for Event
Notification)
–
Programmable alarm Can be Used with
External Output (PMIC_POWER_EN) to
Enable the Power Management IC to Restore
Non-RTC Power Domains
•
Peripherals
–
Up to Two USB 2.0 High-Speed OTG Ports
with Integrated PHY
–
Up to Two Industrial Gigabit Ethernet MACs
(10/100/1000 Mbps)
•
Integrated Switch
•
Each MAC Supports MII/RMII/RGMII and
MDIO Interfaces
•
Ethernet MACs and Switch Can Operate
Independent of Other Functions
•
IEEE 1588 Precision Time Protocol (PTP)
–
Up to Two Controller-Area Network (CAN)
Ports
•
Supports CAN Version 2 Parts A and B
–
Up to Two Multichannel Audio Serial Ports
(McASP)
•
Transmit/Receive Clocks Up to 50 MHz
•
Up to Four Serial Data Pins per McASP
Port with Independent TX/RX Clocks
Copyright
©
2011–2012, Texas Instruments Incorporated
•
PRODUCT PREVIEW
Submit Documentation Feedback
Product Folder Link(s):
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
SPRS717B
–
OCTOBER 2011
–
REVISED JANUARY 2012
–
–
–
–
–
–
–
–
–
Supports Time Division Multiplexing
(TDM), Inter-IC Sound (I2S), and similar
Formats
•
Supports Digital Audio Interface
Transmission (SPDIF, IEC60958-1, and
AES-3 Formats)
•
FIFO Buffers for Transmit and Receive
(256 bytes)
Up to Six UARTs
•
All UARTs Support IrDA and CIR Modes
•
All UARTs Support RTS and CTS Flow
Control
•
UART1 Supports Full Modem control
Up to Two Master/Slave McSPI Serial
Interfaces
•
Up to Two Chip Selects
•
Up to 48 MHz
Up to Three MMC/SD/SDIO Ports
•
1-Bit, 4-Bit and 8-Bit MMC/SD/SDIO
Modes
•
MMCSD0 has dedicated Power Rail for
1.8-V or 3.3-V Operation
•
Up to 48-MHz Data Transfer Rate
•
Supports Card Detect and Write Protect
•
Complies with MMC4.3 and SD/SDIO 2.0
Specifications
Up to Three I2C Master/Slave Interfaces
•
Standard Mode (up to 100 kHz)
•
Fast Mode (up to 400 kHz)
Up to Four Banks of General-Purpose IO
(GPIO)
•
32 GPIOs per Bank (Multiplexed with
Other Functional Pins)
•
GPIOs Can be Used as Interrupt Inputs
(Up to Two Interrupt Inputs per Bank)
Up to Three External DMA Event Inputs That
Can Also be Used as Interrupt Inputs
Eight 32-Bit General-Purpose Timers
•
DMTIMER1 is a 1-ms Timer Used for
Operating System (OS) Ticks
•
DMTIMER4 - DMTIMER7 are Pinned Out
One Watchdog Timer
SGX530 3D Graphics Engine
•
Tile-Based Architecture Delivering Up to
20 MPloy/sec
•
Universal Scalable Shader Engine is a
Multi-Threaded Engine Incorporating
Pixel and Vertex Shader Functionality
•
Advanced Shader Feature Set in Excess
of Microsoft VS3.0, PS3.0 and OGL2.0
•
Industry Standard API Support of
Direct3D Mobile, OGL-ES 1.1 and 2.0,
OpenVG 1.0, and OpenMax
•
Fine-Grained Task Switching, Load
•
–
–
–
–
–
Balancing and Power Management
•
Advanced Geometry DMA Driven
Operation for Minimum CPU Interaction
•
Programmable High-Quality Image
Anti-Aliasing
•
Fully Virtualized Memory Addressing for
OS Operation in a Unified Memory
Architecture
LCD Controller
•
Up to 24-Bits Data Output; 8-Bits per
Pixel (RGB)
•
Up to WXGA (1366x768) Resolution
•
Integrated LCD Interface Display Driver
(LIDD) Controller
•
Integrated Raster Controller
•
Integrated DMA Engine to Pull Data from
the External Frame Buffer without
Burdening the Processor via Interrupts or
a Firmware Timer
•
512-Word Deep Internal FIFO
•
Supported Display Types:
–
Character Displays - Uses LCD
Interface Display Driver (LIDD)
Controller to Program these Displays
–
Passive Matrix LCD Displays - Uses
LCD Raster Display Controller to
Provide Timing and Data for Constant
Graphics Refresh to a Passive Display
–
Active Matrix LCD Displays - Uses
External Frame Buffer Space and the
Internal DMA Engine to Drive
Streaming Data to the Panel. Maximum
Resolution is WXGA (1366x768) at
60-Hz Refresh Rate
12-Bit Successive Approximation Register
(SAR) ADC
•
100K Samples per Second
•
Input Can be Selected from any of the
Eight Analog Inputs Multiplexed Through
an 8:1 analog Switch
•
Can be Configured to Operate as a 4-wire,
5-wire, or 8-wire Resistive Touch Screen
Controller (TSC) Interface
Up to Three 32-Bit Enhanced Capture
Modules (eCAP)
•
Configurable as Three Capture Inputs or
Three Auxiliary PWM Outputs
Up to Three Enhanced High-Resolution PWM
Modules (eHRPWM)
•
Dedicated 16-Bit Time-Base Counter with
Time and Frequency Controls
•
Configurable as Six Single-Ended, Six
Dual-Edge Symmetric, or Three
Dual-Edge Asymmetric Outputs
Up to Three 32-Bit Enhanced Quadrature
Pulse Encoder (eQPE) Modules
Device Summary
3
Copyright
©
2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s):
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352
PRODUCT PREVIEW
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717B
–
OCTOBER 2011
–
REVISED JANUARY 2012
www.ti.com
•
Device Identification
–
Contains Electrical fuse Farm (FuseFarm) of
Which Some Bits are Factory Programmable
•
Production ID
•
Device Part Number (Unique JTAG ID)
•
Device Revision (readable by Host ARM)
•
Debug Interface Support
–
JTAG/cJTAG for ARM (Cortex-A8 and
PRCM), PRU Debug
–
Embedded Trace Buffer (ETB)
–
Supports Device Boundary Scan
–
Supports IEEE1500
•
DMA
–
On-Chip Enhanced DMA Controller (EDMA)
has Three Third-Party Transfer Controllers
(TPTC) and One Third-Party Channel
Controller (TPCC), Which Supports Up to 64
Programmable Logical Channels and Eight
QDMA Channels. EDMA is Used for:
•
Transfers to/from On-Chip Memories
•
Transfers to/from External Storage (EMIF,
General-Purpose Memory Controller,
Slave Peripherals)
•
Inter-Processor Communication (IPC)
–
Integrates Hardware-Based Mailbox for IPC
and Spinlock for Process Synchronization
Between the Cortex-A8, PRCM, and Each
PRU
•
Mailbox Registers that Generate
Interrupts
–
Four Initiators (Cortex-A8, PRCM,
PRU0, PRU1)
•
Spinlock has 128 Software-Assigned
Lock Registers
•
Security
–
Crypto Hardware accelerators (AES, SHA,
PKA, RNG)
•
Boot Modes
–
Boot Mode is Selected via Boot
Configuration Pins Latched on the Rising
Edge of the PWRONRSTn Reset Input Pin
•
Packages:
–
298-Pin S-PBGA-N298 package
(ZCE Suffix), 0.65-mm Ball Pitch
–
324-Pin S-PBGA-N324 package
(ZCZ Suffix), 0.80-mm Ball Pitch
PRODUCT PREVIEW
1.2
•
•
•
•
•
Applications
•
•
•
•
Connected Vending Machines
Weighing Scales
Educational Consoles
Advanced Toys
Gaming Peripherals
Home and Industrial Automation
Consumer Medical Appliances
Printers
Smart Toll Systems
1.3
Description
The AM335x microprocessors, based on the ARM Cortex-A8, are enhanced with image, graphics
processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The device
supports the following high-level operating systems (HLOSs) that are available free of charge from TI:
•
Linux
®
•
Windows
®
CE
•
Android™
The AM335x microrocessor contains these subsystems:
•
Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor.
•
POWERVR SGX™ Graphics Accelerator subsystem for 3D graphics acceleration to support display
and gaming effects.
•
Programmable Real-Time Unit Subsystem (PRUSS) enables the user to create a variety of digital
resources beyond native peripherals of the device. In addition, the PRUSS is separate from the ARM
core. This allows independent operation and clocking to give the device greater flexibility in complex
system solutions.
Note:
The subsystem available on this device is the next-generation PRUSS (PRUSSv2).
4
Device Summary
Copyright
©
2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s):
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
SPRS717B
–
OCTOBER 2011
–
REVISED JANUARY 2012
1.4
Functional Block Diagram
The AM335x microrocessor functional block diagram is shown in
Figure 1-1.
Graphics
PowerVR
SGX
3D GFX
Crypto
64K
shared
RAM
Display
24-bit LCD controller (WXGA)
Touch screen controller
PRU subsystem
12K RAM
PRU x2
w/SED
200 MHz
8K/8K w/SED Peripherals
ARM
Cortex-A8
275/500/600/720 MHz
32K/32K L1 w/SED
256K L2 w/ECC
176K ROM 64K RAM
L3/L4 interconnect
Serial
UART x6
SPI x2
I C x3
McASP x2
(4 channel)
CAN x2
(Ver. 2 A and B)
USB 2.0 HS
OTG + PHY x2
2
System
eDMA
Timers x8
WDT
RTC
eHRPWM x3
eQEP x3
PRCM
eCAP x3
ADC (8 channel)
12-bit SAR
JTAG/ETB
Crystal
Oscillator x2
Parallel
MMC/SD/
SDIO x3
Memory interface
mDDR(LPDDR) / DDR2 / DDR3
(16-bit, 200 / 266 / 303 MHz)
NAND/NOR (16-bit ECC)
EMAC (2-port) 10M/100M/1G
IEEE1588, and switch
(MII, RMII, RGMII)
Figure 1-1. AM335x Functional Block Diagram
Copyright
©
2011–2012, Texas Instruments Incorporated
Device Summary
5
Submit Documentation Feedback
Product Folder Link(s):
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352
PRODUCT PREVIEW
GPIO
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