Verilog Tutorial
By
Deepak Kumar Tala
http://www.asic−world.com
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DISCLAIMER
I don't makes any claims, promises or guarantees about the accuracy,
completeness, or adequacy of the contents of this tutorial and
expressly disclaims liability for errors and omissions in the contents of
this tutorial. No warranty of any kind, implied, expressed or statutory,
including but not limited to the warranties of non−infringement of third
party rights, title, merchantability, fitness for a particular purpose and
freedom from computer virus, is given with respect to the contents of
this tutorial or its hyperlinks to other Internet resources. Reference in
this tutorial to any specific commercial products, processes, or
services, or the use of any trade, firm or corporation name is for the
information, and does not constitute endorsement, recommendation, or
favoring by me. All the source code and Tutorials are to be used on
your own risk. All the ideas and views in this tutorial are my own and
are not by any means related to my employer.
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INTRODUCTION
CHAPTER 1
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Introduction
Verilog is a
HARDWARE DESCRIPTION LANGUAGE (HDL).
A hardware description Language
is a language used to describe a digital system, for example, a network switch, a microprocessor
or a memory or a simple flip−flop. This just means that, by using a HDL one can describe any
hardware (digital ) at any level.
1//
D flip−flop Code
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module
d_ff ( d, clk, q, q_bar);
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input
d ,clk;
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output
q, q_bar;
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wire
d ,clk;
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reg
q, q_bar;
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always
@
(
posedge
clk)
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begin
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q
<=
d;
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q_bar
<= !
d;
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end
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endmodule
One can describe a simple Flip flop as that in above figure as well as one can describe a
complicated designs having 1 million gates. Verilog is one of the HDL languages available in the
industry for designing the Hardware. Verilog allows us to design a Digital design at Behavior Level,
Register Transfer Level (RTL), Gate level and at switch level. Verilog allows hardware designers to
express their designs with behavioral constructs, deterring the details of implementation to a later
stage of design in the final design.
Many engineers who want to learn Verilog, most often ask this question, how much time it will take
to learn Verilog?, Well my answer to them is
"It may not take more then one week, if you
happen to know at least one programming language".
Design Styles
Verilog like any other hardware description language, permits the designers to design a design in
either Bottom−up or Top−down methodology.
Bottom−Up Design
The traditional method of electronic design is bottom−up. Each design is performed at the
gate−level using the standard gates ( Refer to the Digital Section for more details) With increasing
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INTRODUCTION
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complexity of new designs this approach is nearly impossible to maintain. New systems consist of
ASIC or microprocessors with a complexity of thousands of transistors. These traditional
bottom−up designs have to give way to new structural, hierarchical design methods. Without these
new design practices it would be impossible to handle the new complexity.
Top−Down Design
The desired design−style of all designers is the top−down design. A real top−down design allows
early testing, easy change of different technologies, a structured system design and offers many
other advantages. But it is very difficult to follow a pure top−down design. Due to this fact most
designs are mix of both the methods, implementing some key elements of both design styles.
Figure shows a Top−Down design approach.
Abstraction Levels of Verilog
Verilog supports a design at many different levels of abstraction. Three of them are very important:
•
Behavioral level
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INTRODUCTION
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