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HT1621
RAM Mapping 32´4 LCD Controller for I/O MCU
Technical Document
·
Tools Information
·
FAQs
·
Application Note
Features
·
Operating voltage: 2.4V~5.2V
·
Built-in 256kHz RC oscillator
·
External 32.768kHz crystal or 256kHz frequency
·
32´4 LCD driver
·
Built-in 32´4 bit display RAM
·
3-wire serial interface
·
Internal LCD driving frequency source
·
Software configuration feature
·
Data mode and command mode instructions
·
R/W address auto increment
·
Three data accessing modes
·
VLCD pin for adjusting LCD operating voltage
·
HT1621B: 48-pin SSOP/LQFP packages
source input
·
Selection of 1/2 or 1/3 bias, and selection of 1/2 or
1/3 or 1/4 duty LCD applications
·
Internal time base frequency sources
·
Two selectable buzzer frequencies (2kHz/4kHz)
·
Power down command reduces power consumption
·
Built-in time base generator and WDT
·
Time base or WDT overflow output
·
8 kinds of time base/WDT clock sources
HT1621D: 28-pin SKDIP package
HT1621G: Gold bumped chip
General Description
The HT1621 is a 128 pattern (32´4), memory mapping,
and multi-function LCD driver. The S/W configuration
feature of the HT1621 makes it suitable for multiple LCD
applications including LCD modules and display sub-
systems. Only three or four lines are required for the in-
terface between the host controller and the HT1621.
The HT1621 contains a power down command to re-
duce power consumption.
Selection Table
HT162X
COM
SEG
Built-in Osc.
Crystal Osc.
HT1620
4
32
¾
Ö
HT1621
4
32
Ö
Ö
HT1622
8
32
Ö
¾
HT16220
8
32
¾
Ö
HT1623
8
48
Ö
Ö
HT1625
8
64
Ö
Ö
HT1626
16
48
Ö
Ö
Rev. 1.70
1
June 29, 2005
元器件交易½www.cecb2b.com
HT1621
Block Diagram
O S C O
O S C I
C S
R D
W R
D A T A
V D D
V S S
B Z
B Z
T o n e F re q u e n c y
G e n e ra to r
C o n
a n
T im
C ir c
tro l
d
in g
u it
D is p la y R A M
C O M 0
L C D D r iv e r /
B ia s C ir c u it
C O M 3
S E G 0
S E G 3 1
V L C D
W a tc h d o g T im e r
a n d
T im e B a s e G e n e r a to r
IR Q
Note:
CS: Chip selection
BZ, BZ: Tone outputs
WR, RD, DATA: Serial interface
COM0~COM3, SEG0~SEG31: LCD outputs
IRQ: Time base or WDT overflow output
Pin Assignment
S E G 7
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
S E G 6
S E G 5
S E G 4
S E G 3
S E G 2
S E G 1
S E G 0
C S
R D
W R
D A T A
V S S
O S C O
O S C I
V L C D
V D D
IR Q
B Z
B Z
C O M 0
C O M 1
C O M 2
C O M 3
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
S E G 8
S E G 9
S E G 1 0
S E G 1 1
S E G 1 2
S E G 1 3
S E G 1 4
S E G 1 5
S E G 1 6
S E G 1 7
S E G 1 8
S E G 1 9
S E G 2 0
S E G 2 1
S E G 2 2
S E G 2 3
S E G 2 4
S E G 2 5
S E G 2 6
S E G 2 7
S E G 2 8
S E G 2 9
S E G 3 0
S E G 3 1
C S
R D
W R
D A T A
V S S
O S C O
O S C I
V L C D
V D D
IR Q
B Z
B Z
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
S E G 1
S E G 1
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
8
9
0
1
3
1
0
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
S E G 5
1
2
3
4
5
6
7
8
9
S E G 3
S E
S E
S E
S E
S E
S E
S E
S G
S E
S E
S E
S E
G 1
G 1
G 1
G 1
G 1
G 1
G 1
E 1
G 2
G 2
G 2
G 2
2
3
4
5
6
7
8
9
0
1
2
3
S E G 1
C S
R D
W R
D A T A
V S S
V L C D
V D D
IR Q
B Z
C O M 0
C O M 1
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 0
1 1
1 2
1 3
1 4
1 9
1 8
1 7
1 6
1 5
S E G 7
S E G 9
S E G 1 1
S E G 1 3
S E G 1 5
S E G 1 7
S E G 1 9
S E G 2 1
S E G 2 3
S E G 2 5
S E G 2 7
S E G 2 9
S E G 3 1
C O M 2
4
2
H T 1 6 2 1 B
4 8 L Q F P -A
5
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
C O M
C O M
C O M
C O M
6
7
H T 1 6 2 1 B
4 8 S S O P -A
H T 1 6 2 1 D
2 8 S K D IP -A
2 4
2 5
2 6
2 8
2 7
2 9
3 0
3 1
3
0
1
2
Rev. 1.70
2
June 29, 2005
元器件交易½www.cecb2b.com
HT1621
Pad Assignment
S E G 1 5
S E G 1 4
S E G 1 3
S E G 1 2
S E G 1 1
S E G 1 0
S E G 8
S E G 9
S E G 5
S E G 6
S E G 7
S E G 0
4 8
S E G 1
S E G 2
S E G 3
S E G 4
C S
1
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
R D
W R
D A T A
4
5
6
V S S
O S C O
3
2
3 2
3 1
(0 ,0 )
3 0
2 9
2 8
2 7
2 6
2 5
2 4
7
8
2 3
2 2
2 1
1 1
B Z
1 2
B Z
S E G 1 6
S E G 1 7
S E G 1 8
S E G 1 9
S E G 2 0
S E G 2 1
S E G 2 2
S E G 2 3
S E G 2 4
S E G 2 5
S E G 2 6
S E G 2 7
S E G 2 8
O S C I
V L C D
V D D
9
1 0
IR Q
1 3
C O M 0
1 4
C O M 1
1 5
C O M 2
1 6
C O M 3
1 7
S E G 3 1
1 8
S E G 3 0
1 9
S E G 2 9
2 0
Chip size: 127
´
131 (mil)
2
Bump height: 18mm
±
3mm
Min. Bump spacing: 72.36mm
Bump size: 96.042
´
96.042mm
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
Rev. 1.70
3
June 29, 2005
元器件交易½www.cecb2b.com
HT1621
Pad Coordinates
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
X
-55.04
-58.52
-58.52
-58.52
-58.52
-58.52
-58.52
-58.52
-58.52
-58.52
-44.07
-31.58
-20.70
-13.98
-7.05
-0.34
6.33
12.96
19.59
58.14
58.14
58.14
58.14
58.14
Y
59.46
22.18
15.56
5.36
-4.51
-11.14
-34.76
-41.90
-49.13
-59.08
-59.08
-59.08
-59.08
-59.08
-59.08
-59.08
-59.08
-59.08
-59.08
-58.44
-51.81
-45.18
-38.55
-31.92
Pad No.
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
X
58.14
58.14
58.14
58.14
58.14
58.14
58.14
58.14
55.55
48.92
42.29
35.66
29.03
22.40
15.77
9.14
2.42
-4.21
-10.84
-17.47
-24.10
-30.73
-38.17
-45.39
Y
-25.29
-18.66
-11.94
-5.31
1.32
7.95
14.58
21.21
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
Unit: mil
Pad Description
Pad No.
Pad Name
I/O
Function
Chip selection input with pull-high resistor
When the CS is logic high, the data and command read from or written to
the HT1621 are disabled. The serial interface circuit is also reset. But if CS
is at logic low level and is input to the CS pad, the data and command trans-
mission between the host controller and the HT1621 are all enabled.
READ clock input with pull-high resistor
Data in the RAM of the HT1621 are clocked out on the falling edge of the RD
signal. The clocked out data will appear on the DATA line. The host control-
ler can use the next rising edge to latch the clocked out data.
WRITE clock input with pull-high resistor
Data on the DATA line are latched into the HT1621 on the rising edge of the
WR signal.
Serial data input/output with pull-high resistor
Negative power supply, ground
The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to
generate a system clock. If the system clock comes from an external clock
source, the external clock source should be connected to the OSCI pad. But
if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads
can be left open.
LCD power input
Positive power supply
Time base or WDT overflow flag, NMOS open drain output
2kHz or 4kHz tone frequency output pair
LCD common outputs
LCD segment outputs
4
June 29, 2005
1
CS
I
2
RD
I
3
4
5
7
6
8
9
10
11, 12
13~16
48~17
Rev. 1.70
WR
DATA
VSS
OSCI
OSCO
VLCD
VDD
IRQ
BZ, BZ
COM0~COM3
SEG0~SEG31
I
I/O
¾
I
O
I
¾
O
O
O
O
元器件交易½www.cecb2b.com
HT1621
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V
to V
SS
+5.5V
Input Voltage..............................V
SS
-0.3V
to V
DD
+0.3V
Storage Temperature ............................-50
o
C to 125
o
C
Operating Temperature...........................-40
o
C to 85
o
C
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute
Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Symbol
V
DD
I
DD1
Parameter
Operating Voltage
Operating Current
5V
3V
I
DD2
Operating Current
5V
3V
I
DD3
Operating Current
5V
3V
I
STB
Standby Current
5V
3V
V
IL
Input Low Voltage
5V
3V
V
IH
Input High Voltage
5V
3V
I
OL1
DATA, BZ, BZ, IRQ
5V
3V
I
OH1
DATA, BZ, BZ
5V
3V
I
OL2
LCD Common Sink Current
5V
3V
I
OH2
LCD Common Source Current
5V
3V
I
OL3
LCD Segment Sink Current
5V
3V
I
OH3
LCD Segment Source Current
5V
3V
R
PH
Pull-high Resistor
5V
DATA, WR, CS, RD
30
60
100
V
OL
=0.3V
V
OL
=0.5V
V
OH
=2.7V
V
OH
=4.5V
V
OL
=0.3V
V
OL
=0.5V
V
OH
=2.7V
V
OH
=4.5V
V
OL
=0.3V
V
OL
=0.5V
V
OH
=2.7V
V
OH
=4.5V
DATA, WR, CS, RD
4.0
0.5
1.3
-0.4
-0.9
80
150
-80
-120
60
120
-40
-70
60
DATA, WR, CS, RD
0
2.4
No load, Power down mode
Test Conditions
V
DD
¾
3V
Conditions
¾
No load/LCD ON
On-chip RC oscillator
No load/LCD ON
Crystal oscillator
No load/LCD ON
External clock source
Min.
2.4
¾
¾
¾
¾
¾
¾
¾
¾
0
Typ.
¾
150
300
60
120
100
200
0.1
0.3
¾
¾
¾
¾
1.2
2.6
-0.8
-1.8
150
250
-120
-200
120
200
-70
-100
120
Max.
5.2
300
600
120
240
200
400
5
10
0.6
1.0
3.0
5.0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
200
Ta=25°C
Unit
V
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
kW
kW
Rev. 1.70
5
June 29, 2005
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