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FPGA关于EPCS的操作module

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标签: FPGA

FPGA

EPCS

EPCS

FPGA关于EPCS的操作module

Using the Serial FlashLoader with the
Quartus II Software
AN-370-3.2
Application Note
Introduction
Using the JTAG interface, the Altera
®
Serial FlashLoader (SFL) is the first in-system
programming solution for Altera serial configuration devices. The SFL solution is
available with the Quartus
®
II software version 4.1 SP1 and later. The SFL
megafunction is available with the Quartus II software version 6.0 and later.
Because serial configuration devices do not support the JTAG interface, the
conventional method to program them is via the active serial (AS) programming
interface. With the AS programming interface, the configuration data used to program
serial configuration devices is downloaded via programming hardware.
However, with the SFL you can program serial configuration devices in-system via
the JTAG interface. To do so, use an FPGA as a bridge between the JTAG interface and
the serial configuration device.
Table 1
lists the advantages and disadvantages of both methods.
Table 1. Advantages and Disadvantages
Method
Conventional: (AS
Programming)
Advantage
Disadvantage
Requires separate programming
interface to configure FPGAs and
program serial configuration
devices.
Slow, because the SFL solution
must configure the FPGA before
programming serial configuration
devices.
Simple and fast
SFL solution: (JTAG
Programming)
Able to configure the FPGA and
program serial configuration
devices using the same JTAG
interface
In version 9.0 and onwards of the Quartus II software, the enhanced mode of the SFL
solution is introduced. This allows faster EPCS programming time with the following
advantages:
Enhanced SFL solution correctly interprets extra padding bits introduced by third
programmer tool to ensure successful EPCS programming with SFL solution.
Enhanced SFL allows conversion from JTAG Indirect Configuration (.jic) to Jam
STAPL (.jam), JAM Byte-Code File (.jbc) or Serial Vector Format File (.svf) for
multiple devices in JTAG chain in which only one device uses the SFL solution.
Enhanced SFL allows conversion from
.jic
to
.jam, .jbc,
or
.svf
file for multiple
devices in JTAG chain in which two or more devices uses the SFL solution.
101 Innovation Drive
San Jose, CA 95134
www.altera.com
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS,
QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark
Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their
respective holders as described at
www.altera.com/common/legal.html.
Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use
of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are
advised to obtain the latest version of device specifications before relying on any published information and before placing orders
for products or services.
ISO
9001:2008
Registered
October 2012
Altera Corporation
Feedback Subscribe
Page 2
Introduction
1
For more information on how to enable the enhanced SFL mode, refer to
“Using the
SFL Megafunction in the Quartus II Software” on page 7
and
“Programming Serial
Configuration Devices with the Quartus II Programmer” on page 16.
The SFL supports FPGA families that configure using active serial configuration
scheme. With the SFL megafunction, you can instantiate SFL image into user design.
This feature allows you to perform SFL programming without resetting your design
in the FPGA. The SFL solution provides more hardware programming options. For
example, you can use the ByteBlaster
II or USB-Blaster
download cable,
production tester, and other tools that have a JTAG interface.
1
Whenever the term “serial configuration device or devices” is used in this document,
it refers to Altera EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128 devices.
This application note discusses the following topics:
“Programming Single and Multiple Serial Configuration Devices with the SFL
Solution” on page 3
“Using the SFL Megafunction in the Quartus II Software” on page 7
“Generating .jic and .jam Programming Files in the Quartus II Software” on
page 11
“Programming Serial Configuration Devices with the Quartus II Programmer” on
page 16
Using the Serial FlashLoader with the Quartus II Software
October 2012
Altera Corporation
Programming Single and Multiple Serial Configuration Devices with the SFL Solution
Page 3
Figure 1
shows both the conventional method of programming serial configuration
devices as well as the in-system programming method using the SFL solution.
Figure 1. Conventional Versus the In-System Programming Method
Conventional Method of Programming Serial Configuration Devices Via the AS Interface
ByteBlaster II Download Cable,
Microprocessor, etc.
Serial
Configuration
FPGA
AS Interface
Device
In-System Method of Programming Serial Configuration Devices Via the JTAG Interface
JTAG Chain
FPGA
SFL Image
to bridge the
JTAG interface
and ASMI
Serial
ASMI
AS Interface
Configuration
Device
JTAG
JTAG Interface
Programming Single and Multiple Serial Configuration Devices with the
SFL Solution
This section describes the three steps to program both single and multiple serial
configuration devices with the SFL solution.
1
To use the SFL solution, ensure that your board setup is in AS mode.
To program serial configuration devices using the SFL solution, perform the following
steps (refer to
Figure 2, Figure 3,
and
Figure 4):
1. To bridge the JTAG interface with the active serial memory interface (ASMI) block
in the FPGA device, configure the SFL image into the FPGA. The previous design
is replaced with the SFL image.
1
You can bypass this step if the SFL image exists in the FPGA.
2. Program the serial configuration device or devices via the SFL image’s JTAG-
ASMI bridge.
October 2012
Altera Corporation
Using the Serial FlashLoader with the Quartus II Software
Page 4
Programming Single and Multiple Serial Configuration Devices with the SFL Solution
3. Reconfigure the FPGA with the new configuration data. This replaces the SFL
image with the new design. To reconfigure the FPGA with the new configuration
data, pull the
nConfig
pin low and release it to start configuration.
Figure 2
shows the SFL programming flow.
Figure 2. Serial Flash Loader Programming Flow
Start
SFL image exists
in the FPGA?
Yes
No
Step 1:
Configure SFL image
into FPGA
Step 2:
Program EPCS through
SFL
Step 3:
Reconfigure FPGA with
new EPCS image
Using the Serial FlashLoader with the Quartus II Software
October 2012
Altera Corporation
Programming Single and Multiple Serial Configuration Devices with the SFL Solution
Page 5
Figure 3
shows the programming of a single serial configuration device with the SFL
solution.
Figure 3. Programming a Single Serial Configuration Device with the SFL Solution
FPGA
FPGA
with
User
Configuration
JTAG Chain
JTAG
FPGA
Configuration
Image
ASMI
Serial
Configuration
Device
FPGA
Step 1: Configure (1)
SFL
Image
Bridge
Serial
Configuration
Device
JTAG
JTAG Chain
ASMI
JTAG
SFL Image Bridge
AS
Serial
Configuration
Device
FPGA
Step 2: Program
JTAG
JTAG Chain
SFL
Image
Bridge
ASMI
Serial
Configuration
Device
FPGA
Step 3: Reconfigure
JTAG
JTAG Chain
New
FPGA
Configuration
Image
ASMI
Serial
Configuration
Device
Note to
Figure 3:
(1) You can bypass this step if the SFL image exists in the FPGA.
October 2012
Altera Corporation
Using the Serial FlashLoader with the Quartus II Software
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