a
FEATURES
125 MHz Clock Rate
On-Chip High Performance DAC and High Speed
Comparator
DAC SFDR > 50 dB @ 40 MHz A
OUT
32-Bit Frequency Tuning Word
Simplified Control Interface: Parallel Byte or Serial
Loading Format
Phase Modulation Capability
3.3 V or 5 V Single-Supply Operation
Low Power: 380 mW @ 125 MHz (5 V)
Low Power:
155 mW @ 110 MHz (3.3 V)
Power-Down Function
Ultrasmall 28-Lead SSOP Packaging
APPLICATIONS
Frequency/Phase—Agile Sine Wave Synthesis
Clock Recovery and Locking Circuitry for Digital
Communications
Digitally Controlled ADC Encode Generator
Agile Local Oscillator Applications
CMOS, 125 MHz
Complete DDS Synthesizer
AD9850
FUNCTIONAL BLOCK DIAGRAM
+V
S
REF
CLOCK IN
MASTER
RESET
GND
DAC R
SET
HIGH SPEED
DDS
32-BIT
TUNING
WORD
FREQUENCY
UPDATE/
DATA REGISTER
RESET
WORD LOAD
CLOCK
PHASE
AND
CONTROL
WORDS
10-BIT
DAC
ANALOG
OUT
ANALOG
IN
CLOCK OUT
CLOCK
OUT
FREQUENCY/PHASE
DATA REGISTER
DATA INPUT REGISTER
SERIAL
LOAD
1-BIT
40 LOADS
PARALLEL
LOAD
COMPARATOR
AD9850
8-BITS
5 LOADS
FREQUENCY, PHASE, AND CONTROL
DATA INPUT
GENERAL DESCRIPTION
The AD9850 is a highly integrated device that uses advanced
DDS technology coupled with an internal high speed, high
performance D/A converter and comparator to form a com-
plete, digitally programmable frequency synthesizer and
clock generator function. When referenced to an accurate
clock source, the AD9850 generates a spectrally pure, fre-
quency/phase programmable, analog output sine wave. This
sine wave can be used directly as a frequency source, or it can
be converted to a square wave for agile-clock generator applica-
tions. The AD9850’s innovative high speed DDS core provides
a 32-bit frequency tuning word, which results in an output
tuning resolution of 0.0291 Hz for a 125 MHz reference clock
input. The AD9850’s circuit architecture allows the generation
of output frequencies of up to one-half the reference clock
frequency (or 62.5 MHz), and the output frequency can be digi-
tally changed (asynchronously) at a rate of up to 23 million new
frequencies per second. The device also provides five bits of
digitally controlled phase modulation, which enables phase
shifting of its output in increments of 180°, 90°, 45°, 22.5°,
11.25°, and any combination thereof. The AD9850 also contains
a high speed comparator that can be configured to accept the
(externally) filtered output of the DAC to generate a low jitter
square wave output. This facilitates the device’s use as an
agile clock generator function.
The frequency tuning, control, and phase modulation words are
loaded into the AD9850 via a parallel byte or serial loading
format. The parallel load format consists of five iterative loads
of an 8-bit control word (byte). The first byte controls phase
modulation, power-down enable, and loading format; Bytes 2 to
5 comprise the 32-bit frequency tuning word. Serial loading is
accomplished via a 40-bit serial data stream on a single pin. The
AD9850 Complete DDS uses advanced CMOS technology to
provide this breakthrough level of functionality and performance
on just 155 mW of power dissipation (3.3 V supply).
The AD9850 is available in a space-saving 28-lead SSOP,
surface-mount package. It is specified to operate over the
extended industrial temperature range of –40°C to +85°C.
REV. H
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
AD9850–SPECIFICATIONS
(V = 5 V
S
5% except as noted, R
SET
= 3.9 k )
Test Level
Min
AD9850BRS
Typ
Max
Unit
Parameter
CLOCK INPUT CHARACTERISTICS
Frequency Range
5 V Supply
3.3 V Supply
Pulse Width High/Low
5 V Supply
3.3 V Supply
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
R
SET
= 3.9 kΩ
R
SET
= 1.95 kΩ
Gain Error
Gain Temperature Coefficient
Output Offset
Output Offset Temperature Coefficient
Differential Nonlinearity
Integral Nonlinearity
Output Slew Rate (50
Ω,
2 pF Load)
Output Impedance
Output Capacitance
Voltage Compliance
Spurious-Free Dynamic Range (SFDR)
Wideband (Nyquist Bandwidth)
1 MHz Analog Out
20 MHz Analog Out
40 MHz Analog Out
Narrowband
40.13579 MHz
±
50 kHz
40.13579 MHz
±
200 kHz
4.513579 MHz
±
50 kHz/20.5 MHz CLK
4.513579 MHz
±
200 kHz/20.5 MHz CLK
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance
Input Resistance
Input Current
Input Voltage Range
Comparator Offset*
COMPARATOR OUTPUT CHARACTERISTICS
Logic 1 Voltage 5 V Supply
Logic 1 Voltage 3.3 V Supply
Logic 0 Voltage
Propagation Delay, 5 V Supply (15 pF Load)
Propagation Delay, 3.3 V Supply (15 pF Load)
Rise/Fall Time, 5 V Supply (15 pF Load)
Rise/Fall Time, 3.3 V Supply (15 pF Load)
Output Jitter (p-p)
CLOCK OUTPUT CHARACTERISTICS
Clock Output Duty Cycle (Clk Gen. Config.)
Temp
Full
Full
25°C
25°C
IV
IV
IV
IV
1
1
3.2
4.1
125
110
MHz
MHz
ns
ns
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
V
V
I
V
I
V
I
I
V
IV
IV
I
10.24
20.48
–10
150
10
50
0.5
0.5
400
120
0.75
1
+10
50
8
1.5
mA
mA
% FS
ppm/°C
µA
nA/°C
LSB
LSB
V/µs
kΩ
pF
V
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
IV
IV
IV
IV
IV
IV
IV
V
IV
I
IV
VI
VI
VI
VI
V
V
V
V
V
IV
63
50
46
72
58
54
80
77
84
84
3
dBc
dBc
dBc
dBc
dBc
dBc
dBc
pF
kΩ
µA
V
mV
V
V
V
ns
ns
ns
ns
ps
%
500
–12
0
30
4.8
3.1
+12
V
DD
30
0.4
5.5
7
3
3.5
80
50
±
10
–2–
REV. H
AD9850
Parameter
CMOS LOGIC INPUTS (Including CLKIN)
Logic 1 Voltage, 5 V Supply
Logic 1 Voltage, 3.3 V Supply
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
POWER SUPPLY (A
OUT
= 1/3 CLKIN)
+V
S
Current @
62.5 MHz Clock, 3.3 V Supply
110 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 5 V Supply
125 MHz Clock, 5 V Supply
P
DISS
@
62.5 MHz Clock, 3.3 V Supply
110 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 5 V Supply
125 MHz Clock, 5 V Supply
P
DISS
Power-Down Mode
5 V Supply
3.3 V Supply
*Tested
by measuring output duty cycle variation.
Specifications subject to change without notice.
Temp
25°C
25°C
25°C
25°C
25°C
25°C
Test Level
I
IV
IV
I
I
V
AD9850BRS
Min
Typ
Max
3.5
2.4
0.8
12
12
3
Unit
V
V
V
µA
µA
pF
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
VI
VI
VI
VI
VI
VI
VI
VI
V
V
30
47
44
76
100
155
220
380
30
10
48
60
64
96
160
200
320
480
mA
mA
mA
mA
mW
mW
mW
mW
mW
mW
TIMING CHARACTERISTICS*
(V = 5 V
S
5% except as noted, R
SET
= 3.9 k )
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
AD9850BRS
Min
Typ Max
3.5
3.5
3.5
3.5
7.0
3.5
7.0
7.0
18
13
7.0
3.5
3.5
5
13
2
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
CLKIN Cycles
CLKIN Cycles
ns
ns
ns
CLKIN Cycles
CLKIN Cycles
CLKIN Cycles
µs
Parameter
t
DS
t
DH
t
WH
t
WL
t
WD
t
CD
t
FH
t
FL
t
CF
t
FD
t
RH
t
RL
t
RS
t
OL
t
RR
(Data Setup Time)
(Data Hold Time)
(W_CLK Minimum Pulse Width High)
(W_CLK Minimum Pulse Width Low)
(W_CLK Delay after FQ_UD)
(CLKIN Delay after FQ_UD)
(FQ_UD High)
(FQ_UD Low)
(Output Latency from FQ_UD)
Frequency Change
Phase Change
(FQ_UD Minimum Delay after W_CLK)
(CLKIN Delay after RESET Rising Edge)
(RESET Falling Edge after CLKIN)
(Minimum RESET Width)
(RESET Output Latency)
(Recovery from RESET)
Wake-Up Time from Power-Down Mode
*Control
functions are asynchronous with CLKIN.
Specifications subject to change without notice.
REV. H
–3–
AD9850
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION OF TEST LEVELS
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +V
S
Digital Output Continuous Current . . . . . . . . . . . . . . . 5 mA
DAC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300°C
SSOP
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . 82°C/W
*Absolute
maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.
Test Level
I
100% Production Tested.
III Sample Tested Only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI All devices are 100% production tested at 25°C. 100%
production tested at temperature extremes for military
temperature devices; guaranteed by design and
characterization testing for industrial devices.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9850 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Application Note:
Users are cautioned not to apply digital input signals prior to power-up of this
device. Doing so may r
esult in a latch-up condition.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
AD9850BRS
AD9850BRS-REEL
AD9850BRSZ*
AD9850BRSZ-REEL*
AD9850/CGPCB
AD9850/FSPCB
*Z
= Pb-free part.
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
Shrink Small Outline Package (SSOP)
Shrink Small Outline Package (SSOP)
Shrink Small Outline Package (SSOP)
Shrink Small Outline Package (SSOP)
Evaluation Board Clock Generator
Evaluation Board Frequency Synthesizer
Package Option
RS-28
RS-28
RS-28
RS-28
–4–
REV. H
AD9850
PIN CONFIGURATION
D3
D2
D1
LSB D0
DGND
DVDD
W CLK
FQ UD
CLKIN
1
2
3
4
5
6
7
28
D4
27
D5
26
D6
25
D7 MSB/SERIAL LOAD
24
DGND
23
DVDD
22
RESET
TOP VIEW
8
(Not to Scale) 21
IOUT
AD9850
9
20
IOUTB
19
AGND
18
AVDD
17
DACBL (NC)
16
VINP
15
VINN
AGND 10
AVDD 11
R
SET
12
QOUTB 13
QOUT 14
NC = NO CONNECT
Table I. PIN FUNCTION DESCRIPTIONS
Pin
No.
4 to 1,
28 to 25
5, 24
6, 23
7
8
9
10, 19
11, 18
12
Mnemonic
D0 to D7
DGND
DVDD
W_CLK
FQ_UD
CLKIN
AGND
AVDD
R
SET
Function
8-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and the 8-bit phase/
control word. D7 = MSB; D0 = LSB. D7 (Pin 25) also serves as the input pin for the 40-bit serial data-word.
Digital Ground. These are the ground return leads for the digital circuitry.
Supply Voltage Leads for Digital Circuitry.
Word Load Clock. This clock is used to load the parallel or serial frequency/phase/control words.
Frequency Update. On the rising edge of this clock, the DDS updates to the frequency (or phase)
loaded in the data input register; it then resets the pointer to Word 0.
Reference Clock Input. This may be a continuous CMOS-level pulse train or sine input biased at
1/2 V supply. The rising edge of this clock initiates operation.
Analog Ground. These leads are the ground return for the analog circuitry (DAC and comparator).
Supply Voltage for the Analog Circuitry (DAC and Comparator).
DAC’s External R
SET
Connection. This resistor value sets the DAC full-scale output current. For
normal applications (F
S
I
OUT
= 10 mA), the value for R
SET
is 3.9 kΩ connected to ground. The R
SET
/I
OUT
relationship is
I
OUT
= 32 (1.248 V/R
SET
).
Output Complement. This is the comparator’s complement output.
Output True. This is the comparator’s true output.
Inverting Voltage Input. This is the comparator’s negative input.
Noninverting Voltage Input. This is the comparator’s positive input.
13
14
15
16
17
20
21
22
QOUTB
QOUT
VINN
VINP
DACBL (NC) DAC Baseline. This is the DAC baseline voltage reference; this lead is internally bypassed and should
normally be considered a no connect for optimum performance.
IOUTB
IOUT
RESET
Complementary Analog Output of the DAC.
Analog Current Output of the DAC.
Reset. This is the master reset function; when set high, it clears all registers (except the input register), and
the DAC output goes to cosine 0 after additional clock cycles—see Figure 7.
REV. H
–5–
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