Fundamentals of Modern"
VLSI Devices
SECOND EDITION
YUAN TAUR
University of California,
san
Diego
TAK H. NING
IBM
T.
J.
Watson Research
Center,
New York
CAMBRIDGE
UNIVERSITY PRESS
CAMBRIDGE UNIVERSITY PRESS
Cambridge, New York, Melbourne, Madrid, Cape Town, Singapore, Sao Paulo, Delhi
Cambridge University Press
The Edinburgh Building, Cambridge CB2 8RU, UK
Published in the United States of America by Cambridge University
Press,
New York
www..cambridge.org
Information on this title: www.cambridge.orgl9780521832946
©
Cambridge University Press 1998, 2009
Contents
This publication is in copyright. Subject to statutory exception
and
to
the
provisions of relevant collective licensing agreements,
no reproduction of any part may take place without
the written pennission of Cambridge University Press.
First published 1998
Second edition 2009
Preface to the first edition
Preface to the second edition
Physical constants and unit conversions
List ofsymbols
page
xi
xiii
xv
XVI
1
Printed in the United Kingdom
at
the University Press, Cambridge
A catalog record for this publication
is
available from the British Library
Library ofCongress Cataloging in Publication data
Introduction
1.1 Evolution ofVLSI Device Technology
1.1.1 Historical Perspective
1.1.2 Recent Developments
1.2 Modern VLSI Devices
1.2.1 Modern CMOS Transistors
1.2.2 Modern Bipolar Transistors
1.3 Scope and Brief Description of the Book
Taur, Yuan, 1946
Fundamentals
of
modem VLSI devices / Yuan Taur, Tak H. Ning. 2nd ed.
p.
cm.
ISBN 978-0-521-83294-6
1. Metal oxide semiconductors, Complementary. 2. Bipolar transistors.
3. Integrated circuits Very large scale integration.
l.
Ning, Tak H., 1943- 11. Title.
TK7871.99.M44T38 2009
621.39'5-dc22
2009007334
ISBN 978-0-521-83294-6 hardback
Cambridge University Press
has
no responsibility for the persistence or
accuracy of URLs for external or third-party Internet websites referred to
in this publ.ication, and does not guarantee
thai
any content on such
websites is, or will remain, accurate or appropriate.
4
4
4
5
6
2
Basic Device PhysiCS
2.1 Electrons and Holes in Silicon
2.Ll Energy Bands in Silicon
2.1.2 n-Type and p-Type Silicon
2.1.3 Carrier Transport in Silicon
2.1.4 Basic Equations for Device Operation
2.2 p-n Junctions
2.2.1 Energy-Band Diagrams for a p-n Diode
2.2.2 Abrupt Junctions
2.2.3 The Diode Equation
2.2.4 Current-Voltage Characteristics
2.2.5 Time-Dependent and Switching Characteristics
2.2.6 Diffusion Capacitance
2.3 MOS Capacitors
23.1
Surface Potential: Accumulation, Depletion, and Inversion
2.3.2 Electrostatic Potential and Charge Distribution in Silicon
2.3.3 Capacitances in an MOS Structure
2.3.4 Polysilicon-Gate Work Function and Depletion Effects
2.3.5 MOS under Nonequilibrium and Gated Diodes
11
II
11
17
23
27
35
35
38
46
51
64
70
72
72
78
85
91
94
vi
Contents
Contents
vii
2.3.6
Charge in Silicon Dioxide and at the Silicon-Oxide Interface
2.3.7
Effect of Interface Traps and Oxide Charge on Device Characteristics
2.4
Metal-Silicon Contacts
2.4.1
Static Characteristics of a Schottky Barrier Diode
2.4.2
Current Transport in a Schottky Barrier Diode
2.4.3
Current-Voltage Characteristics of a Schottky Barrier Diode
2.4.4
Ohmic Contacts
2.5
High-Field Effects
2.5.1
Impact Ionization and Avalanche Breakdown
2.5.2
Band-to-Band Tunneling
2.5.3
Tunneling into and through Silicon Dioxide
2.5.4
Injection of Hot Carriers from Silicon into Silicon Dioxide
2.5.5
High-Field Effects in Gated Diodes
2.5.6
Dielectric Breakdown
Exercises
98
103
108
108
115
ll5
120
122
122
125
127
133
135
137
141
148
148
149
155
163
166
169
172
175
176
186
195
196
196
201
204
204
204
207
210
212
213
217
224
234
239
4.3
MOSFET Channel Length
4.3.1
Various Definitions ofChannel Length
4.3.2
Extraction ofthe Effective Channel Length
4.3.3
Physical Meaning of Effective Channel Length
4.3.4
Extraction of Channel Length by C-VMeasurements
Exercises
242
242
244
248
252
254
256
256
256
266
270
273
274
277
280
283
289
289
296
299
301
304
307
308
311
312
315
318
318
322
322
327
329
330
334
336
337
338
340
343
347
5
CMOS Perfonnance Factors
5.1
Basic CMOS Circuit Elements
5.1.1
CMOS Inverters
5.1.2
CMOS NAND and NOR Gates
5.1.3
Inverter and NAND Layouts
5.2
Parasitic Elements
5.2.1
Source-Drain Resistance
5.2.2
Parasitic Capacitances
5.2.3
Gate Resistance
5.2.4
Interconnect
R
and C
5.3
Sensitivity of CMOS Delay to Device Parameters
5.3.1
Propagation Delay and Delay Equation
5.3.2
Delay Sensitivity to Channel
Width,
Length, and Gate Oxide Thickness
5.3.3
Sensitivity of Delay to Power-Supply
and Threshold Voltage
5.3.4
Sensitivity of Delay to Parasitic Resistance and Capacitance
5.3.5
Delay of Two-Way NAND and Body Effect
5.4
Performance Factors of Advanced CMOS Devices
5.4.1
MOSFETs in RF Circuits
5.4.2
Effect of Transport Parameters on CMOS Performance
5.4.3
Low-Temperature CMOS
Exercises
3
MOSFET Devices
3.1 Long-Channel MOSFETs
3.1.1
Drain-Current Model
3.1.2
MOSFET
J-
V
Characteristics
3.1.3
Subthreshold Characteristics
3.1.4
Substrate Bias and Temperature Dependence of Threshold Voltage
3.1.5
MOSFET Channel Mobility
3.1.6
MOSFET Capacitances and Inversion-Layer Capacitance Effect
3.2
Short-Channel MOSFETs
3.2.1
Short-Channel Effect
3.2.2
Velocity Saturation and High-Field Transport
3.2.3
Channel Length Modulation
3.2.4
Source-Drain Series Resistance
3.2.5
MOSFET Degradation and Breakdown at High Fields
Exercises
I
6
Bipolar Devices
6.1
n-p-n Transistors
6.1.1
Basic Operation of a Bipolar Transistor
6.1.2
Modifying the Simple Diode Theory for Describing Bipolar Transistors
6.2
Ideal Current-Voltage Characteristics
6.2.1
Collector Current
6.2.2
Base Current
6.2.3
Current Gains
6.2.4
Ideal
Characteristics
6.3
Characteristics of a Typical n-p-n Transistor
6.3.1
Effect of Emitter and Base Series Resistances
6.3.2
Effect of Base-Collector Voltage on Collector Current
6.3.3
Collector Current Falloff at High Currents
6.3.4
Nonideal Base Current at Low Currents
4
CMOS Device Design
4.1
MOSFET Scaling
4.1.1
Constant-Field Scaling
4.1.2
Generalized Scaling
4.1.3
Nonscaling Effects
4.2
Threshold Voltage
4.2.1
Threshold-Voltage Requirement
4.2.2
Channel Profile Design
4.2.3
Nonuniform Doping
4.2.4
Quantum Effect on Threshold Voltage
4.2.5
Discrete Dopant Effects on Threshold Voltage
Contents
Contents
ix
6.4 Bipolar Device Models for Circuit and Time-Dependent Analyses
6.4.1 Basic dc Model
6.4.2 Basic ac Model
6.4.3 Small-Signal Equivalent-Circuit Model
6.4.4 Emitter Diffusion Capacitance
6.4.5 Charge-Control Analysis
6.5 Breakdown Voltages
Common-Base Current Gain in the Presence of Base-Collector
Junction Avalanche
6.5.2 Saturation Currents in a Transistor
6.5.3 Relation Between
BV
CEO
and
BV
CBO
Exercises
352
352
355
356
359
361
366
367
369
370
371
374
374
375
376
377
378
380
381
384
385
387
388
389
390
396
401
406
410
414
419
423
426
429
429
430
430
431
431
432
8
Bipolar Performance Factors
8.1 Figures of Merit of a Bipolar Transistor
8.1.1 Cutoff Frequency
8.1.2 Maximum Oscillation Frequency
8.1.3 Ring Oscillator and Gate Delay
8.2 Digital Bipolar Circuits
8.2.1 Delay Components of a Logic Gate
8.2.2 Device Structure and Layout for Digital Circuits
8.3 Bipolar Device Optimization for Digital Circuits
8.3.1 Design Points for a Digital Circuit
8.3.2 Device Optimization When There Is Significant
Base Widening
8.3.3 Device Optimization When There Is Negligible
Base Widening
8.3.4 Device Optimization for Small Power-Delay Product
8.3.5 Bipolar Device Optimization from Some Data Analyses
8.4 Bipolar Device Scaling for ECL Circuits
8.4.1 Device Scaling Rules
8.4.2 Limits in Bipolar Device Scaling for ECL Circuits
8.5 Bipolar Device Optimization and Scaling for RF and Analog Circuits
8.5.1 The Single-Transistor Amplifier
8.5.2 Optimizing the Individual Parameters
8.5.3 Technology for RF and Analog Bipolar Devices
8.5.4 Limits in Scaling Bipolar Transistors for RF and
Analog Applications
8.6 Comparing a SiGe-Base Bipolar Transistor with a GaAs HBT
Exercises
437
437
437
440
440
44]
442
445
447
447
448
449
453
455
457
458
460
463
463
464
467
468
469
472
476
477
478
486
487
495
496
499
500
501
507
511
514
516
7
Bipolar Device Design
of the Emitter Region
Diffused or Implanted-and-Diffused Emitter
Polysilicon Emitter
of the Base Region
Relationship between Base Sheet Resistivity and Collector
Current Density
7.2.2 Intrinsic-Base Dopant Distribution
7.2.3 Electric Field in the Quasineutral Intrinsic Base
7.2.4 Base Transit Time
7.3 Design of the Collector Region
7.3.1 Collector Design When There Is Negligible Base Widening
7.3.2 Collector Design When There Is Appreciable Base Widening
7.4 SiGe-Base Bipolar Transistors
7.4.1 Transistors Having a Simple Linearly Graded Base Bandgap
7.4.2 Base Current When Ge Is Present in the Emitter
7.4.3 Transistors Having a Trapezoidal Ge Distribution in the Base
7.4.4 Transistors Having a Constant Ge Distribution in the Base
7.4.5 Effect of Emitter Depth Variation on Device Characteristics
7.4.6 Some Optimal Ge Profiles
7.4.7 Base-Width Modulation by
V
BE
7.4.8 Reverse-Mode
I-V
Characteristics
7.4.9 Heterojunction Nature of a SiGe-Base Bipolar Transistor
7.5 Modem Binolar Transistor Structures
Isolation
7.5.2 Polysilicon Emitter
7.5.3 Self-Aligned Polysilicon Base Contact
7.5.4 Pedestal Collector
7.5.5 SiGe-Base
Exercises
7.1 Design
7.1.1
7.1.2
7.2 Design
7.2.1
9
Memory Devices
9.1 Static Random-Access Memory
9.1.1 CMOS SRAM Cell
9.1.2 Other Bistable MOSFET SRAM Cells
9.1.3 Bipolar SRAM Cell
9.2 Dynamic Random-Access Memory
9.2.1 Basic DRAM Cell and Its Operation
9.2.2 Device Design and Scaling Considerations for a DRAM Cell
9.3 Nonvolatile Memory
9.3.1 MOSFET Nonvolatile Memory Devices
9.3.2 Flash Memory Arrays
9.3.3 Floating-Gate Nonvolatile Memory Cells
9.3.4 Nonvolatile Memory Cells with Charge Stored in Insulator
Exercise
x
Contents
10
Silicon-on-Insulator Devices
517
517
518
Preface to the first edition
10.1
SOl CMOS
10.1.1 Partially Depleted SOl MOSFETs
10.1.2 Fully Depleted SOl MOSFETs
10.2
Thin-Silicon SOl Bipolar
10.2.1
Fully Depleted Collector Mode
10.2.2
Partially Depleted Collector Mode
10.2.3
Accumulation Collector Mode
10.2.4
Discussion
10.3
Double-Gate MOSFETs
10.3.1
An
Analytic Drain Current Model for Symmetric DG MOSFETs
10.3.2
The Scale Length of Double-Gate MOSFETs
10.3.3
Fabrication Requirements and Challenges ofDG MOSFETs
10.3.4
Multiple-Gate MOSFETs
Exercise
Appendix 1
Appendix 2
Appendix 3
Appendix 4
Appendix 5
Appendix 6
Appendix 7
Appendix 8
Appendix 9
Appendix 10
Appendix 11
Appendix 12
Appendix 13
Appendix 14
Appendix 15
Appendix 16
Appendix 17
Appendix 18
References
Index
CMOS Process Flow
Outline of a Process for Fabricating Modem n-p-n Bipolar
Transistors
Einstein Relations
Spatial Variation of Quasi-Fermi Potentials
Generation and Recombination Processes and Space-Charge
Region Current
Diffusion Capacitance of a p-n Diode
Image-Force-Induced Barrier Lowering
Electron-Initiated and Hole-Initiated Avalanche Breakdown
An Analytical Solution for the Short-Channel Effect in
Subthreshold
Generalized MOSFET Scale Length Model
Drain Current Model of a Ballistic MOSFET
Quantum-Mechanical Solution in Weak Inversion
Power Gain of a Two-Port Network
Frequencies of a MOSFET Transistor
DeterminatioIJ.,ofEmitter and Base Series Resistances
Intrinsic-Base Resistance
Energy-Band Diagram of a Si-SiGe n-p Diode
IT
and
Imax
of a Bipolar Transistor
520
523
524
526
527
527
529
529
533
534
536
537
538
542
543
546
553
562
569
573
575
582
588
594
598
601
605
610
614
617
623
644
It has been fifty years since the invention of the bipolar transistor, more than forty years
since the invention of the
integrated~circuit
(IC) technology, and more than thirty-five
years since the invention ofthe MOSFET. During this time, there has been a tremendous
and steady progress in the development of the IC technology with a
the IC industry. One distinct characteristic in the evolution ofthe IC tecnnOlogy
physical feature sizes of the transistors are reduced continually over time as the litho
graphy technologies used to define these features become available. For almost thirty
years now, the minimum lithography feature size used in IC manufacturing has been
reduced at a rate ofO.7x every three years. In 1997, the leading-edge IC products have a
minimum feature size of 0.25
1Jll1.
The basic operating principles oflarge and small transistors are the same. However, the
relative importance of the various device parameters and performance factors for tran
sistors ofthe
l-1Jll1
and smaller generations
is
quite different from those for transistors of
larger-dimension generations. For example, in the case of CMOS, the power-supp
voltage was lowered from the standard
5
V, starting with the
0.6-
to
0.8-1Jll1
generation.
Since then CMOS power supply voltage has been lowered in steps once every few years
as the device physical dimensions are reduced. At the same time, many physical
phenomena, such as short-channel effect and velocity saturation, which are negligible
in large-dimension MOSFETs, are becoming more and more important in determining
the behavior ofMOSFETs ofdeep-submicron dimensions. In the case of bipolar devices,
breakdown voltage and base-widening effects are limiting their performance, and power
dissipation is limiting their level of integration on a chip. Also, the advent of SiGe
base bipolar technology has extended the frequency capability of small-dimension
bipolar transistors into the range previously reserved for GaAs and other compound
semiconductor devices.
The purpose of this book
is
to bring together the device fundamentals that govern the
behavior of CMOS and bipolar transistors into a single text, with emphasis on those
parameters and eerformance factors that are particularly important for VLSI (very-large
scale-integration) devices of deep-submicron dimensions. The book starts with
a
com
prehensive review of the properties of the silicon material, and the basic physics ofp-n
junctions and MOS capacitors, as they relate to the fundamental principles of MOSFET
and bipolar transistors. From there, the basic operation of MOSFET and bipolar devices,
and their design and optimization for VLSI applications are developed. A great deal of
the volume is devoted to in-depth discussions of the intricate interdependence and subtle
tradeoffs of the various device parameters pertaining to circuit performance and manu
facturability. The effects which are particularly important in small-dimension devices,
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