Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
TMS320C6748
SPRS590F – JUNE 2009 – REVISED MARCH 2014
TMS320C6748™ Fixed- and Floating-Point DSP
1 TMS320C6748 Fixed- and Floating-Point DSP
1.1
1
Features
– 2 SP x DP
→
DP Every Three Clocks
– 2 DP x DP
→
DP Every Four Clocks
• Fixed-Point Multiply Supports Two 32 x 32-
Bit Multiplies, Four 16 x 16-Bit Multiplies, or
Eight 8 x 8-Bit Multiplies per Clock Cycle,
and Complex Multiples
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and
Program Redirection
Software Support
– TI DSP BIOS™
– Chip Support Library and DSP Library
128KB of RAM Shared Memory
1.8-V or 3.3-V LVCMOS I/Os (Except for USB and
DDR2 Interfaces)
Two External Memory Interfaces:
– EMIFA
• NOR (8- or 16-Bit-Wide Data)
• NAND (8- or 16-Bit-Wide Data)
• 16-Bit SDRAM with 128-MB Address Space
– DDR2/Mobile DDR Memory Controller with one
of the following:
• 16-Bit DDR2 SDRAM with 256-MB Address
Space
• 16-Bit mDDR SDRAM with 256-MB Address
Space
Three Configurable 16550-Type UART Modules:
– With Modem Control Signals
– 16-Byte FIFO
– 16x or 13x Oversampling Option
LCD Controller
Two Serial Peripheral Interfaces (SPIs) Each with
Multiple Chip Selects
Two Multimedia Card (MMC)/Secure Digital (SD)
Card Interfaces with Secure Data I/O (SDIO)
Interfaces
Two Master and Slave Inter-Integrated Circuits
( I
2
C Bus™)
• 375- and 456-MHz C674x Fixed- and Floating-
Point VLIW DSP
• C674x Instruction Set Features
– Superset of the C67x+ and C64x+ ISAs
– Up to 3648 MIPS and 2746 MFLOPS
– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
• C674x Two-Level Cache Memory Architecture
– 32KB of L1P Program RAM/Cache
– 32KB of L1D Data RAM/Cache
– 256KB of L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct Memory Access Controller 3
(EDMA3):
– 2 Channel Controllers
– 3 Transfer Controllers
– 64 Independent DMA Channels
– 16 Quick DMA Channels
– Programmable Transfer Burst Size
• TMS320C674x Floating-Point VLIW DSP Core
– Load-Store Architecture with Nonaligned
Support
– 64 General-Purpose Registers (32-Bit)
– Six ALU (32- and 40-Bit) Functional Units
• Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
• Supports up to Four SP Additions Per Clock,
Four DP Additions Every Two Clocks
• Supports up to Two Floating-Point (SP or
DP) Reciprocal Approximation (RCPxP) and
Square-Root Reciprocal Approximation
(RSQRxP) Operations Per Cycle
– Two Multiply Functional Units:
• Mixed-Precision IEEE Floating-Point Multiply
Supported up to:
– 2 SP x SP
→
SP Per Clock
– 2 SP x SP
→
DP Every Two Clocks
•
•
•
•
•
•
•
•
•
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320C6748
SPRS590F – JUNE 2009 – REVISED MARCH 2014
www.ti.com
• One Host-Port Interface (HPI) with 16-Bit-Wide
Muxed Address and Data Bus For High Bandwidth
• Programmable Real-Time Unit Subsystem
(PRUSS)
– Two Independent Programmable Real-Time Unit
(PRU) Cores
• 32-Bit Load-Store RISC Architecture
• 4KB of Instruction RAM Per Core
• 512 Bytes of Data RAM Per Core
• PRUSS can be Disabled via Software to
Save Power
• Register 30 of Each PRU is Exported From
the Subsystem in Addition to the Normal R31
Output of the PRU Cores.
– Standard Power-Management Mechanism
• Clock Gating
• Entire Subsystem Under a Single PSC Clock
Gating Domain
– Dedicated Interrupt Controller
– Dedicated Switched Central Resource
• USB 1.1 OHCI (Host) with Integrated PHY (USB1)
• USB 2.0 OTG Port with Integrated PHY (USB0)
– USB 2.0 High- and Full-Speed Client
– USB 2.0 High-, Full-, and Low-Speed Host
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt, or
ISOC) RX and TX
• One Multichannel Audio Serial Port (McASP):
– Two Clock Zones and 16 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable
– FIFO Buffers for Transmit and Receive
• Two Multichannel Buffered Serial Ports (McBSPs):
– Supports TDM, I2S, and Similar Formats
– AC97 Audio Codec Interface
– Telecom Interfaces (ST-Bus, H100)
– 128-Channel TDM
– FIFO Buffers for Transmit and Receive
• 10/100 Mbps Ethernet MAC (EMAC):
– IEEE 802.3 Compliant
– MII Media-Independent Interface
– RMII Reduced Media-Independent Interface
– Management Data I/O (MDIO) Module
• Video Port Interface (VPIF):
– Two 8-Bit SD (BT.656), Single 16-Bit or Single
Raw (8-, 10-, and 12-Bit) Video Capture
Channels
– Two 8-Bit SD (BT.656), Single 16-Bit Video
Display Channels
• Universal Parallel Port (uPP):
– High-Speed Parallel Interface to FPGAs and
Data Converters
– Data Width on Both Channels is 8- to 16-Bit
Inclusive
– Single-Data Rate or Dual-Data Rate Transfers
– Supports Multiple Interfaces with START,
ENABLE, and WAIT Controls
• Serial ATA (SATA) Controller:
– Supports SATA I (1.5 Gbps) and SATA II
(3.0 Gbps)
– Supports All SATA Power-Management
Features
– Hardware-Assisted Native Command Queueing
(NCQ) for up to 32 Entries
– Supports Port Multiplier and Command-Based
Switching
• Real-Time Clock (RTC) with 32-kHz Oscillator and
Separate Power Rail
• Three 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
• One 64-Bit General-Purpose or Watchdog Timer
(Configurable as Two 32-Bit General-Purpose
Timers)
• Two Enhanced High-Resolution Pulse Width
Modulators (eHRPWMs):
– Dedicated 16-Bit Time-Base Counter with
Period and Frequency Control
– 6 Single-Edge Outputs, 6 Dual-Edge Symmetric
Outputs, or 3 Dual-Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
• Three 32-Bit Enhanced Capture (eCAP) Modules:
– Configurable as 3 Capture Inputs or 3 Auxiliary
Pulse Width Modulator (APWM) Outputs
– Single-Shot Capture of up to Four Event Time-
Stamps
• Packages:
– 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)
[ZCE Suffix], 0.65-mm Ball Pitch
– 361-Ball Pb-Free PBGA [ZWT Suffix],
0.80-mm Ball Pitch
• Commercial, Extended, or Industrial Temperature
2
TMS320C6748 Fixed- and Floating-Point DSP
Submit Documentation Feedback
Product Folder Links:
TMS320C6748
Copyright © 2009–2014, Texas Instruments Incorporated
TMS320C6748
www.ti.com
SPRS590F – JUNE 2009 – REVISED MARCH 2014
1.2
•
•
Applications
•
Machine Vision (Low-End)
Currency Inspection
Biometric Identification
1.3
Description
The TMS320C6748 fixed- and floating-point DSP is a low-power applications processor based on a C674x
DSP core. This DSP provides significantly lower power than other members of the TMS320C6000™
platform of DSPs.
The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs)
to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor
performance through the maximum flexibility of a fully integrated, mixed processor solution.
The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a
32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache.
The level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program
and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.
Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM shared
memory is available for use by other hosts without affecting DSP performance.
For security-enabled devices, TI’s Basic Secure Boot lets users protect proprietary intellectual property
and prevents external entities from modifying user-developed algorithms. By starting from a hardware-
based “root-of-trust”, the secure boot flow ensures a known good starting point for code execution. By
default, the JTAG port is locked down to prevent emulation and debug attacks; however, the JTAG port
can be enabled during the secure boot process during application development. The boot modules are
encrypted while sitting in external nonvolatile memory, such as flash or EEPROM, and are decrypted and
authenticated when loaded during secure boot. Encryption and decryption protects customers’ IP and lets
them securely set up the system and begin device operation with known, trusted code.
Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot image validation. Basic Secure
Boot also uses AES-128 for boot image encryption. The secure boot flow employs a multilayer encryption
scheme which not only protects the boot process but offers the ability to securely upgrade boot and
application software code. A 128-bit device-specific cipher key, known only to the device and generated
using a NIST-800-22 certified random number generator, is used to protect customer encryption keys.
When an update is needed, the customer uses the encryption keys to create a new encrypted image.
Then the device can acquire the image through an external interface, such as Ethernet, and overwrite the
existing code. For more details on the supported security features or TI’s Basic Secure Boot, refer to the
TMS320C674x/OMAP-L1x Processor Security User’s Guide
(SPRUGQ9).
The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management
data input/output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two I
2
C Bus
interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two
multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with
multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as a
watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output
(GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes,
multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-
resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module
peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory
interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or
peripherals; and a higher speed DDR2/Mobile DDR controller.
The EMAC provides an efficient interface between the device and a network. The EMAC supports both
10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an
MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.
Copyright © 2009–2014, Texas Instruments Incorporated
TMS320C6748 Fixed- and Floating-Point DSP
Submit Documentation Feedback
Product Folder Links:
TMS320C6748
3
TMS320C6748
SPRS590F – JUNE 2009 – REVISED MARCH 2014
www.ti.com
The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller
supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps).
The uPP provides a high-speed interface to many types of data converters, FPGAs, or other parallel
devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-
data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to
provide control for a variety of data converters.
A video port interface (VPIF) is included providing a flexible video I/O port.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections in this document and
the associated peripheral reference guides.
The device has a complete set of development tools for the DSP. These tools include C compilers, a DSP
assembly optimizer to simplify programming and scheduling, and a Windows
®
debugger interface for
visibility into source code execution.
Device Information
PART NUMBER
TMS320C6748ZCE
TMS320C6748ZWT
PACKAGE
NFBGA (361)
NFBGA (361)
BODY SIZE
13,00 mm x 13,00 mm
16,00 mm x 16,00 mm
4
TMS320C6748 Fixed- and Floating-Point DSP
Submit Documentation Feedback
Product Folder Links:
TMS320C6748
Copyright © 2009–2014, Texas Instruments Incorporated
TMS320C6748
www.ti.com
SPRS590F – JUNE 2009 – REVISED MARCH 2014
1.4
Functional Block Diagram
Figure 1-1
shows the functional block diagram of the device.
JTAG Interface
System Control
Input
Clock(s)
PLL/Clock
Generator
w/OSC
General-
Purpose
Timer (x3)
RTC/
32-kHz
OSC
C674x™
DSP CPU
Memory
Protection
AET
32KB
L1 Pgm
32KB
L1 RAM
DSP Subsystem
Power/Sleep
Controller
Pin
Multiplexing
256KB L2 RAM
BOOT ROM
Switched Central Resource (SCR)
Peripherals
DMA
Audio Ports
Serial Interfaces
Display
Parallel Port
Internal Memory
Control Timers
EDMA3
(x2)
McASP
w/FIFO
McBSP
(x2)
I
2
C
(x2)
SPI
(x2)
UART
(x3)
LCD
Ctlr
uPP
128KB
RAM
ePWM
(x2)
eCAP
(x3)
Customizable Interface
Connectivity
Video
External Memory Interfaces
PRU Subsystem
USB2.0
OTG Ctlr
PHY
USB1.1
OHCI Ctlr
PHY
EMAC
10/100 MDIO
(MII/RMII)
HPI
MMC/SD
(8b)
(x2)
SATA
VPIF
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
DDR2/MDDR
Controller
Figure 1-1. Functional Block Diagram
Copyright © 2009–2014, Texas Instruments Incorporated
TMS320C6748 Fixed- and Floating-Point DSP
Submit Documentation Feedback
Product Folder Links:
TMS320C6748
5
京公网安备 11010802033920号
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved
评论