LDC1000
www.ti.com.cn
ZHCSBM0 – SEPTEMBER 2013
LDC1000
电感数字½换器
查询样品
:
LDC1000
1
特性
无磁½操½
亚微米高精度
可调感测范围（通过线圈设计实现）
更½的系统成本
远程传感器放½（从恶劣环境中将
LDC
去耦合）
高耐久性（借助于遥控操½）
对于环境干扰的不敏感性（诸如污垢、灰尘、水、
油）
电源电压，模拟：
4.75V
至
5.25V
电源电压，
IO：1.8V
至
5.25V
：
电源电流（无
LC
谐振回路）：
1.7mA
Rp
分辨率：
16
½
L
分辨率：
24
½
LC
频率范围：
5kHz
至
5MHz
说明
电感感测是一种遥控的、短程感测技术，此项技术½够
在灰尘、污垢、油和½湿环境中实现导½目标的½成
本、高分辨率感测，这½得它在恶劣环境中非常可靠。
通过½用可在印刷电路板
(PCB)
上被创建为一个感测
元件的线圈，LDC1000 可实现超½成本系统解决方
案。
电感感测技术可实现线性/角½½、½移、运动、压
缩、振动、金属成分以及市面上包括½½、消费类、计
算机、工业用、医疗用和通信应用在内的很多其它应用
的高精度测量。 电感感测以½于其它竞争对手解决方
案的成本提供更½的性½和可靠性。
LDC1000
是世界上第一个电感数字½换器，从而在一
个½功耗、小封装尺寸解决方案内提供电感感测的优
势。 此产品采用一个小外½尺寸无引线
(SON)-16
封
装，并且提供了几种运行模式。 一个串行外设接口
(SPI)
简化了到微控制器
(MCU)
的连接。
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应用范围
•
•
•
•
•
•
•
•
•
电传线控系统
½½计数
流量计
按钮开关
笔记本电脑
游戏控制器
多功½打印机
数码照相机
医疗设备
TYPICAL APPLICATION
Figure 1. Axial Distance Sensing
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet:
SNOSCX2
LDC1000
ZHCSBM0 – SEPTEMBER 2013
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
BLOCK DIAGRAM
CFA
CFB
L
INA
LDC
C
INB
Threshold
Detector
Proximity Data
Register
Frequency
Counter Data
Register
4-Wire
Serial
Interface
SCLK
SDI
SDO
CS
INTB
R
s
Power
Frequency Counter
VDD
GND
VIO
DGND
CLDO
TBCLK/XIN
XOUT
Figure 2. LDC1000 Block Diagram
TYPICAL APPLICATION SCHEMATIC
5V
V
IO
LDO
5V
V
IO
V
IO
MOSI
MISO
SCLK
MCU
GPIO
INT/GPIO
Timer/Aux CLK
DGND
DGND
CLDO
CSB
INTB
TBCLK
SDI
SDO
SCLK
LDC1000
V
DD
INA
INB
Sensor
CFA
CFB
GND
DAP
DGND
DGND
AGND
Figure 3. Typical Application Schematic
2
Copyright © 2013, Texas Instruments Incorporated
LDC1000
www.ti.com.cn
ZHCSBM0 – SEPTEMBER 2013
CONNECTION DIAGRAM
SCLK
CSB
SDI
VIO
SDO
DGND
CFB
CFA
1
2
3
4
5
6
7
8
DAP
(GND)
16
15
14
13
12
11
10
9
INTB
XOUT
TBCLK/XIN
CLDO
VDD
GND
INB
INA
Figure 4. LDC1000 Pin Diagram
SON-16
Table 1. Pin Description
(1)
PIN NAME
SCLK
CSB
SDI
VIO
SDO
DGND
CFB
CFA
INA
INB
GND
VDD
CLDO
TBCLK/XIN
XOUT
INTB
DAP
(1)
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
PIN
TYPE
DO
DI
DI
P
DO
P
A
A
A
A
P
P
A
DI/A
A
DO
P
FUNCTION
SPI clock input. SCLK is used to clock-out/clock-in the data from/into the chip
SPI CSB. Multiple devices can be connected on the same SPI bus and CSB can be used to select the
device to be communicated with
SPI Slave Data In (Master Out Slave In). This should be connected to the Master Out Slave In of the
master
Digital IO Supply
SPI Slave Data Out (Master In Slave Out).It is high-z when CSB is high
Digital ground
LDC filter capacitor
LDC filter capacitor
External LC Tank. Connected to external LC tank
External LC Tank. Connected to external LC tank
Analog ground
Analog supply
LDO bypass capacitor. A 56nF capacitor should be connected from this pin to GND
External time-base clock/XTAL. Either an external clock or crystal can be connected
XTAL. Crystal out. Recommended to connect 8Mhz crystal between XIN and XOUT with 20pF cap
from each pin to ground. Should be floating when external clock is used
Configurable interrupt. This pin can be configured to behave in 3 different ways by programing the INT
pin mode register. Either threshold detect, wakeup, or DRDYB
Connect to GND
DO: Digital Output, DI: Digital Input, P: Power, A: Analog
Copyright © 2013, Texas Instruments Incorporated
3
LDC1000
ZHCSBM0 – SEPTEMBER 2013
www.ti.com.cn
ABSOLUTE MAXIMUM RATINGS
(1)
ESD Tolerance
(2)
Analog Supply Voltage (VDD – GND)
IO Supply Voltage (VIO – GND)
Voltage on any Analog Pin
Voltage on any Digital Pin
Input Current on INA and INB
Junction Temperature, TJ
(3)
Storage Temperature Range , T
stg
(1)
(2)
(3)
Human Body Model
Charge Device Model
1kV
250V
6V
6V
-0.3V to VDD + 0.3V
-0.3V to VIO + 0.3V
8mA
+150°C
-65°C to +150°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability. Operating Ratings are conditions under which operation of the device is intended to be
functional. For ensured specifications and test conditions, see the Electrical Characteristics.
The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
The maximum power dissipation is a function of TJ(MAX),
θJA,
and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/
θJA.
All numbers apply for packages soldered directly onto a PC
board. The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
(1)
MIN
Analog Supply Voltage (VDD – GND)
IO Supply Voltage (VIO – GND)
VDD-VIO
Operating Temperature, TA
Package Thermal Resistance
(1)
(2)
(2)
MAX
5.25
5.25
125
28
UNIT
V
V
V
°C
°C/W
4.75
1.8
>=0
-40
SON (θ
JA
)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability. Operating Ratings are conditions under which operation of the device is intended to be
functional. For ensured specifications and test conditions, see the Electrical Characteristics.
The maximum power dissipation is a function of TJ(MAX),
θJA,
and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/
θJA.
All numbers apply for packages soldered directly onto a PC
board. The package thermal impedance is calculated in accordance with JESD 51-7.
4
Copyright © 2013, Texas Instruments Incorporated
LDC1000
www.ti.com.cn
ZHCSBM0 – SEPTEMBER 2013
ELECTRICAL CHARACTERISTICS
(1)
Unless otherwise specified, all limits ensured for TA = TJ = 25°C, VDD = 5.0V, VIO = 3.3V
(2)
SYMBOL
POWER
V
DD
V
IO
I
DD
I
VIO
I
DD_LP
t
START
Start-Up Time
LDC
f
sensor_MIN
f
sensor_MAX
A
sensor_MIN
A
sensor_MAX
t
REC
Recovery time
R
p_MIN
R
p_MAX
R
p_RES
t
S_MIN
Minimum Sensor Rp
Range
Maximum Sensor Rp
Range
Rp Measurement
Resolution
Minimum Response
Time
Maximum Response
Time
Minimum
programmable settling
time of digital filter
Maximum
programmable settling
time of digital filter
Minimum sensor
frequency
Maximum sensor
frequency
Minimum sensor
amplitude
Maximum sensor
amplitude
Oscillation start-up time
after RP under-range
condition
5
5
1
4
10
798
3.93M
16
192×1/f
sensor
kHz
MHz
VPP
VPP
1/f
sensor
Ω
Ω
Bits
s
Analog Supply Voltage
IO Supply Voltage
Supply Current, VDD
IO Supply Current
Low-Power Mode
Supply Current
VIO≤VDD
Does not include LC
tank current
Static current
With out LC Tank
From POR to ready-to-
convert. Crystal not
used for frequency
counter
250
4.75
1.8
5
3.3
1.7
5.25
5.25
2.3
14
V
V
mA
uA
uA
PARAMETER
CONDITIONS/
COMMENTS
MIN
(3)
TYP
(4)
MAX
(3)
UNITS
2
ms
t
S_MAX
6144×1/f
sensor
s
EXTERNAL CLOCK/CRYSTAL FOR FREQUENCY COUNTER
Crystal
External Clock
Frequency
Startup time
Frequency
Clock Input High
Voltage
(1)
8
30
8
V
IO
MHz
ms
MHz
V
(2)
(3)
(4)
Electrical Characteristics Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
The maximum power dissipation is a function of TJ(MAX),
θJA,
and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/
θJA.
All numbers apply for packages soldered directly onto a PC
board. The package thermal impedance is calculated in accordance with JESD 51-7.
Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through
correlations using statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
Copyright © 2013, Texas Instruments Incorporated
5
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