In most LCA designs, performance cannot be estimatedwith any accuracy until after implementation. This isbecause the performance is affected by routing delays;and, prior to implementation, these are not known. However,in adders and counters using the XC4000E dedicatedcarry logic, delay estimation is possible.The carry path in an adder uses dedicated interconnectsbetween CLBs. These interconnects introduce a fixeddelay, even when the carry passes from one CLB column tothe next at the top or bottom of the array. This permits therouting delay to be incorporated into the CLB specificationspublished in the data book. Consequently, the propagationdelay through an adder can be calculated directly from thedata book specifications.
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