TMS320C28x
CPU and Instruction Set
Reference Guide
Literature Number: SPRU430E
August 2001 − Revised January 2009
Preface
Read This First
About This Manual
This manual describes the central processing unit (CPU) and the assembly language instructions of the
TMS320C28x 32-bit fixed-point CPU. It also describes emulation features available on these devices.
A summary of the chapters and appendixes follows:
Chapter 1
Architectural Overview
This chapter introduces the C2800 CPU that is at the heart of each
TMS320C28x device. The chapter includes a memory map and a high-level
description of the memory interface that connects the core with memory and
peripheral devices.
Central Processing Unit
This chapter describes the architecture, registers, and primary functions of
the CPU. The chapter includes detailed descriptions of the flag and control
bits in the most important CPU registers, status registers ST0 and ST1.
Interrupts and Reset
This chapter describes the interrupts and how they are handled by the CPU.
The chapter also explains the effects of a reset on the CPU and includes dis-
cussion of the automatic context save performed by the CPU prior to servic-
ing an interrupt.
Pipeline
This chapter describes the phases and operation of the instruction pipeline.
The chapter is primarily for readers interested in increasing the efficiency of
their programs by preventing pipeline delays.
Addressing Modes
This chapter explains the modes by which the assembly language instruc-
tions accept data and access register and memory locations. The chapter in-
cludes a description of how addressing-mode information is encoded in op-
codes.
Assembly Language Instructions
This chapter provides summaries of the instruction set and detailed descrip-
tions (including examples) for the instructions. The chapter includes an ex-
planation of how 32-bit accesses are aligned to even addresses.
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
Read This First
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About This Manual
Chapter 7
Emulation Features
This chapter describes the TMS320C28x emulation features that can be
used with only a JTAG port and two additional emulation pins.
Register Quick Reference
This appendix is a concise central resource for information about the status
and control registers of the CPU. The chapter includes figures that summa-
rize the bit fields of the registers.
C2xLP and C28x Architectural Differences
This appendix describes the differences in the architecture of the C2xLP and
the C28x.
Migration From C2xLP
This appendix explains how to migrate code from the C2xLP to the C28x.
C2xLP Instruction Set Compatibility
This appendix describes the instruction set compatibility with the C2xLP.
Migration From C27x to C28x
This appendix explains how to migrate code from the C27x to the C28x.
Glossary
This appendix explains abbreviations, acronyms, and special terminology
used throughout this document.
Appendix A
Appendix B
Appendix C
Appendix D
Appendix E
Appendix G
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About This Manual / Notational Conventions
Notational Conventions
This document uses the following conventions:
-
The device number TMS320C28x is very often abbreviated as ’28x.
-
Program examples are shown in a
special typeface.
Here is a sam-
ple line of program code:
PUSH IER
-
Portions of an instruction syntax that are in
bold
should be entered as
shown; portions of a syntax that are in
italics
are variables indicating in-
formation that should be entered. Here is an example of an instruction
syntax:
MOV ARx, *−SP[6bit]
MOV is the instruction mnemonic. This instruction has two operands, indi-
cated by
ARx
and
*−SP[6bit].
Where the variable
x
appears, you type a
value from 0 to 5; where the
6bit
appears, you type a 6-bit constant. The
rest of the instruction, including the square brackets, must be entered as
shown.
-
When braces or brackets enclose an operand, as in {operand}, the oper-
and is optional. If you use an optional operand, you specify the information
within the braces; you do not enter the braces themselves. In the following
syntax, the operand <<
shift
is optional:
MOV ACC, *−SP[6bit]
{<<
shift
}
MOV ACC, *−SP{6bit}
{<<
shift
}
For example, you could use either of the following instructions:
MOV ACC, *−SP[5]
MOV ACC, *−SP[5]<< 4
-
In most cases, hexadecimal numbers are shown with a subscript of 16. For
example, the hexadecimal number 40 would be shown as 40
16
. An excep-
tion to this rule is a hexadecimal number in a code example; these hexade-
cimal numbers have the suffix h. For example, the number 40 in the follow-
ing code is a hexadecimal 40.
MOVB AR0,#40h
Read This First
v
Notational Conventions
Similarly, binary numbers usually are shown with a subscript of 2. For ex-
ample, the binary number 4 would be shown as 0100
2
. Binary numbers in
example code have the suffix b. For example, the following code uses a
binary 4.
MOVB AR0,#0100b
-
Bus signals and bits are sometimes represented with the following nota-
tions:
Notation
Bus(n:m)
Description
Signals n through m of bus
Example
PRDB(31:0) represents the 32
signals of the program-read data
bus (PRDB).
T(3:0) represents the 4 least sig-
nificant bits of the T register.
IER(4) represents bit 4 of the in-
terrupt enable register (IER).
Register(n:m)
Bits n through m of register
Register(n)
Bit n of register
-
Concatenated values are represented with the following notation:
Notation
x:y
Description
x concatenated with y
Example
AR1:AR0 is the concatenation of
the 16-bit registers AR1 and
AR0. AR0 is the low word. AR1
is the high word.
-
If a signal is from an active-low pin, the name of the signal is qualified with
an overbar (for example, INT1). If a signal is from an active-high pin or from
hardware inside the the device (in which case, the polarity is irrelevant),
the name of the signal is left unqualified (for example, DLOGINT).
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