PCI Express
™
Base Specification
Revision 1.1
March 28, 2005
Revision
1.0
1.0a
1.1
Revision History
Initial release.
Incorporated Errata C1-C66 and E1-E4.17.
Incorporated approved Errata and ECNs.
DATE
07/22/02
04/15/03
03/28/05
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contained herein and assumes no responsibility for any errors that may appear in this document, nor
does PCI-SIG make a commitment to update the information contained herein.
Contact the PCI-SIG office to obtain the latest revision of this specification.
Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be
forwarded to:
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www.pcisig.com
E-mail:
administration@pcisig.com
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techsupp@pcisig.com
DISCLAIMER
This PCI Express Base Specification is provided “as is” with no warranties whatsoever,
including any warranty of merchantability, noninfringement, fitness for any particular
purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of
information in this specification. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted herein.
PCI Express and PCI-SIG are trademarks of PCI-SIG.
All other product names are trademarks, registered trademarks, or servicemarks of their respective
owners.
Copyright © 2002-2005 PCI-SIG
2
PCI EXPRESS BASE SPECIFICATION, REV 1.1
Contents
OBJECTIVE OF THE SPECIFICATION.................................................................................... 19
DOCUMENT ORGANIZATION ................................................................................................ 19
DOCUMENTATION CONVENTIONS ...................................................................................... 20
TERMS AND ACRONYMS........................................................................................................ 21
REFERENCE DOCUMENTS...................................................................................................... 26
1.
INTRODUCTION ................................................................................................................ 27
1.1. A T
HIRD
G
ENERATION
I/O I
NTERCONNECT
................................................................... 27
1.2.
PCI E
XPRESS
L
INK
........................................................................................................ 29
1.3.
PCI E
XPRESS
F
ABRIC
T
OPOLOGY
.................................................................................. 30
1.3.1.
Root Complex........................................................................................................ 30
1.3.2.
Endpoints .............................................................................................................. 31
1.3.3.
Switch.................................................................................................................... 34
1.3.4.
Root Complex Event Collector.............................................................................. 35
1.3.5.
PCI Express-PCI Bridge....................................................................................... 35
1.4.
PCI E
XPRESS
F
ABRIC
T
OPOLOGY
C
ONFIGURATION
....................................................... 35
1.5.
PCI E
XPRESS
L
AYERING
O
VERVIEW
............................................................................. 36
1.5.1.
Transaction Layer................................................................................................. 37
1.5.2.
Data Link Layer .................................................................................................... 37
1.5.3.
Physical Layer ...................................................................................................... 38
1.5.4.
Layer Functions and Services............................................................................... 38
2.
TRANSACTION LAYER SPECIFICATION ..................................................................... 43
2.1.
T
RANSACTION
L
AYER
O
VERVIEW
.................................................................................. 43
2.1.1.
Address Spaces, Transaction Types, and Usage................................................... 44
2.1.2.
Packet Format Overview ...................................................................................... 46
2.2.
T
RANSACTION
L
AYER
P
ROTOCOL
- P
ACKET
D
EFINITION
............................................... 47
2.2.1.
Common Packet Header Fields ............................................................................ 47
2.2.2.
TLPs with Data Payloads - Rules ......................................................................... 50
2.2.3.
TLP Digest Rules .................................................................................................. 52
2.2.4.
Routing and Addressing Rules .............................................................................. 52
2.2.5.
First/Last DW Byte Enables Rules........................................................................ 55
2.2.6.
Transaction Descriptor......................................................................................... 57
2.2.7.
Memory, I/O, and Configuration Request Rules................................................... 62
2.2.8.
Message Request Rules ......................................................................................... 65
2.2.9.
Completion Rules .................................................................................................. 76
3
PCI EXPRESS BASE SPECIFICATION, REV 1.1
2.3. H
ANDLING OF
R
ECEIVED
TLP
S
...................................................................................... 78
2.3.1.
Request Handling Rules........................................................................................ 81
2.3.2.
Completion Handling Rules.................................................................................. 93
2.4.
T
RANSACTION
O
RDERING
.............................................................................................. 95
2.4.1.
Transaction Ordering Rules ................................................................................. 95
2.4.2.
Update Ordering and Granularity Observed by a Read Transaction .................. 99
2.4.3.
Update Ordering and Granularity Provided by a Write Transaction ................ 100
2.5.
V
IRTUAL
C
HANNEL
(VC) M
ECHANISM
....................................................................... 100
2.5.1.
Virtual Channel Identification (VC ID) .............................................................. 103
2.5.2.
TC to VC Mapping .............................................................................................. 103
2.5.3.
VC and TC Rules................................................................................................. 105
2.6.
O
RDERING AND
R
ECEIVE
B
UFFER
F
LOW
C
ONTROL
..................................................... 106
2.6.1.
Flow Control Rules ............................................................................................. 107
2.7.
D
ATA
I
NTEGRITY
......................................................................................................... 116
2.7.1.
ECRC Rules ........................................................................................................ 117
2.7.2.
Error Forwarding ............................................................................................... 121
2.8.
C
OMPLETION
T
IMEOUT
M
ECHANISM
........................................................................... 123
2.9.
L
INK
S
TATUS
D
EPENDENCIES
...................................................................................... 124
2.9.1.
Transaction Layer Behavior in DL_Down Status............................................... 124
2.9.2.
Transaction Layer Behavior in DL_Up Status ................................................... 125
3.
DATA LINK LAYER SPECIFICATION .......................................................................... 127
3.1.
D
ATA
L
INK
L
AYER
O
VERVIEW
.................................................................................... 127
3.2.
D
ATA
L
INK
C
ONTROL AND
M
ANAGEMENT
S
TATE
M
ACHINE
...................................... 129
3.2.1.
Data Link Control and Management State Machine Rules ................................ 130
3.3.
F
LOW
C
ONTROL
I
NITIALIZATION
P
ROTOCOL
............................................................... 132
3.3.1.
Flow Control Initialization State Machine Rules ............................................... 132
3.4.
D
ATA
L
INK
L
AYER
P
ACKETS
(DLLP
S
)........................................................................ 136
3.4.1.
Data Link Layer Packet Rules ............................................................................ 136
3.5.
D
ATA
I
NTEGRITY
......................................................................................................... 141
3.5.1.
Introduction......................................................................................................... 141
3.5.2.
LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 141
3.5.3.
LCRC and Sequence Number (TLP Receiver) .................................................... 153
4.
PHYSICAL LAYER SPECIFICATION ............................................................................ 161
4.1.
I
NTRODUCTION
............................................................................................................ 161
4.2.
L
OGICAL
S
UB
-
BLOCK
................................................................................................... 161
4.2.1.
Symbol Encoding ................................................................................................ 162
4.2.2.
Framing and Application of Symbols to Lanes................................................... 165
4.2.3.
Data Scrambling ................................................................................................. 168
4.2.4.
Link Initialization and Training.......................................................................... 169
4.2.5.
Link Training and Status State Machine (LTSSM) Descriptions........................ 177
4.2.6.
Link Training and Status State Rules.................................................................. 180
4.2.7.
Clock Tolerance Compensation.......................................................................... 210
4.2.8.
Compliance Pattern ............................................................................................ 211
4
PCI EXPRESS BASE SPECIFICATION, REV 1.1
4.3. E
LECTRICAL
S
UB
-
BLOCK
............................................................................................. 213
4.3.1.
Electrical Sub-Block Requirements .................................................................... 213
4.3.2.
Electrical Signal Specifications .......................................................................... 217
4.3.3.
Differential Transmitter (TX) Output Specifications .......................................... 222
4.3.4.
Differential Receiver (RX) Input Specifications ................................................. 228
5.
POWER MANAGEMENT................................................................................................. 231
5.1.
O
VERVIEW
................................................................................................................... 231
5.1.1.
Statement of Requirements.................................................................................. 232
5.2.
L
INK
S
TATE
P
OWER
M
ANAGEMENT
............................................................................. 232
5.3.
PCI-PM S
OFTWARE
C
OMPATIBLE
M
ECHANISMS
........................................................ 237
5.3.1.
Device Power Management States (D-States) of a Function.............................. 237
5.3.2.
PM Software Control of the Link Power Management State.............................. 241
5.3.3.
Power Management Event Mechanisms ............................................................. 246
5.4.
N
ATIVE
PCI E
XPRESS
P
OWER
M
ANAGEMENT
M
ECHANISMS
....................................... 253
5.4.1.
Active State Power Management (ASPM) .......................................................... 253
5.5.
A
UXILIARY
P
OWER
S
UPPORT
....................................................................................... 269
5.5.1.
Auxiliary Power Enabling................................................................................... 269
5.6.
P
OWER
M
ANAGEMENT
S
YSTEM
M
ESSAGES AND
DLLP
S
............................................. 270
6.
SYSTEM ARCHITECTURE ............................................................................................. 273
6.1.
I
NTERRUPT AND
PME S
UPPORT
................................................................................... 273
6.1.1.
Rationale for PCI Express Interrupt Model........................................................ 273
6.1.2.
PCI Compatible INTx Emulation........................................................................ 274
6.1.3.
INTx Emulation Software Model ........................................................................ 274
6.1.4.
Message Signaled Interrupt (MSI/MSI-X) Support............................................. 274
6.1.5.
PME Support....................................................................................................... 276
6.1.6.
Native PME Software Model .............................................................................. 276
6.1.7.
Legacy PME Software Model ............................................................................. 277
6.1.8.
Operating System Power Management Notification........................................... 277
6.1.9.
PME Routing Between PCI Express and PCI Hierarchies ................................ 277
6.2.
E
RROR
S
IGNALING AND
L
OGGING
................................................................................ 278
6.2.1.
Scope ................................................................................................................... 278
6.2.2.
Error Classification ............................................................................................ 278
6.2.3.
Error Signaling ................................................................................................... 280
6.2.4.
Error Logging ..................................................................................................... 287
6.2.5.
Sequence of Device Error Signaling and Logging Operations .......................... 290
6.2.6.
Error Message Controls ..................................................................................... 292
6.2.7.
Error Listing and Rules ...................................................................................... 293
6.2.8.
Virtual PCI Bridge Error Handling.................................................................... 297
6.3.
V
IRTUAL
C
HANNEL
S
UPPORT
...................................................................................... 298
6.3.1.
Introduction and Scope ....................................................................................... 298
6.3.2.
TC/VC Mapping and Example Usage................................................................. 299
6.3.3.
VC Arbitration .................................................................................................... 301
6.3.4.
Isochronous Support ........................................................................................... 309
6.4.
D
EVICE
S
YNCHRONIZATION
......................................................................................... 312
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