飞思卡尔的 YL-KL26Z - 原理图。
文档内容节选
5 4 3 2 1 U2 1 7 8 VDD1 VDDA VSSA GND 11 VBAT 5V C7 22UF GND TP3 TP4 6 5 4 3 10 9 19 VREGIN VOUT33 USB0DM USB0DP EXTAL32 XTAL32 RESET USB 5V 33V P5VSDA C1 10uF GND 3 U1 LM111733 VIN D N G 2 4 OUT TAB 1 GND 3V3 SS14 SMA D1 C2 10uF GND 3V3 C3 10uF GND P5VSDA 5V TP1 68 J1 CONN USB MINIB 1 2 3 4 5 V 5 D D D I G 7 9 GND TP2 GND D2 SS14 SMA C4 10uF GND R2 R3 33R 33R 5V R6 47K R7 10K GND PUPD LOGIC SERIAL INTERFACE IS ALWAYS RESET WHEN USB PORT IS DISCONNECTED SDARST TP5 TARGET RESET AND BOOTLOADE......
猜您喜欢
京公网安备 11010802033920号
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved
评论