Lattice Diamond Tutorial
May 2014
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Copyright © 2014 Lattice Semiconductor Corporation.
This document may not, in whole or part, be copied, photocopied, reproduced,
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Trademarks
Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L
(stylized), L (design), Lattice (design), LSC, CleanClock, Custom Mobile Device,
DiePlus, E
2
CMOS, ECP5, Extreme Performance, FlashBAK, FlexiClock, flexiFLASH,
flexiMAC, flexiPCS, FreedomChip, GAL, GDX, Generic Array Logic, HDL Explorer,
iCE Dice, iCE40, iCE65, iCEblink, iCEcable, iCEchip, iCEcube, iCEcube2, iCEman,
iCEprog, iCEsab, iCEsocket, IPexpress, ISP, ispATE, ispClock, ispDOWNLOAD,
ispGAL, ispGDS, ispGDX, ispGDX2, ispGDXV, ispGENERATOR, ispJTAG, ispLEVER,
ispLeverCORE, ispLSI, ispMACH, ispPAC, ispTRACY, ispTURBO, ispVIRTUAL
MACHINE, ispVM, ispXP, ispXPGA, ispXPLD, Lattice Diamond, LatticeCORE,
LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2, LatticeECP2M, LatticeECP3,
LatticeECP4, LatticeMico, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM,
LatticeXP, LatticeXP2, MACH, MachXO, MachXO2, MachXO3, MACO, mobileFPGA,
ORCA, PAC, PAC-Designer, PAL, Performance Analyst, Platform Manager,
ProcessorPM, PURESPEED, Reveal, SensorExtender, SiliconBlue, Silicon Forest,
Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST, SuperWIDE,
sysCLOCK, sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The Simple Machine for
Complex Design, TraceID, TransFR, UltraMOS, and specific product designations are
either registered trademarks or trademarks of Lattice Semiconductor Corporation or its
subsidiaries in the United States and/or other countries. ISP, Bringing the Best
Together, and More of the Best are service marks of Lattice Semiconductor
Corporation.
Other product names used in this publication are for identification purposes only and
may be trademarks of their respective companies.
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NO WARRANTIES: THE INFORMATION PROVIDED IN THIS DOCUMENT IS “AS IS”
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Lattice Diamond Tutorial
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Press the two keys at the same time.
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Lattice Diamond Tutorial
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Lattice Diamond Tutorial
Contents
Lattice Diamond Tutorial
Learning Objectives
System Requirements
1
1
2
2
Time to Complete This Tutorial
2
3
3
Accessing Online Help and Diamond User Guide
About the Tutorial Design
About the Tutorial Data Flow
Task 1: Create a New Lattice Diamond Project
Task 2: Create an IPexpress Module
Task 4: Inspect Strategy Settings
Task 5: Examine Resources
17
20
Task 6: Run Synthesis Process
15
11
13
Task 3: Verify Functionality with Simulation
5
Task 7: Set Timing and Location Assignments
Task 8: Running Place and Route
26
Task 9: Examine Post Place and Route Results
21
29
33
36
Task 10: Adjust Static Timing Constraints and Review Results
Task 11: Comparing Multiple Place and Route Runs
Task 12: Analyze Power Consumption
Task 13: Run Export Utility Programs
37
39
39
41
Task 14: Download a Bitstream to an FPGA
Task 15: Convert a File Using Deployment Tool
Task 16: Use Reveal Inserter to Add On-chip Debug Logic
45
Setting Up the Trigger Units
47
Setting Up the Trigger Expressions
48
Inserting the Debug Logic
49
Generating a Bitstream and Programming the FPGA
51
Lattice Diamond Tutorial
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