Zilog
P R E L I M I N A R Y
Z80182/Z8L182
Z
ILOG
I
NTELLIGENT
P
ERIPHERAL
P
RELIMINARY
P
RODUCT
S
PECIFICATION
Z80182/Z8L182
Z
ILOG
I
NTELLIGENT
P
ERIPHERAL
C
ONTROLLER
(ZIP
™
)
FEATURES
s
Z8S180 MPU
- Code Compatible with Zilog Z80
®
/Z180
™
CPU
- Extended Instructions
- Operating Frequency: 33 MHz/5V or 20 MHz/3.3V
- Two DMA Channels
- On-Chip Wait State Generators
- Two UART Channels
- Two 16-Bit Timer Counters
- On-Chip Interrupt Controller
- On-Chip Clock Oscillator/Generator
- Clocked Serial I/O Port
- Fully Static
- Low EMI Option
s
s
s
Two ESCC
™
Channels with 32-Bit CRC
Three 8-Bit Parallel I/O Ports
16550 Compatible MIMIC Interface for
Direct Connection to PC, XT, AT Bus
100-Pin Package Styles (QFP, VQFP)
(0.8 Micron CMOS 5120 Technology)
Individual WSG for RAMCS and ROMCS
s
s
GENERAL DESCRIPTION
The Z80182/Z8L182 is a smart peripheral controller IC for
modem (in particular V. Fast applications), fax, voice
messaging and other communications applications. It
uses the Z80180 microprocessor (Z8S180 MPU core)
linked with two channels of the industry standard Z85230
ESCC (Enhanced Serial Communications Controller), 24
bits of parallel I/O, and a 16550 MIMIC for direct connection
to the IBM PC, XT, AT bus.
The Z80182/Z8L182 allows complete flexibility for both
internal PC and external applications. Also current PC
modem software compatibility can be maintained with the
Z80182/Z8L182 ability to mimic the 16550 UART chip. The
Z80180 acts as an interface between the ESCC
™
and
16550 MIMIC interface when used in internal applications,
and between the two ESCC channels in the external
applications. This interface allows data compression and
error correction on outgoing and incoming data. In external
applications, three 8-bit parallel ports are available for
driving LEDs or other devices. Figure 1 shows the Z80182/
Z8L182 block diagram, while the pin assignments for the
QFP and the VQFP packages are shown in Figures 2 and
3, respectively. All references in this document to the
Z80182, or Z182 refer to both the Z80182 and Z8L182.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Power
Ground
Circuit
V
CC
GND
Device
V
DD
V
SS
DS971820600
PS009801-0301
3-1
Zilog
P R E L I M I N A R Y
Z80182/Z8L182
Z
ILOG
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P
ERIPHERAL
GENERAL DESCRIPTION
(Continued)
D7-D0
Control
A19-A0
Bus
Transceiver
GLU
Logic
EV1
EV2
Tx Data
Rx Data
ESCC
Control
85230
ESCC
Channel
A
Z8S180
(Static Z80180)
MPU Core
/TRxCB
85230
ESCC
Channel
B
/ROMCS
/RAMCS
Address
Decode
16550
MIMIC
Interface
8-Bit Parallel
Port C
8-Bit Parallel
Port B
8-Bit Parallel
Port A
MUX
85230
ESCC Ch. A
or Port C
Z180 Signals
or Port B
MUX
MUX
16550 MIMIC
or ESCC
85230 Ch. B
and Port A
Note:
Conventional use of the term "MPU side" refers to all interface through the Z180 MPU
core and "PC side" refers to all interface through the16550 MIMIC interface.
Figure 1. Z80182/Z8L182 Functional Block Diagram
3-2
PS009801-0301
DS971820600
Zilog
P R E L I M I N A R Y
/MRD//MREQ
/IORQ
/RFSH
/HALT
/SYNCB//HCS
Z80182/Z8L182
Z
ILOG
I
NTELLIGENT
P
ERIPHERAL
/BUSREQ
/BUSACK
/WAIT
EXTAL
/NMI
/RESET
/INT0
/INT1/PC6
/INT2/PC7
ST
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
VSS
A13
A14
A15
A16
A17
A18/TOUT
VDD
A19
D0
D1
D2
D3
1
100
/M1
E
/RTXCB/HA2
RXDB/HA1
80
XTAL
VSS
PHI
/RD
/WR
95
90
85
/TRXCB/HA0
TXDB//HDDIS
/CTSB//HWR
5
75
/DCDB//HRD
TXDA
/TRXCA
RXDA
VDD
IEI
/IOCS/IEO
VSS
/RTXCA
/SYNCA/PC4
/DCDA/PC0
/CTSA/PC1
/MWR/PC2//RTSA
/DTR//REQA/PC3
/W//REQA/PC5
PA7/HD7
PA6/HD6
PA5/HD5
PA4/HD4
PA3/HD3
PA2/HD2
10
70
15
Z80182/Z8L182
100-Pin QFP
65
20
60
25
55
PA1/HD1
PA0/HD0
EV2
EV1
/ROMCS
/RAMCS
30
35
40
45
50
Figure 2. Z80182/Z8L182 100-Pin QFP Pin Configuration
DS971820600
CKA1//TEND0
TXS//DTR//REQB//HINTR
CKS//W//REQB//HTXRDY
/DREQ1
VDD
/TEND1//RTSB//HRXRDY
/RTS0/PB0
/CTS0/PB1
/DCD0/PB2
TXA0/PB3
RXA0/PB4
TXA1/PB5
RXA1/PB6
RXS//CTS1/PB7
CKA0//DREQ0
VSS
D4
D5
D6
D7
PS009801-0301
3-3
Zilog
P R E L I M I N A R Y
Z80182/Z8L182
Z
ILOG
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NTELLIGENT
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GENERAL DESCRIPTION
(Continued)
/CTSB//HWR
/DCDB//HRD
TXDA
/TRXCA
RXDA
VDD
IEI
/IOCS/IEO
VSS
/RTXCA
/SYNCA/PC4
/DCDA/PC0
/CTSA/PC1
/MWR/PC2//RTSA
/DTR//REQA/PC3
/W//REQA/PC5
PA7/HD7
PA6/HD6
PA5/HD5
PA4/HD4
PA3/HD3
55
75
TXDB//HDDIS
/TRXCB/HA0
RXDB/HA1
/RTXCB/HA2
/SYNCB//HCS
/HALT
/RFSH
/IORQ
/MRD//MREQ
E
/M1
/WR
/RD
PHI
VSS
XTAL
EXTAL
/WAIT
/BUSACK
/BUSREQ
/RESET
/NMI
/INT0
/INT1/PC6
/INT2/PC7
76
70
65
60
PA2/HD2
PA1/HD1
PA0/HD0
EV2
51
50
EV1
/ROMCS
/RAMCS
/TEND1//RTSB//HRXRDY
VDD
/DREQ1
CKS//W//REQB//HTXRDY
TXS//DTR//REQB/HINTR
CKA1//TEND0
VSS
CKA0//DREQ0
RXS//CTS1/PB7
RXA1/PB6
TXA1/PB5
RXA0/PB4
TXA0/PB3
/DCD0/PB2
/CTS0/PB1
/RTS0/PB0
D7
D6
D5
D4
D3
D2
45
40
35
30
26
25
80
85
Z80182/Z8L182
100-Pin VQFP
90
95
100
1
5
10
15
20
ST
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Figure 3. Z80182/Z8L182 100-Pin VQFP Pin Configuration
3-4
PS009801-0301
VSS
A13
A14
A15
A16
A17
A18/TOUT
VDD
A19
D0
D1
DS971820600
Zilog
Z180 CPU SIGNALS
P R E L I M I N A R Y
Z80182/Z8L182
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P
ERIPHERAL
A19-A0.
Address Bus (input/output, active High, tri-state).
A19-A0 form a 20-bit address bus. The Address Bus
provides the address for memory data bus exchanges up
to 1 Mbyte, and I/O data bus exchanges up to 64K. The
address bus enters a high impedance state during reset
and external bus acknowledge cycles, as well as during
SLEEP and HALT states. This bus is an input when the
external bus master is accessing the on-chip peripherals.
Address line A18 is multiplexed with the output of PRT
channel 1 (T
OUT
, selected as address output on reset).
D7-D0.
Data Bus (bi-directional, active High, tri-state).
D7-
D0 constitute an 8-bit bi-directional data bus, used for the
transfer of information to and from I/O and memory devices.
The data bus enters the high impedance state during reset
and external bus acknowledge cycles, as well as during
SLEEP and HALT states.
/RD.
Read (input/output, active Low, tri-state).
/RD indicates
that the CPU wants to read data from memory or an I/O
device. The addressed I/O or memory device should use
this signal to gate data onto the CPU data bus.
/WR.
Write (input/output, active Low, tri-state).
/WR indicates
that the CPU data bus holds valid data to be stored at the
addressed I/O or memory location.
/IORQ.
I/O Request (input/output, active Low, tri-state).
/IORQ indicates that the address bus contains a valid I/O
address for an I/O read or I/O write operation. /IORQ is also
generated, along with /M1, during the acknowledgment of
the /INT0 input signal to indicate that an interrupt response
vector can be placed onto the data bus. This signal is
analogous to the IOE signal of the Z64180.
/M1.
Machine Cycle 1 (input/output, active Low).
Together
with /MREQ, /M1 indicates that the current cycle is the
opcode fetch cycle of an instruction execution; unless
/M1E bit in the OMCR is cleared to 0. Together with /IORQ,
/M1 indicates that the current cycle is for an interrupt
acknowledge. It is also used with the /HALT and ST signals
to decode status of the CPU machine cycle. This signal is
analogous to the /LIR signal of the Z64180.
/MREQ.
Memory Request (input/output, active Low, tri-
state).
/MREQ indicates that the address bus holds a valid
address for a memory read or memory write operation.
This signal is analogous to the /ME signal of the Z64180.
/MREQ is multiplexed with /MRD on the /MRD//MREQ pin.
The /MRD//MREQ pin is an input during adapter modes; is
tri-state during bus acknowledge if the /MREQ function is
selected; and is inactive High if /MRD function is selected.
/MRD.
Memory Read (input/output, active Low, tri-state).
/MRD is active when both the internal /MREQ and /RD are
active. /MRD is multiplexed with /MREQ on the /MRD
//MREQ pin. The /MRD//MREQ pin is an input during
adapter modes; is tri-state during bus acknowledge if
/MREQ function is selected; and is inactive High if /MRD
function is selected. The default function on power up is
/MRD and may be changed by programming bit 3 of the
Interrupt Edge/Pin MUX Register (xxDFH).
/MWR.
Memory Write (input/output, active Low, tri-state).
/MWR is active when both the internal /MREQ and /WR are
active. This /RTSA or PC2 combination is pin multiplexed
with /MWR on the /MWR/PC2//RTSA pin. The default function
of this pin on power up is /MWR, which may be changed by
programming bit 3 in the Interrupt Edge/Pin MUX Register
(xxDFH).
/WAIT.
(input/output active Low).
/WAIT indicates to the
MPU that the addressed memory or I/O devices are not
ready for a data transfer. This input is used to induce
additional clock cycles into the current machine cycle. The
/WAIT input is sampled on the falling edge of T2 (and
subsequent wait states). If the input is sampled Low, then
additional wait states are inserted until the /WAIT input is
sampled High, at which time execution will continue.
/HALT.
Halt/Sleep Status (input/output, active Low).
This
output is asserted after the CPU has executed either the
HALT or SLEEP instruction, and is waiting for either non-
maskable or maskable interrupts before operation can
resume. It is also used with the /M1 and ST signals to
decode status of the CPU machine cycle. On exit of HALT/
SLEEP mode, the first instruction fetch can be delayed by
16 clock cycles after the /HALT pin goes High, if HALT 16
feature is selected.
/BUSACK.
Bus Acknowledge (input/output, active Low).
/BUSACK indicates to the requesting device, the MPU
address and data bus, and some control signals, have
entered their high impedance state.
/BUSREQ.
Bus Request (input, active Low).
This input is
used by external devices (such as DMA controllers) to
request access to the system bus. This request has a
higher priority than /NMI and is always recognized at the
end of the current machine cycle. This signal will stop the
CPU from executing further instructions and places the
address/data buses and other control signals, into the high
impedance state.
DS971820600
PS009801-0301
3-5
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