THE I
2
C-BUS SPECIFICATION
VERSION 2.1
JANUARY 2000
Philips Semiconductors
The I
2
C-bus specification
CONTENTS
1
1.1
1.2
1.3
1.4
2
2.1
2.2
3
4
5
6
6.1
6.2
7
7.1
7.2
8
8.1
8.2
8.3
9
10
10.1
10.1.1
10.1.2
10.1.3
11
12
13
13.1
13.2
13.3
PREFACE . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Version 1.0 - 1992. . . . . . . . . . . . . . . . . . . .
Version 2.0 - 198. . . . . . . . . . . . . . . . . . . . .
Version 2.1 - 1999. . . . . . . . . . . . . . . . . . . .
Purchase of Philips I
2
C-bus components . .
3
3
3
3
13.5.1
13.5.2
13.5.3
14
14.1
14.2
14.3
15
13.4
13.5
Hs-mode devices at lower speed modes . . 24
Mixed speed modes on one serial bus
system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
F/S-mode transfer in a mixed-speed bus
system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Hs-mode transfer in a mixed-speed bus
system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Timing requirements for the bridge in a
mixed-speed bus system . . . . . . . . . . . . . . 27
10-BIT ADDRESSING . . . . . . . . . . . . . . . . 27
Definition of bits in the first two bytes. . . . . 27
Formats with 10-bit addresses. . . . . . . . . . 27
General call address and start byte with
10-bit addressing . . . . . . . . . . . . . . . . . . . . 30
ELECTRICAL SPECIFICATIONS
AND TIMING FOR I/O STAGES
AND BUS LINES . . . . . . . . . . . . . . . . . . . . 30
Standard- and Fast-mode devices. . . . . . . 30
Hs-mode devices . . . . . . . . . . . . . . . . . . . . 34
ELECTRICAL CONNECTIONS OF
I
2
C-BUS DEVICES TO THE BUS LINES . 37
Maximum and minimum values of
resistors R
p
and R
s
for Standard-mode
I
2
C-bus devices . . . . . . . . . . . . . . . . . . . . . 39
APPLICATION INFORMATION . . . . . . . . . 41
Slope-controlled output stages of
Fast-mode I
2
C-bus devices . . . . . . . . . . . . 41
Switched pull-up circuit for Fast-mode
I
2
C-bus devices . . . . . . . . . . . . . . . . . . . . . 41
Wiring pattern of the bus lines . . . . . . . . . . 42
Maximum and minimum values of
resistors R
p
and R
s
for Fast-mode
I
2
C-bus devices . . . . . . . . . . . . . . . . . . . . . 42
Maximum and minimum values of
resistors R
p
and R
s
for Hs-mode
I
2
C-bus devices . . . . . . . . . . . . . . . . . . . . . 42
BI-DIRECTIONAL LEVEL SHIFTER
FOR F/S-MODE I
2
C-BUS SYSTEMS . . . . 42
Connecting devices with different
logic levels . . . . . . . . . . . . . . . . . . . . . . . . . 43
Operation of the level shifter . . . . . . . . . . . 44
DEVELOPMENT TOOLS AVAILABLE
FROM PHILIPS . . . . . . . . . . . . . . . . . . . . . 45
SUPPORT LITERATURE . . . . . . . . . . . . . 46
THE I
2
C-BUS BENEFITS DESIGNERS
AND MANUFACTURERS . . . . . . . . . . . . . . .4
Designer benefits . . . . . . . . . . . . . . . . . . . . 4
Manufacturer benefits . . . . . . . . . . . . . . . . . 6
INTRODUCTION TO THE I
2
C-BUS
SPECIFICATION . . . . . . . . . . . . . . . . . . . . .6
THE I
2
C-BUS CONCEPT . . . . . . . . . . . . . . .6
GENERAL CHARACTERISTICS . . . . . . . . .8
BIT TRANSFER . . . . . . . . . . . . . . . . . . . . . .8
Data validity . . . . . . . . . . . . . . . . . . . . . . . . 8
START and STOP conditions . . . . . . . . . . . 9
TRANSFERRING DATA . . . . . . . . . . . . . . .10
Byte format . . . . . . . . . . . . . . . . . . . . . . . . 10
Acknowledge. . . . . . . . . . . . . . . . . . . . . . . 10
ARBITRATION AND CLOCK
GENERATION . . . . . . . . . . . . . . . . . . . . . .11
Synchronization . . . . . . . . . . . . . . . . . . . . 11
Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . 12
Use of the clock synchronizing
mechanism as a handshake . . . . . . . . . . . 13
FORMATS WITH 7-BIT ADDRESSES . . . .13
7-BIT ADDRESSING . . . . . . . . . . . . . . . . .15
Definition of bits in the first byte . . . . . . . .
General call address . . . . . . . . . . . . . . . . .
START byte . . . . . . . . . . . . . . . . . . . . . . .
CBUS compatibility . . . . . . . . . . . . . . . . . .
15
16
17
18
15.1
15.2
16
16.1
17
17.1
17.2
17.3
17.4
17.5
EXTENSIONS TO THE STANDARD-
MODE I
2
C-BUS SPECIFICATION . . . . . . .19
FAST-MODE . . . . . . . . . . . . . . . . . . . . . . . .19
Hs-MODE . . . . . . . . . . . . . . . . . . . . . . . . . .20
High speed transfer. . . . . . . . . . . . . . . . . . 20
Serial data transfer format in Hs-mode . . . 21
Switching from F/S- to Hs-mode and
back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
18
18.1
18.1.1
19
20
2
Philips Semiconductors
The I
2
C-bus specification
1
1.1
PREFACE
Version 1.0 - 1992
voltages. This updated version of the I
2
C-bus specification
meets those requirements and includes the following
modifications:
•
The High-speed mode (Hs-mode) is added. This allows
an increase in the bit rate up to 3.4 Mbit/s. Hs-mode
devices can be mixed with Fast- and Standard-mode
devices on the one I
2
C-bus system with bit rates from 0
to 3.4 Mbit/s.
•
The low output level and hysteresis of devices with a
supply voltage of 2 V and below has been adapted to
meet the required noise margins and to remain
compatible with higher supply voltage devices.
•
The 0.6 V at 6 mA requirement for the output stages of
Fast-mode devices has been omitted.
•
The fixed input levels for new devices are replaced by
bus voltage-related levels.
•
Application information for bi-directional level shifter is
added.
1.3
Version 2.1 - 2000
This version of the 1992 I
2
C-bus specification includes the
following modifications:
•
Programming of a slave address by software has been
omitted. The realization of this feature is rather
complicated and has not been used.
•
The “low-speed mode” has been omitted. This mode is,
in fact, a subset of the total I
2
C-bus specification and
need not be specified explicitly.
•
The Fast-mode is added. This allows a fourfold increase
of the bit rate up to 400 kbit/s. Fast-mode devices are
downwards compatible i.e. they can be used in a 0 to
100 kbit/s I
2
C-bus system.
•
10-bit addressing is added. This allows 1024 additional
slave addresses.
•
Slope control and input filtering for Fast-mode devices is
specified to improve the EMC behaviour.
NOTE: Neither the 100 kbit/s I
2
C-bus system nor the
100 kbit/s devices have been changed.
1.2
Version 2.0 - 1998
Version 2.1 of the I
2
C-bus specification includes the
following minor modifications:
•
After a repeated START condition in Hs-mode, it is
possible to stretch the clock signal SCLH (see
Section 13.2 and Figs 22, 25 and 32).
•
Some timing parameters in Hs-mode have been relaxed
(see Tables 6 and 7).
The I
2
C-bus has become a de facto world standard that is
now implemented in over 1000 different ICs and licensed
to more than 50 companies. Many of today’s applications,
however, require higher bus speeds and lower supply
1.4
Purchase of Philips I
2
C-bus components
Purchase of Philips I
2
C components conveys a license under the Philips’ I
2
C patent to use the
components in the I
2
C system provided the system conforms to the I
2
C specification defined by
Philips.
3
Philips Semiconductors
The I
2
C-bus specification
2
THE I
2
C-BUS BENEFITS DESIGNERS AND
MANUFACTURERS
•
The number of ICs that can be connected to the same
bus is limited only by a maximum bus capacitance of
400 pF.
Figure 1 shows two examples of I
2
C-bus applications.
2.1
Designer benefits
In consumer electronics, telecommunications and
industrial electronics, there are often many similarities
between seemingly unrelated designs. For example,
nearly every system includes:
•
Some intelligent control, usually a single-chip
microcontroller
•
General-purpose circuits like LCD drivers, remote I/O
ports, RAM, EEPROM, or data converters
•
Application-oriented circuits such as digital tuning and
signal processing circuits for radio and video systems, or
DTMF generators for telephones with tone dialling.
To exploit these similarities to the benefit of both systems
designers and equipment manufacturers, as well as to
maximize hardware efficiency and circuit simplicity, Philips
developed a simple bi-directional 2-wire bus for efficient
inter-IC control. This bus is called the Inter IC or I
2
C-bus.
At present, Philips’ IC range includes more than 150
CMOS and bipolar I
2
C-bus compatible types for
performing functions in all three of the previously
mentioned categories. All I
2
C-bus compatible devices
incorporate an on-chip interface which allows them to
communicate directly with each other via the I
2
C-bus. This
design concept solves the many interfacing problems
encountered when designing digital control circuits.
Here are some of the features of the I
2
C-bus:
•
Only two bus lines are required; a serial data line (SDA)
and a serial clock line (SCL)
•
Each device connected to the bus is software
addressable by a unique address and simple
master/slave relationships exist at all times; masters can
operate as master-transmitters or as master-receivers
•
It’s a true multi-master bus including collision detection
and arbitration to prevent data corruption if two or more
masters simultaneously initiate data transfer
•
Serial, 8-bit oriented, bi-directional data transfers can be
made at up to 100 kbit/s in the Standard-mode, up to
400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the
High-speed mode
•
On-chip filtering rejects spikes on the bus data line to
preserve data integrity
I
2
C-bus compatible ICs allow a system design to rapidly
progress directly from a functional block diagram to a
prototype. Moreover, since they ‘clip’ directly onto the
I
2
C-bus without any additional external interfacing, they
allow a prototype system to be modified or upgraded
simply by ‘clipping’ or ‘unclipping’ ICs to or from the bus.
Here are some of the features of I
2
C-bus compatible ICs
which are particularly attractive to designers:
•
Functional blocks on the block diagram correspond with
the actual ICs; designs proceed rapidly from block
diagram to final schematic.
•
No need to design bus interfaces because the I
2
C-bus
interface is already integrated on-chip.
•
Integrated addressing and data-transfer protocol allow
systems to be completely software-defined
•
The same IC types can often be used in many different
applications
•
Design-time reduces as designers quickly become
familiar with the frequently used functional blocks
represented by I
2
C-bus compatible ICs
•
ICs can be added to or removed from a system without
affecting any other circuits on the bus
•
Fault diagnosis and debugging are simple; malfunctions
can be immediately traced
•
Software development time can be reduced by
assembling a library of reusable software modules.
In addition to these advantages, the CMOS ICs in the
I
2
C-bus compatible range offer designers special features
which are particularly attractive for portable equipment and
battery-backed systems.
They all have:
•
Extremely low current consumption
•
High noise immunity
•
Wide supply voltage range
•
Wide operating temperature range.
4
Philips Semiconductors
The I
2
C-bus specification
handbook, full pagewidth
SDA
SCL
MICRO-
CONTROLLER
PCB83C528
PLL
SYNTHESIZER
TSA5512
NON-VOLATILE
MEMORY
PCF8582E
M/S COLOUR
DECODER
TDA9160A
STEREO / DUAL
SOUND
DECODER
TDA9840
SDA
SCL
PICTURE
SIGNAL
IMPROVEMENT
TDA4670
DTMF
GENERATOR
PCD3311
HI-FI
AUDIO
PROCESSOR
TDA9860
LINE
INTERFACE
PCA1070
VIDEO
PROCESSOR
TDA4685
ADPCM
PCD5032
SINGLE-CHIP
TEXT
BURST MODE
CONTROLLER
SAA52XX
PCD5042
ON-SCREEN
DISPLAY
MICRO-
CONTROLLER
PCA8510
P80CLXXX
MSB575
(a)
(b)
Fig.1 Two examples of I
2
C-bus applications: (a) a high performance highly-integrated TV set
(b) DECT cordless phone base-station.
5
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