CMOS Layout
Measure twice, fab once
6.371 – Fall 2002
10/16/02
L12 – CMOS Layout 1
Lambda-based design rules
One lambda = one half of the “minimum” mask dimension, typically the length
of a transistor channel. Usually all edges must be “on grid”, e.g., in the
MOSIS scalable rules, all edges must be on a lambda grid.
2x2
1
2
3
2
2
3
3
1
diffusion (active)
poly
metal1
contact
More info at: http://www.mosis.org/Technical/Designrules/scmos/scmos-main.html
6.371 – Fall 2002
10/16/02
L12 – CMOS Layout 2
2
1
2
3
2x2
3
λ
vdd
Sample
“Lambda”
Layout
A
Y
vss
6.371 – Fall 2002
10/16/02
L12 – CMOS Layout 3
Sample Sea-of-Gates Layout
vss
nfets
Column showing all
possible contact
locations
pfets
vdd
pfets
nfets
vss
6.371 – Fall 2002
10/16/02
L12 – CMOS Layout 4
Lamba vs. Micron rules
Lambda-based design rules are based on the assumption that one can scale
a design to the appropriate size before manufacture. The assumuption is
that
all manufacturing dimensions scale equally,
an assumption that “works”
only over some modest span of time. For example: if a design is completed
with a poly width of 2λ and a metal width of 3λ then minimum width metal
wires will always be 50% wider than minimum width poly wires.
Consider the following
data from
Weste,
contacted metal pitch
Table 3.2:
lambda lambda
rule = 0.5u
1
λ
0.5
µ
1
λ
0.5
µ
3
λ
1.5
µ
1
λ
0.5
µ
1
λ
0.5
µ
8
λ
4
µ
micron
rule
0.375
µ
0.5
µ
1.0
µ
0.5
µ
0.375
µ
2.75
µ
1/2 * contact size
contact surround
metal-to-metal spacing
contact surround
1/2 * contact size
Scaled design is legal
but much larger than
it needs to be!
6.371 – Fall 2002
10/16/02
L12 – CMOS Layout 5
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