1.0. INTRODUCTION.............................................52.0. HARDWARE INTERFACE .............................53.0. INTERFACING 3 Volt Intel® StrataFlash™Memory..........................................................63.1. Interfacing 3 Volt Intel® StrataFlash™Memory to ARM7TDMI at 33 MHz...............63.1.1. Interface Considerations.......................63.1.2. Processor Interface Signals ..................73.1.3. Control Signal Generation.....................73.2. Interfacing 3 Volt Intel® StrataFlash™Memory to the StrongARM® SA-110 at 40MHz...........................................................113.2.1. Interface Considerations.....................113.2.2. Processor Interface Signals ................123.2.3. Control Signal Generation...................123.3. Interfacing 3 Volt Intel® StrataFlash™Memory to the StrongARM® SA-1100 at190 MHz....................................................153.3.1. Interface Considerations.....................153.3.2. Processor Interface Signals ................163.3.3. Control Signal Generation...................163.4. Interfacing the 3 Volt Intel® StrataFlash™Memory to Intel® StrongARM® SA-1110 at66 MHz......................................................203.4.1. Interface Considerations.....................203.4.2. Processor Interface Signals ................213.4.3. Control Signal Generation...................213.5. Interfacing 3 Volt Intel® StrataFlash™Memory to MC68060 at 66 MHz................233.5.1. Interface Considerations.....................233.5.2. Processor Interface Signals ................243.5.3. Control Signal Generation...................24
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