Chrontel AN96 Application Notes PCB Layout and Design Considerations for CH7023CH7024 10 Introduction The CH7023CH7024 is a device targeting handheld and similar systems which accepts digital input signal encodes and transmits data through a 10bit high speed DAC The device is able to encode the video signals and generate synchronization signals for NTSC PAL interface standards The device accepts different data formats including RGB and YCrCb eg RGB565 RGB666 RGB888 ITU656 like YCrCb etc This ......
AN-96
Chrontel
Application Notes
PCB Layout and Design Considerations for CH7023/CH7024
1.0 Introduction
The CH7023/CH7024 is a device targeting handheld and similar systems which accepts digital input signal,
encodes and transmits data through a 10-bit high speed DAC. The device is able to encode the video signals and
generate synchronization signals for NTSC, PAL interface standards. The device accepts different data formats
including RGB and YCrCb (e.g. RGB565, RGB666, RGB888, ITU656 like YCrCb, etc.).
This application note focuses only on the basic PCB layout and design guidelines for CH7023/CH7024 TV
encoder. Guidelines in component placement, power supply decoupling, grounding, input/output signal
interface are discussed in this document.
The guidelines discussed here are intended to optimize the PCB layout and applications for this product. They
are only for reference. Designers are urged to implement the configurations and evaluate the performance of
the system prior to bringing the design to production.
2.0 Component Placement
Components associated with CH7023/CH7024 should be placed as close as possible to the respective pins.
The following discussion will describe guidelines on how to connect critical pins, component placement, and
layout associated with these pins.
2.1
Power Supply Decoupling
There is only one type of grounding associated with power supply and ground pins. The optimal power supply
decoupling is accomplished by placing a 0.1uF to each of the power supply pins as in
Figure 1
. These
capacitors should be connected as close as possible to their respective power and ground pins using short and
wide traces to minimize lead inductance.
2.1.1 Ground Pins
The ground pins of CH7023/CH7024 should be connected to a common ground plane to provide a low
impedance return path for the supply currents. Whenever possible, each of CH7023/CH7024 ground pins
should connect directly to its respective decoupling capacitor ground lead, then connected to the ground plane
through a ground via. Short and wide traces should be used to minimize the lead inductance.
2.1.2 Power Supply Pins
There are four power supply pins, AVDD, AVDD_DAC, AVDD_PLL, and DVDD. See
Figure
1 for proper
design of the power-ground pairs.
Table 1
shows the power supply and ground pins assignment of
CH7023/CH7024.
206-0000-096
Rev. 1.1,
12/19/2006
1
CHRONTEL
+1.2V ~ +3.3V
+1.2V ~ +3.3V
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1
C50
0.1uF
1
C55
0.1uF
2
38
A6
2
VDDIO
+3.3V
33
1
C22
0.1uF
36
+1.8V
+3.3V
C7
1
C48
0.1uF
1
C51
0.1uF
B7
VDDIO
+1.8V
AVDD
DVDD
16
AVDD
DVDD
G2
1
C53
0.1uF
2
AGND
DGND
18
2
2
AGND
DGND
G3
2
CH7023/CH7024
+3.3V
25
CH7023/CH7024
+1.8V
+3.3V
E7
LQFP
AVDD_DAC
AVDD_PLL
32
BGA
AVDD_DAC
AVDD_PLL
C6
+1.8V
1
C47
0.1uF
29
1
C49
0.1uF
1
C52
0.1uF
D7
1
C54
0.1uF
2
AGND_DAC
AGND_PLL
31
2
2
AGND_DAC
AGND_PLL
D6
2
Figure 1: Power Supply Decoupling
Table 1: Power and Ground Pins
LQFP Pin
38
16
18
25
29
32
31
33
36
BGA Pin
A6
G2
G3
E7
D7
C6
D6
C7
B7
Type
Power
Power
Ground
Power
Ground
Power
Ground
Power
Ground
Symbol
VDDIO
DVDD
DGND
AVDD_DAC
AGND_DAC
AVDD_PLL
AGND_PLL
AVDD
AGND
Description
IO Supply Voltage (1.2-3.3V)
Digital Supply Voltage (1.8V)
Digital Ground
DAC Supply Voltage (3.3V)
DAC Ground
PLL Supply Voltage (1.8V)
PLL Ground
Crystal Supply Voltage (3.3V)
Crystal Ground
2
206-0000-096
Rev. 1.1,
12/19/2006
CHRONTEL
2.2
•
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Internal Reference Pins
ISET
This pin sets the DAC current. A 1.2 KΩ,
1%
tolerance resistor should be connected between ISET
and AGND_DAC as shown in
Figure 2
. A smaller resistance will create more DAC current, resulting
brighter TV out images. This resistor should be placed with short and wide traces as much as possible
to CH7023/CH7024.
ISET
30
ISET
D5
CH7023/CH7024
LQFP
AGND_DAC
29
R1
1.2K
CH7023/CH7024
BGA
AGND_DAC
D7
R2
1.2K
Figure 2: Internal Reference Pins
2.3
•
General Control Pins
RESET*
This pin is the chip reset pin for CH7023/CH7024. RESET* pin, which is internally pulled-up, places
the device in the power on reset condition when this pin is low. A power reset switch can be placed on
the RESETB* pin on the PCB as a hardware reset for CH7023/CH7024 as shown in
Figure 3
. When
the pin is high, the reset function can also be controlled through the serial port.
•
XI/FIN and XO
CH7023/CH7024 has capability to accept external clocks with frequencies from 0.7 MHz to 71.6 MHz.
However, we recommend predefined crystal frequencies as stated in the CH7023/CH7024 datasheet
for the crystal or oscillator.
Predefined crystal frequencies used for CH7023/CH7024 are shown in
Table 2
.
The crystal selection
register is located at Register 0Bh.
206-0000-096
Rev. 1.1,
12/19/2006
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CHRONTEL
Table 2: Predefined Crystal Frequencies
XTAL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Frequency
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3.6864MHz
3.579545MHz
4MHz
12MHz
13MHz
13.5MHz
14.318MHz
14.7456MHz
16MHz
18.432MHz
20MHz
26MHz
27MHz
32MHz
40MHz
49MHz
The crystal load capacitance, C
L
, is usually specified in the crystal spec from the vendor. As an
example to show the load capacitors
Figure 3
gives a reference design for crystal circuit design.
+3.3
V
R
1
10
K
+3.3
V
R
2
10
K
23
RESET*
SW
1
P8058SS
-ND
G6
RESET*
SW
2
P8058SS
-ND
0.1u
F
C
1
0.1u
F
C
2
CH7023/CH7024
CH7023/CH7024
LQFP
34
XI/FIN
35
XO
Y
1
BGA
XI/FIN
XO
C5
B6
Y
2
C
1
38p
F
C
1
48p
F
C
1
58p
F
C
68p
1
F
Figure 3: General Control Pins
•
Reference Crystal Oscillator
CH7023/CH7024 includes an oscillator circuit that allows a predefined-frequency crystal to be
connected directly. Alternatively, an externally generated clock source may be supplied to
CH7023/CH7024. If an external clock source is used, it should have CMOS level specifications. The
clock should be connected to the XI/FIN pin, and the XO pin should be left open. The external source
must exhibit ±20ppm or better frequency accuracy, and have low jitter characteristics.
If a crystal is used, the designer should ensure that the following conditions are met:
4
206-0000-096
Rev. 1.1,
12/19/2006
CHRONTEL
AN-96
The crystal is specified to be predefined-frequency, ±20 ppm fundamental type and in parallel
resonance (NOT series resonance). The crystal should also have a load capacitance equal to its
specified value (C
L
).
External load capacitors have their ground connection very close to CH7023/CH7024 (C
ext
).
To be able to tune, a variable capacitor may be connected from XI/FIN to ground.
Note that the XI/FIN and XO pins each has approximately 10 pF (C
int
) of shunt capacitance internal to
the device. To calculate the proper external load capacitance to be added to the XI/FIN and XO pins,
the following calculation should be used:
C
ext
= (2 x C
L
) - C
int
- 2C
S
where
C
ext
C
L
= external load capacitance required on XI/FIN and XO pins.
= crystal load capacitance specified by crystal manufacturer.
C
int
= capacitance internal to CH7023/CH7024 (approximately 10-15 pF on each of XI/FIN and
XO pins).
C
S
= stray capacitance of the circuit (i.e. routing capacitance on the PCB, associated capacitance
of crystal holder from pin to pin etc.).
In general,
C
int
XI/FIN = C
int
XO = C
int
C
ext
XI/FIN = C
ext
XO = C
ext
such that
C
L
= (C
int
+ C ext) / 2 + C
S
and C ext = 2 (C
L
- C
S
) - C
int
=2C
L
- (2C
S
+ C
int
)
Therefore C
L
must be specified greater than C
int
/2 + C
S
in order to select C
ext
properly.
After C
L
(crystal load capacitance) is properly selected, care should be taken to make sure the crystal
is not operating in an excessive drive level specified by the crystal manufacturer. Otherwise, the
crystal will age quickly and that in turn will affect the operating frequency of the crystal.
For detail considerations of crystal oscillator design, please refer to
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