ADC0805 are CMOS 8-bit successive approximation A D
converters that use a differential potentiometric ladder
similar to the 256R products These converters are de-
signed to allow operation with the NSC800 and INS8080A
derivative control bus with TRI-STATE output latches di-
rectly driving the data bus These A Ds appear like memory
locations or I O ports to the microprocessor and no inter-
facing logic is needed
Differential analog voltage inputs allow increasing the com-
mon-mode rejection and offsetting the analog zero input
voltage value In addition the voltage reference input can
be adjusted to allow encoding any smaller analog voltage
span to the full 8 bits of resolution
Y
Y
Y
Y
Y
Y
Y
Y
Y
Differential analog voltage inputs
Logic inputs and outputs meet both MOS and TTL volt-
age level specifications
Works with 2 5V (LM336) voltage reference
On-chip clock generator
0V to 5V analog input voltage range with single 5V
supply
No zero adjust required
0 3 standard width 20-pin DIP package
20-pin molded chip carrier or small outline package
Operates ratiometrically or with 5 V
DC
2 5 V
DC
or ana-
log span adjusted voltage reference
Key Specifications
Y
Y
Y
Features
Y
Y
Compatible with 8080
mP
derivatives no interfacing
logic needed - access time - 135 ns
Easy interface to all microprocessors or operates
‘‘stand alone’’
Resolution
Total error
Conversion time
g
LSB
g
8 bits
LSB and
g
1 LSB
100
ms
Typical Applications
TL H 5671 – 1
8080 Interface
Error Specification (Includes Full-Scale
Zero Error and Non-Linearity)
Part
Number
Full-
V
REF
2
e
2 500 V
DC
V
REF
2
e
No Connection
Scale
(No Adjustments)
(No Adjustments)
Adjusted
LSB
g
ADC0801
g
ADC0802
ADC0803
g
ADC0804
ADC0805
TL H 5671–31
TRI-STATE is a registered trademark of National Semiconductor Corp
Z-80 is a registered trademark of Zilog Corp
C
1995 National Semiconductor Corporation
LSB
LSB
g
1 LSB
g
1 LSB
TL H 5671
RRD-B30M115 Printed in U S A
(Notes 1 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
) (Note 3)
6 5V
Voltage
b
0 3V to
a
18V
Logic Control Inputs
b
0 3V to (V
CC
a
0 3V)
At Other Input and Outputs
Lead Temp (Soldering 10 seconds)
Dual-In-Line Package (plastic)
260 C
Dual-In-Line Package (ceramic)
300 C
Surface Mount Package
Vapor Phase (60 seconds)
215 C
Infrared (15 seconds)
220 C
Absolute Maximum Ratings
Storage Temperature Range
Package Dissipation at T
A
e
25 C
ESD Susceptibility (Note 10)
b
65 C to
a
150 C
875 mW
800V
Operating Ratings
(Notes 1 2)
Temperature Range
T
MIN
s
T
A
s
T
MAX
ADC0801 02LJ ADC0802LJ 883
b
55 C
s
T
A
s
a
125 C
b
40 C
s
T
A
s
a
85 C
ADC0801 02 03 04LCJ
b
40 C
s
T
A
s
a
85 C
ADC0801 02 03 05LCN
ADC0804LCN
0 C
s
T
A
s
a
70 C
ADC0802 03 04LCV
0 C
s
T
A
s
a
70 C
ADC0802 03 04LCWM
0 C
s
T
A
s
a
70 C
Range of V
CC
4 5 V
DC
to 6 3 V
DC
Electrical Characteristics
The following specifications apply for V
CC
e
5 V
DC
T
MIN
s
T
A
s
T
MAX
and f
CLK
e
640 kHz unless otherwise specified
Parameter
ADC0801 Total Adjusted Error (Note 8)
ADC0802 Total Unadjusted Error (Note 8)
ADC0803 Total Adjusted Error (Note 8)
ADC0804 Total Unadjusted Error (Note 8)
ADC0805 Total Unadjusted Error (Note 8)
V
REF
2 Input Resistance (Pin 9)
Analog Input Voltage Range
DC Common-Mode Error
Power Supply Sensitivity
Conditions
With Full-Scale Adj
(See Section 2 5 2)
V
REF
2
e
2 500 V
DC
With Full-Scale Adj
(See Section 2 5 2)
V
REF
2
e
2 500 V
DC
V
REF
2-No Connection
ADC0801 02 03 05
ADC0804 (Note 9)
(Note 4) V(
a
) or V(
b
)
Over Analog Input Voltage
Range
V
CC
e
5 V
DC
g
10% Over
Allowed V
IN
(
a
) and V
IN
(
b
)
Voltage Range (Note 4)
25
0 75
Gnd – 0 05
g
Min
Typ
Max
g
g
g
g
1
g
1
Units
LSB
LSB
LSB
LSB
LSB
kX
kX
80
11
V
CC
a
0 05
g
V
DC
LSB
LSB
g
g
AC Electrical Characteristics
The following specifications apply for V
CC
e
5 V
DC
and T
A
e
25 C unless otherwise specified
Symbol
T
C
T
C
f
CLK
CR
t
W(WR)L
t
ACC
t
1H
t
0H
Parameter
Conversion Time
Conversion Time
Clock Frequency
Clock Duty Cycle
Conversion Rate in Free-Running
Mode
Width of WR Input (Start Pulse Width)
Access Time (Delay from Falling
Edge of RD to Output Data Valid)
TRI-STATE Control (Delay
from Rising Edge of RD to
Hi-Z State)
Delay from Falling Edge
of WR or RD to Reset of INTR
Input Capacitance of Logic
Control Inputs
TRI-STATE Output
Capacitance (Data Buffers)
Logical ‘‘1’’ Input Voltage
(Except Pin 4 CLK IN)
V
CC
e
5 25 V
DC
20
Conditions
f
CLK
e
640 kHz (Note 6)
(Note 5 6)
V
CC
e
5V (Note 5)
(Note 5)
INTR tied to WR with
CS
e
0 V
DC
f
CLK
e
640 kHz
CS
e
0 V
DC
(Note 7)
C
L
e
100 pF
C
L
e
10 pF R
L
e
10k
(See TRI-STATE Test
Circuits)
Min
103
66
100
40
8770
100
135
125
200
200
640
Typ
Max
114
73
1460
60
9708
Units
ms
1 f
CLK
kHz
%
conv s
ns
ns
ns
t
WI
t
RI
C
IN
C
OUT
300
5
5
450
75
75
ns
pF
pF
CONTROL INPUTS
Note CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately
V
IN
(1)
15
V
DC
2
AC Electrical Characteristics
(Continued)
The following specifications apply for V
CC
e
5V
DC
and T
MIN
s
T
A
s
T
MAX
unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CONTROL INPUTS
Note CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately
V
IN
(0)
I
IN
(1)
I
IN
(0)
Logical ‘‘0’’ Input Voltage
(Except Pin 4 CLK IN)
Logical ‘‘1’’ Input Current
(All Inputs)
Logical ‘‘0’’ Input Current
(All Inputs)
V
CC
e
4 75 V
DC
V
IN
e
5 V
DC
V
IN
e
0 V
DC
b
1
08
0 005
b
0 005
V
DC
mA
DC
mA
DC
1
CLOCK IN AND CLOCK R
V
T
a
V
T
b
V
H
V
OUT
(0)
V
OUT
(1)
CLK IN (Pin 4) Positive Going
Threshold Voltage
CLK IN (Pin 4) Negative
Going Threshold Voltage
CLK IN (Pin 4) Hysteresis
(V
T
a
)
b
(V
T
b
)
Logical ‘‘0’’ CLK R Output
Voltage
Logical ‘‘1’’ CLK R Output
Voltage
I
O
e
360
mA
V
CC
e
4 75 V
DC
I
O
eb
360
mA
V
CC
e
4 75 V
DC
24
27
15
06
31
18
13
35
21
20
04
V
DC
V
DC
V
DC
V
DC
V
DC
DATA OUTPUTS AND INTR
V
OUT
(0)
Logical ‘‘0’’ Output Voltage
Data Outputs
INTR Output
Logical ‘‘1’’ Output Voltage
Logical ‘‘1’’ Output Voltage
TRI-STATE Disabled Output
Leakage (All Data Buffers)
I
OUT
e
1 6 mA V
CC
e
4 75 V
DC
I
OUT
e
1 0 mA V
CC
e
4 75 V
DC
I
O
eb
360
mA
V
CC
e
4 75 V
DC
I
O
eb
10
mA
V
CC
e
4 75 V
DC
V
OUT
e
0 V
DC
V
OUT
e
5 V
DC
V
OUT
Short to Gnd T
A
e
25 C
V
OUT
Short to V
CC
T
A
e
25 C
Supply Current (Includes
Ladder Current)
ADC0801 02 03 04LCJ 05
ADC0804LCN LCV LCWM
f
CLK
e
640 kHz
V
REF
2
e
NC T
A
e
25 C
and CS
e
5V
11
19
18
25
mA
mA
24
45
b
3
04
04
V
DC
V
DC
V
DC
V
DC
mA
DC
mA
DC
mA
DC
mA
DC
V
OUT
(1)
V
OUT
(1)
I
OUT
I
SOURCE
I
SINK
3
45
90
6
16
POWER SUPPLY
I
CC
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions
Note 2
All voltages are measured with respect to Gnd unless otherwise specified The separate A Gnd point should always be wired to the D Gnd
Note 3
A zener diode exists internally from V
CC
to Gnd and has a typical breakdown voltage of 7 V
DC
Note 4
For V
IN
(
b
)
t
V
IN
(
a
) the digital output code will be 0000 0000 Two on-chip diodes are tied to each analog input (see block diagram) which will forward
conduct for analog input voltages one diode drop below ground or one diode drop greater than the V
CC
supply Be careful during testing at low V
CC
levels (4 5V)
as high level analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures and cause errors for analog inputs near full-scale The
spec allows 50 mV forward bias of either diode This means that as long as the analog V
IN
does not exceed the supply voltage by more than 50 mV the output
code will be correct To achieve an absolute 0 V
DC
to 5 V
DC
input voltage range will therefore require a minimum supply voltage of 4 950 V
DC
over temperature
variations initial tolerance and loading
Note 5
Accuracy is guaranteed at f
CLK
e
640 kHz At higher clock frequencies accuracy can degrade For lower clock frequencies the duty cycle limits can be
extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns
Note 6
With an asynchronous start pulse up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process The
start request is internally latched see
Figure 2
and section 2 0
Note 7
The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width An arbitrarily wide pulse width will hold
the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams)
Note 8
None of these A Ds requires a zero adjust (see section 2 5 1) To obtain zero code at other analog input voltages see section 2 5 and
Figure 5
Note 9
The V
REF
2 pin is the center point of a two-resistor divider connected from V
CC
to ground In all versions of the ADC0801 ADC0802 ADC0803 and
ADC0805 and in the ADC0804LCJ each resistor is typically 16 kX In all versions of the ADC0804 except the ADC0804LCJ each resistor is typically 2 2 kX
Note 10
Human body model 100 pF discharged through a 1 5 kX resistor
3
Typical Performance Characteristics
Logic Input Threshold Voltage
vs Supply Voltage
Delay From Falling Edge of
RD to Output Data Valid
vs Load Capacitance
CLK IN Schmitt Trip Levels
vs Supply Voltage
f
CLK
vs Clock Capacitor
Full-Scale Error vs
Conversion Time
Effect of Unadjusted Offset Error
vs V
REF
2 Voltage
Output Current vs
Temperature
Power Supply Current
vs Temperature (Note 9)
Linearity Error at Low
V
REF
2 Voltages
TL H 5671 – 2
4
TRI-STATE Test Circuits and Waveforms
t
1H
t
1H
C
L
e
10 pF
t
0H
t
0H
C
L
e
10 pF
t
r
e
20 ns
t
r
e
20 ns
TL H 5671 – 3
Timing Diagrams
(All timing is measured from the 50% voltage points)
Output Enable and Reset INTR
Note Read strobe must occur 8 clock periods (8 f
CLK
) after assertion of interrupt to guarantee reset of INTR
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