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altera FPGA视频图像处理手册

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标签： FPGA 视频图像处理 altera

详细介绍了altera FPGA图像处理IP核的使用方法，能极大提高开发效率

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Video and Image Processing Suite User Guide Subscribe Send Feedback UGVIPSUITE 20150504 101 Innovation Drive San Jose CA 95134 wwwalteracom TOC2 Contents Video and Image Processing Suite Overview 11 Release Information13 Device Family Support14 Latency15 InSystem Performance and Resource Guidance18 Stall Behavior and Error Recovery 112 Interfaces 21 Video Formats22 AvalonST Video Protocol27 Video Data Packets211 Static Parameters of Video Data Packets211 Control Data Packets215 Ancillary Data Pa......

Video and Image Processing Suite User

Guide

Send Feedback

UG-VIPSUITE

2015.05.04

101 Innovation Drive

San Jose, CA 95134

www.altera.com

TOC-2

Contents

Video and Image Processing Suite Overview..................................................... 1-1

Release Information.....................................................................................................................................1-3

Device Family Support................................................................................................................................ 1-4

Latency...........................................................................................................................................................1-5

In-System Performance and Resource Guidance....................................................................................1-8

Stall Behavior and Error Recovery.......................................................................................................... 1-12

Interfaces............................................................................................................. 2-1

Video Formats.............................................................................................................................................. 2-2

Avalon-ST Video Protocol..........................................................................................................................2-7

Video Data Packets........................................................................................................................ 2-11

Static Parameters of Video Data Packets....................................................................................2-11

Control Data Packets.....................................................................................................................2-15

Ancillary Data Packets.................................................................................................................. 2-19

User-Defined and Altera-Reserved Packets............................................................................... 2-19

Packet Propagation........................................................................................................................ 2-19

Transmission of Avalon-ST Video Over Avalon-ST Interfaces..............................................2-20

Packet Transfer Examples.............................................................................................................2-21

Avalon-MM Slave Interfaces....................................................................................................................2-25

Specification of the Type of Avalon-MM Slave Interfaces.......................................................2-27

Avalon-MM Master Interfaces.................................................................................................................2-28

Specification of the Type of Avalon-MM Master Interfaces....................................................2-28

Buffering of Non-Image Data Packets in Memory............................................................................... 2-29

Getting Started.................................................................................................... 3-1

IP Catalog and Parameter Editor...............................................................................................................3-1

Specifying IP Core Parameters and Options................................................................................3-2

Installing and Licensing IP Cores.............................................................................................................. 3-2

OpenCore Plus IP Evaluation........................................................................................................ 3-3

Clocked Video Interface IP Cores.......................................................................4-1

Control Port..................................................................................................................................................4-1

Clocked Video Input Format Detection................................................................................................... 4-2

Interrupts.......................................................................................................................................... 4-5

Clocked Video Output Video Modes........................................................................................................4-5

Interrupts.......................................................................................................................................... 4-9

Generator Lock.............................................................................................................................................4-9

Underflow and Overflow.......................................................................................................................... 4-11

Timing Constraints....................................................................................................................................4-12

Handling Ancillary Packets...................................................................................................................... 4-12

Altera Corporation

TOC-3

Modules for Clocked Video Input II IP Core........................................................................................ 4-15

Clocked Video Interface Parameter Settings......................................................................................... 4-18

Clocked Video Interface Signals.............................................................................................................. 4-26

Clocked Video Interface Control Registers............................................................................................4-36

2D FIR Filter IP Core.......................................................................................... 5-1

Calculation Precision...................................................................................................................................5-1

Coefficient Precision....................................................................................................................................5-2

Result to Output Data Type Conversion.................................................................................................. 5-2

2D FIR IP Core Parameter Settings...........................................................................................................5-2

2D FIR Filter Signals....................................................................................................................................5-4

2D FIR Filter Control Registers................................................................................................................. 5-5

Video Mixing IP Cores........................................................................................ 6-1

Alpha Blending.............................................................................................................................................6-2

Video Mixing Parameter Settings..............................................................................................................6-3

Video Mixing Signals...................................................................................................................................6-5

Video Mixing Control Registers................................................................................................................ 6-8

Chroma Resampler IP Core................................................................................ 7-1

Horizontal Resampling (4:2:2)................................................................................................................... 7-1

4:4:4 to 4:2:2...................................................................................................................................... 7-2

4:2:2 to 4:4:4...................................................................................................................................... 7-2

Vertical Resampling (4:2:0)........................................................................................................................ 7-3

Chroma Resampler Parameter Settings.................................................................................................... 7-4

Chroma Resampler Signals.........................................................................................................................7-5

Video Clipping IP Cores..................................................................................... 8-1

Video Clipping Parameter Settings........................................................................................................... 8-1

Video Clipping Signals................................................................................................................................8-4

Video Clipping Control Registers..............................................................................................................8-6

Color Plane Sequencer IP Core...........................................................................9-1

Combining Color Patterns..........................................................................................................................9-1

Rearranging Color Patterns........................................................................................................................9-2

Splitting and Duplicating............................................................................................................................9-3

Subsampled Data..........................................................................................................................................9-4

Color Plane Sequencer Parameter Settings.............................................................................................. 9-4

Color Plane Sequencer Signals................................................................................................................... 9-5

Color Space Conversion IP Cores..................................................................... 10-1

Input and Output Data Types.................................................................................................................. 10-2

Color Space Conversion............................................................................................................................10-2

Result of Output Data Type Conversion................................................................................................ 10-3

Altera Corporation

TOC-4

Color Space Conversion Parameter Settings..........................................................................................10-4

Color Space Conversion Signals.............................................................................................................. 10-8

Color Space Conversion Control Registers..........................................................................................10-10

Control Synchronizer IP Core.......................................................................... 11-1

Using the Control Synchronizer IP Core............................................................................................... 11-2

Control Synchronizer Parameter Settings..............................................................................................11-4

Control Synchronizer Signals...................................................................................................................11-5

Control Synchronizer Control Registers................................................................................................ 11-6

Deinterlacing IP Cores...................................................................................... 12-1

Deinterlacing Methods..............................................................................................................................12-2

Bob with Scanline Duplication.....................................................................................................12-3

Bob with Scanline Interpolation.................................................................................................. 12-3

Weave.............................................................................................................................................. 12-3

Motion-Adaptive........................................................................................................................... 12-3

Pass-Through Mode for Progressive Frames.............................................................................12-6

Frame Buffering......................................................................................................................................... 12-6

Frame Rate Conversion.............................................................................................................................12-8

Bandwidth Requirement Calculations for 10-bit YCbCr Video......................................................... 12-8

Behavior When Unexpected Fields are Received.................................................................................. 12-9

Handling of Avalon-ST Video Control Packets.................................................................................. 12-10

Deinterlacing Parameter Settings.......................................................................................................... 12-10

Deinterlacing Signals...............................................................................................................................12-17

Deinterlacing Control Registers............................................................................................................ 12-23

Design Guidelines for Broadcast Deinterlacer IP Core......................................................................12-30

Tuning Motion Shift....................................................................................................................12-32

Active Video Threshold Adjustment........................................................................................ 12-32

Frame Reader IP Core....................................................................................... 13-1

Single-Cycle Color Patterns......................................................................................................................13-1

Frame Reader Output Pattern and Memory Organization..................................................................13-2

Frame Reader Parameter Settings............................................................................................................13-3

Frame Reader Signals................................................................................................................................ 13-3

Frame Reader Control Registers..............................................................................................................13-5

Frame Buffer IP Cores.......................................................................................14-1

Double Buffering........................................................................................................................................14-2

Triple Buffering..........................................................................................................................................14-2

Locked Frame Rate Conversion...............................................................................................................14-3

Handling of Avalon-ST Video Control Packets.................................................................................... 14-3

Color Format.............................................................................................................................................. 14-4

Frame Buffer Parameter Settings.............................................................................................................14-5

Frame Buffer Signals..................................................................................................................................14-9

Frame Buffer Control Registers............................................................................................................. 14-13

Altera Corporation

TOC-5

Gamma Corrector IP Core................................................................................ 15-1

Gamma Corrector Parameter Settings....................................................................................................15-1

Gamma Corrector Signals........................................................................................................................ 15-2

Gamma Corrector Control Registers...................................................................................................... 15-3

Interlacer IP Core.............................................................................................. 16-1

Interlacer Parameter Settings................................................................................................................... 16-2

Interlacer Signals........................................................................................................................................16-2

Interlacer Control Registers..................................................................................................................... 16-4

Scaler II IP Core.................................................................................................17-1

Nearest Neighbor Algorithm................................................................................................................... 17-1

Bilinear Algorithm.....................................................................................................................................17-2

Bilinear Algorithmic Description................................................................................................ 17-2

Polyphase and Bicubic Algorithm........................................................................................................... 17-3

Double-Buffering........................................................................................................................... 17-5

Polyphase Algorithmic Description............................................................................................ 17-6

Choosing and Loading Coefficients............................................................................................ 17-6

Edge-Adaptive Scaling Algorithm...........................................................................................................17-8

Scaler II Parameter Settings......................................................................................................................17-9

Scaler II Signals........................................................................................................................................ 17-12

Scaler II Control Registers...................................................................................................................... 17-14

Video Switching IP Cores..................................................................................18-1

Mixer Layer Switching.............................................................................................................................. 18-2

Video Switching Parameter Settings....................................................................................................... 18-3

Video Switching Signals............................................................................................................................18-3

Video Switching Control Registers......................................................................................................... 18-5

Test Pattern Generator IP Cores.......................................................................19-1

Test Pattern.................................................................................................................................................19-1

Generation of Avalon-ST Video Control Packets and Run-Time Control....................................... 19-3

Test Pattern Generator Parameter Settings............................................................................................19-4

Test Pattern Generator Signals................................................................................................................ 19-6

Test Pattern Generator Control Registers.............................................................................................. 19-8

Trace System IP Core........................................................................................ 20-1

Trace System Parameter Settings.............................................................................................................20-2

Trace System Signals................................................................................................................................. 20-3

Operating the Trace System from System Console...............................................................................20-4

Loading the Project and Connecting to the Hardware.............................................................20-5

Trace Within System Console......................................................................................................20-6

TCL Shell Commands................................................................................................................... 20-7

Altera Corporation

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