The Intersil HCS161MS is a Radiation Hardened 4-Input Binary;synchronous counter featuring asynchronous reset and lookaheadcarry logic. The HCS161 has an active-low master reset tozero, MR. A low level at the synchronous parallel enable, SPE,disables counting and allows data at the preset inputs (p0 - p3) toload the counter. The data is latched to the outputs on the positiveedge of the clock input, CP. The HCS161MS has two countoutput, IC. The terminal count output indicates a maximum countfor one clock pulse and is used to enable the next cascadedstage to count.The HCS161MS utilizes advanced CMOS/SOS technology toachieve high-speed operation. This device is a member ofradiation hardened, high-speed, CMOS/SOS Logic Family.The HCS161MS is supplied in a 16 lead Ceramic flatpack(K suffix) or a SBDIP Package (D suffix).
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