串并转换 通过多通道串-并转换器将多个同步串行数据流转换为并行数据(源代码) ** Filenames and Des criptions: ** ** TOP_VHD.vhd - Top level design file ** OUTPUT_PIPELINE.vhd - Output multiplexor tree with pipelining. Depth determined by number of channels ** DELAY.vhd - Delay elements ** OR4X32_REG.vhd - Mux elements ** RD_CNTRL.vhd - Read control circuit ** S2P8X32.vhd - Deserializer block ** MUX_8X1.vhd - Steering muxes ** SYNC.vhd - synchronizing circuit ** WR_CNTRL.vhd - Write control circuit
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