TN-29-07: Small-Block vs. Large-Block NAND Flash Devices
Introduction
Technical Note
Small-Block vs. Large-Block NAND Flash Devices
For detailed NAND Flash device information, see
www.micron.com/products/nand/partlist.aspx.
Introduction
As NAND Flash densities increase, it has become necessary to organize the NAND Flash
array more efficiently while simultaneously reducing cost. Increasing the block size of
the NAND Flash array accomplishes both of these goals. Using fewer blocks increases
READ, PROGRAM, and ERASE performance and reduces chip size by reducing periph-
eral circuits between blocks. Most newer NAND Flash designs use the large-block for-
mat.
A general rule for determining when NAND Flash devices transition from small-block to
large-block organization is:
• Small-block devices
≤
1Gb density.
• Large-block devices
≥
1Gb density.
Array Organization
Small-block NAND Flash devices contain blocks made up of 32 pages, where each page
contains 512 data bytes + 16 spare bytes. Large-block NAND Flash devices contain
blocks made up of 64 pages, each page containing 2,048 data bytes + 64 spare bytes. For a
1Gb NAND Flash device, this translates to 8,192 blocks in the small-block organization
and 1,024 blocks in the large-block organization.
These organizational differences are highlighted in Figures 1 and 2 on page 2 and in
Table 1 on page 3.
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. All
information discussed herein is provided on an “as is” basis, without warranties of any kind.
TN-29-07: Small-Block vs. Large-Block NAND Flash Devices
Array Organization
Figure 1:
1Gb NAND Flash Small-Block Array Organization
528 bytes
I/O 0
I/O 7
1 page
= 528 bytes
= 528 bytes x 32 pages
= (16K + 512) bytes
Data register: 512 bytes
16
1 block
256K pages
(8,192 blocks)
per device
1st half of
data register
(256 bytes)
2nd half of
data register
(256 bytes)
1 block
1 device = 528 bytes x 32 pages x 8,192 blocks
= 1,056 Mb
8 bits
512 bytes (data)
16-byte
spare area
Figure 2:
1Gb NAND Flash Large-Block Array Organization
2,112
bytes
I/O 0
Data register 2,048
bytes
64
I/O 7
1 page
1,024
blocks
per
device
= (2K +
64 bytes)
= (2K +
64) bytes
x
64
pages
= (128K + 4K)
bytes
1 block
1
block
1
device
= (2K +
64) bytes
x
64
pages x 1,024
blocks
= 1,056 Mb
2,048
bytes
(data)
64-byte
spare area
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-29-07: Small-Block vs. Large-Block NAND Flash Devices
Address Cycles
Table 1:
Small-Block/Large-Block Comparison
Page #
0
1
2
…
30
31
32
…
62
63
Total bytes
Small Block
512 bytes + 16 bytes
512 bytes + 16 bytes
512 bytes + 16 bytes
…
512 bytes + 16 bytes
512 bytes + 16 bytes
N/A
…
N/A
N/A
16,896
Large Block
2,048 bytes + 64 bytes
2,048 bytes + 64 bytes
2,048 bytes + 64 bytes
…
2,048 bytes + 64 bytes
2,048 bytes + 64 bytes
2,048 bytes + 64 bytes
…
2,048 bytes + 64 bytes
2,048 bytes + 64 bytes
135,168
Address Cycles
NAND Flash devices have no dedicated address pins. Addresses are loaded via a shared
I/O bus that is also used for loading commands and data. Small-block and large-block
NAND Flash devices use 4 address cycles to load the entire address for a 1Gb device.
However, as shown in Tables 2 and 3, the address cycles are used differently by small-
block and large-block devices. The small-block devices use 1 column address cycle while
the large-block devices require 2 column address cycles. Small-block devices require
more row address cycles due to the increased number of blocks.
Large-block 2Gb devices use 5 address cycles.
Table 2:
Cycle
First
Second
Third
Fourth
Small-Block NAND Flash Address Cycles
I/O7
A7
A16
A24
LOW
I/O6
A6
A15
A23
LOW
I/O5
A5
A14
A22
LOW
I/O4
A4
A13
A21
LOW
I/O3
A3
A12
A20
LOW
I/O2
A2
A11
A19
LOW
I/O1
A1
A10
A18
A26
I/O0
A0
A9
1
A17
A25
Notes: 1. There is no A8 address bit in small-block devices.
Table 3:
Cycle
First
Second
Third
Fourth
Large-Block NAND Flash Address Cycles
I/O7
CA7
LOW
BA7
LOW
I/O6
CA6
LOW
BA6
LOW
I/O5
CA5
LOW
PA5
LOW
I/O4
CA4
LOW
PA4
LOW
I/O3
CA3
CA11
PA3
LOW
I/O2
CA2
CA10
PA2
LOW
I/O1
CA1
CA9
PA1
LOW
I/O0
CA0
CA8
PA0
BA16
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©2005 Micron Technology, Inc. All rights reserved.
TN-29-07: Small-Block vs. Large-Block NAND Flash Devices
Commands
Commands
Some commands differ between small- and large-block NAND Flash devices. The sys-
tem designer should be aware of these differences and implement accordingly. Table 4
shows the basic command set for small-block NAND Flash devices; Table 5 shows the
basic command set for large-block devices.
Table 4:
Command
READ 1
READ 2
READ ID
RESET
PAGE PROGRAM (actual)
PAGE PROGRAM (dummy)
COPY BACK PROGRAM (actual)
COPY BACK PROGRAM (dummy)
BLOCK ERASE
MULTI-PLANE BLOCK ERASE
READ STATUS
READ MULTI-PLANE STATUS
Small-Block NAND Flash Commands
1st Cycle
00h/01h
50h
90h
FFh
80h
80h
00h
03h
60h
60h-60h
70h
71h
2nd Cycle
–
–
–
–
10h
11h
8Ah
8Ah
D0h
D0h
–
–
3rd Cycle
–
–
–
–
–
–
10h
11h
–
–
–
–
Acceptable Command
During Busy
No
No
No
Yes
No
No
No
No
No
No
Yes
Yes
Table 5:
Command
Large-Block NAND Flash Commands
1st Cycle
00h
31h
3Fh
00h
05h
90h
70h
80h
80h
85h
85h
60h
FFh
2nd Cycle
30h
–
–
35h
E0h
–
–
10h
15h
10h
–
D0h
–
Valid During Busy
No
No
No
No
No
No
Yes
No
No
No
No
No
Yes
PAGE READ
PAGE READ CACHE MODE START
PAGE READ CACHE MODE START LAST
READ for INTERNAL DATA MOVE
RANDOM DATA READ
READ ID
READ STATUS
PROGRAM PAGE
PROGRAM PAGE CACHE MODE
PROGRAM for INTERNAL DATA MOVE
RANDOM DATA INPUT for PROGRAM
BLOCK ERASE
RESET
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-29-07: Small-Block vs. Large-Block NAND Flash Devices
Commands
Operation Examples
General operation is similar in small-block and large-block NAND Flash devices. For
example, when reading a page of data, both large- and small-block NAND Flash devices
must first transfer a page of data from the NAND Flash array to the data register, as
shown in Figure 3. The
t
R parameter represents the time required to move the page of
data from the NAND Flash array into the data register. When a page of data is being pro-
grammed in both large- and small-block NAND Flash devices, the data is clocked into
the device serially and stored in the cache register until a PROGRAM CONFIRM com-
mand is issued; the NAND Flash array is then programmed with the data. The
t
PROG
parameter represents the time required to program the data from the data register to the
NAND Flash array.
Figure 3:
Small-Block/Large-Block PROGRAM and READ Operations
512 + 16-byte page
tWC
Serial data in
tRC
Data register
Serial data out
tR
tPROG
Small-
block
NAND
Flash
array
2,048 + 64-byte page
tWC
Serial data in
tRC
Data register
Serial data out
tR
tPROG
Large-
block
NAND
Flash
array
Table 6:
PROGRAM and READ Operation Parameters
Symbol
t
PROG
t
R
t
Parameter Definition
Program time
Random access time
Serial READ cycle time
WRITE cycle time
RC
t
WC
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
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