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DB120 参考板 AR9344 原理图

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标签: AR9344

AR9344

DB120

AR9344

DB120  参考板  AR9344  原理图

5
4
3
2
1
DATE
6/8/2010
REVISION NUMBER
245-02042-010
INITIALS
SC
INITIAL VERSION
DESCRIPTION
1. 25MHz Xtal, 22pF Xtal caps
2. Updt GPIOx cfg strap changes
3. Rst cap = 0.01uF
4. RF changes:
2G
C94,C64 NO Load
C98,C61 = 1.2pF;C97,C60= 1.5pF;C99,C57=1.8pF,C100,C58=2.2nH,
C101,C54=1.8pF;
5G:
C59 is 1.8nH
C106 is 1.8nH
C66, C67, C103, C104 =3.9pF
C68, C109 = 2.2pF
L10,L19 = 1.8nH
8/9/2010
245-02042-011
JaiW
D
D
8/9/2010
245-02042-012
JaiW
Updt RF reworks for 5G:
- 6 components noLOAD (3 per chain)
C68, C59, L10 = noLOAD
C109, C106,L19 =noLOAD
- 8 components change
(4 per chain)
C67= 0ohms L11 =0.9nH C66=2.2pF
C62=0.5pF
C104=0 ohms L20 =0.8nH C103= 2.2pF C105=0.5pF
8/9/2010
245-02042-013
JaiW
Changed Sw Inductor L23 for lower DCR, higher rating
Changed Ethernet switch to AR8327N - page 09,10
Changed VR2 reg for AR8316 to 3.3V optional for AR8327
Added separation for BB, SYNTH pins from main 1.2_RF and 3.3V_RF
Added separation for 1.2V_USB from 1.2_PU and VDD33_USB from VDD33_AR9344
Added separation for VDD33_SWREG from VDD33_AR9344
Changed GPIO allocation
Corrected cfg strap connections
Added Page 13 - T/R Switch, Ant; Changed the RX2G match topology;
C367,C406 = 8.2pF
9/17/2010
245-02042-020
Jai,JK,SC
C
C
R295
R397
R532
DS2,
= NL
= 10K
= 10K
DS5 = load
2G TX: C101, C1xx = 1.2pF (was 1.8pF)
5G TX: Ch0: C67 = 0.6nH C68=0.2pF L11=0
5G TX: Ch1:
10/27/2010
245-02042-021
Jai,JK,SC
AR9344 Pwr supply: Replaced all 22nH with 0 ohms.
L11 - 0 Ohms
C703 = 0.1uF
11/12/2010
245-02042-022
Jai,JK,SC
2G:
L51 NL
AR8327: MDC R583 = 330E MDIO R565 =1K
Pwr:
C706 C704 C703 C707 C344 C376 C708 C705 C379 C380 = 0.1uF
5G: Ch-0
C62 - 1.8pF C66 - 1.2pF C67 - 0.6nH C68 - 0.2pF C721 - 2.2pF
0.2pF C734 - 2.2pF
DB120
B
Ch-1 C103 - 1.2pF C105 - 1.5pF C104 - 1.2nH C109 -
802.11 a/b/g/n DBDC (Dual Band Dual Concurrent) Dev Board
AR9344 + AR9380+ AR8327 4 LAN+1 WAN 10/100/1000 router
12/10/2010
245-02042-023
Jai/SC
1. Changed mem part to 64M for 128M total
2. LNA chain 0 changes
C724 = 1.2pF
R567 = 49.9ohm
R605 = NL
R609,R606 = 0 ohm;
B
12/19/2010
245-02042-030
Jai/SC
1.
2.
3.
4.
5.
Added xPAs for 5G AR9344
Added PAs, LNAs for AR9380
Moved optional reg to 1.15V rail for AR8327
GPIO connections for boot_MDIO, MDC corrected
bufr option on MDC pullup opt to 3.3V on MDIO
1/21/2011
245-02042-031
Jai
1. 40Mhz xtal sel R396 = 10K
2. MDC pullup R583 = 560E
3. 2G Tx match changed:
C94, C64= 0.3pF;
C95,C96, C63, C65 = 6.8pF;
C101, C54=1.5pF;
4. SWrst option R499 = NC
SC
2/10/2011
245-02042-032
For 2G Tx match:
C97,C98,C60,C61 = 1.3pF
C101,C54 = 1.0pF
C99, C57 = 1.8pF
VDD33_RF (for 5G flatness issue)
R676 = 1.0nH
VDD12_BB decoupling: C706=1000pF
A
2/17/2011
245-02042-033
Jai
1. (spectral flatness) L11 = 1.5nH 0201
2. (ch0 revert LNA to rec. values) R567 = 27E, C724 = 6.8pF
3. (DDR ck term change): R355,R356, R88, R89 = 0E
R357, R87 = 100E
Correcting error for Ops. U5 VSSDL connected to GND. some silk text updt.
DDR2 Memory part updated for more effective BOM
A
4/05/2011
4/28/2011
245-02042-040
245-02042-041
Jai
Jai
ATHEROS CONFIDENTIAL
PRELIMINARY
5
4
3
Atheros Communications, Inc
1700 Technology Drive
San Jose, CA 95110
Date
Thursday, July 07, 2011
2
Title
Title And Revision
DWG NO
Size C
Rev
?
Sheet
1
of
15
1
245-02042-041
5
4
3
2
1
10/100
WAN PORT
I2S
USB dev
D
4 10/100 ETHERNET PORTS
xMII Connector
USB host
NAND FLASH
Switch Control
D
5G_TX_0 Match
PA
SP3T SWITCH
UART
4 10/100/1000 ETHERNET PORTS
EJTAG
NOR FLASH
25MHz/
40MHz XTAL
RGMII
5G_RX_0 Match
2G_RX_0 Match
DIPLEXER
WBAND
LNA
Ant-0
AR9344
Option C
2G_TX_0 Match
C
5G_TX_1 Match
PA
C
5G_RX_1 Match
2G_RX_1 Match
DIPLEXER
WBAND
LNA
AR8327
32bit DDR2
2G_TX_1 Match
1.8V
10/100/1000
WAN PORT
PCIe RC
PNP
PCIe EP
B
SP3T SWITCH
Ant-1
PCIe Connector
PCIe CONNECTOR
B
AR9380
LX
1.1V
VR1
VR
IND
1.1V
VR3
VR
1.2V
3.3V
2.5V
VR
1.2V
5G_TX_0 Match
PA
SP2T SWITCH
5G Ant-0
5G_RX_0 Match
LNA
5G_TX_1 Match
PA
SP2T SWITCH
5G Ant-1
5G_RX_1 Match
LNA
+5V
5G_TX_2 Match
A
PA
SP2T SWITCH
5G Ant-2
A
5G_RX_2 Match
LNA
Atheros Communications, Inc
Title
ATHEROS CONFIDENTIAL
Date
5
4
3
1700 Technology Drive
San Jose, CA 95110
Saturday, April 30, 2011
2
Block Diagram
DWG NO
Size C
Rev
?
Sheet
2
of
15
1
245-02042-041
5
4
3
2
1
VDD3p3
U4A
VDD12_AR9344
VDD25_AR9344
0
R587
C752
0.1uF
+/-10%
6.3V
C751
0.01uF
+/-10%
10V
R676
VDD33_RF
U4J
AR9344-W ASP-TEST
{7}
NAND_CE
{7} NAND_READ_BUSY
{7}
NAND_WE
{7}
NAND_RE
{7}
NAND_ALE
{7}
NAND_CLE
{7}
NAND_WP
{7}
{7}
{7}
{7}
{7}
{7}
{7}
{7}
NAND_IO7
NAND_IO6
NAND_IO5
NAND_IO4
NAND_IO3
NAND_IO2
NAND_IO1
NAND_IO0
AD26
AE19
AE21
AE22
AE24
AC25
AD25
AA26
AB25
AE6
B8
C14
Y26
L25
U25
H2
T2
C8
AE8
AE12
R25
P26
AE15
AE17
V26
G25
AD2
AVDD20
CTRL2P0
AVDD12_SC
AVDD12_SC
AVDD12_SC
AVDD25_SC
AVDD25_SC
AVDD25_SC
AVDD25_SC
DVDDVCO
AVDD_VCO
VDD25_bottom
VDD25_top
VDD25_top
VDD25_reg
VDD25_right
VDD25_right
VDD12CD_left
VDD12CD_left
VDD12CD_top
VDD12CD_bottom
VDD12CD_bottom
VDD12CD_right
VDD12CD_right
VDD12_PCIe
VDD12_PCIe
VDD12_PLL_USB
VDD12_PLL
VDD3p3V
VDD33_LDO
VDD33_USB
VDD33_RF_PAD[0]
VDD33_RF_PAD[1]
VDD33_XTAL
VDD33_PLL
VDD33_SYNTH
VDD12_RF_PAD[0]
VDD12_RF_PAD[1]
VDD12_BB_PAD[0]
VDD12_BB_PAD[1]
VDD12_SYNTH
VDD12D_SYNTH
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD33_SWREG_0
VDD33_SWREG_1
Y25
AD3
W26
B25
G26
K25
H25
C20
B21
C26
B18
F25
C18
C19
P3
F2
K2
V2
AB2
C6
C4
AG1
AG2
AF2
AF3
AG3
VDD33_AR9344
VDD33_USB
VDD33_RF_
C380
0.1uF
+/-10%
6.3V
C376
0.1uF
+/-10%
6.3V
C819
1.0nH
1uF
+/-0.1NH
+/-10%
6.3V
C111
10pF
+/-5%
50V
R92
C108
0.1uF
+/-10%
6.3V
3.3V
0
AVDDVCO
VDD12_RF
0
R354
C393
10uF
6.3V
+/-20%
VDD33_XTAL
VDD33_PLL
VDD33_SYNTH
VDD12_RF_
R679
VDD12_RF
0R
+/-5%
1/20W
C379
0.1uF
+/-10%
6.3V
R677
R678
0R
0R
+/-5%
1/20W
+/-5%
1/20W
VDD33_RF
B9
C10
A9
B10
C11
A10
B11
C12
A11
B12
C13
A12
A13
B13
A14
0 R475
? +/-5%
C409
+/-10%
0.1uF
6.3V
VDD12_BB
R680
0R
+/-5%
1/20W
C344
0.1uF
+/-10%
6.3V
C820
1uF
6.3V
+/-10%
NAND_CS_0
NAND_RB_L_0
NAND_WE_L
NAND_RE_L
NAND_ALE
NAND_CLE
NAND_WP_L
NAND_DATA_IO_7
NAND_DATA_IO_6
NAND_DATA_IO_5
NAND_DATA_IO_4
NAND_DATA_IO_3
NAND_DATA_IO_2
NAND_DATA_IO_1
NAND_DATA_IO_0
PCIE_RST_L_IN
PCIE_CLKOUT_N
PCIE_CLKOUT_P
PCIE_TX_N
PCIE_TX_P
PCIE_RX_N
PCIE_RX_P
txn0
txp0
rxn0
rxp0
txn1
txp1
rxn1
rxp1
txn2
txp2
rxn2
rxp2
rxn3
rxp3
txn3
txp3
txn4
txp4
rxn4
rxp4
AD27
AE27
AF27
AG27
AF25
AG25
AG26
AF26
AF24
AG24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
P0_TX-
P0_TX+
P0_RX-
P0_RX+
P1_TX-
P1_TX+
P1_RX-
P1_RX+
P2_TX-
P2_TX+
P2_RX-
P2_RX+
P3_RX-
P3_RX+
P3_TX-
P3_TX+
P4_TX-
P4_TX+
P4_RX-
P4_RX+
P0_TX-
P0_TX+
P0_RX-
P0_RX+
P1_TX-
P1_TX+
P1_RX-
P1_RX+
P2_TX-
P2_TX+
P2_RX-
P2_RX+
P3_RX-
P3_RX+
P3_TX-
P3_TX+
P4_TX-
P4_TX+
P4_RX-
P4_RX+
{11}
{11}
{11}
{11}
{11}
{11}
{11}
{11}
{11}
{11}
{11}
{11}
{11}
{11}
{11}
{11}
{11}
{11}
{11}
{11}
D
D
VDD12_AR9344
VDD12_PCIe
VDD12_AR9344
0
R385
VDD12_SYNTH
C703
0.1uF
C704
0.1uF
+/-10%
6.3V
+/-10%
6.3V
VDD_DDR_AR9344
R681
0R
+/-5%
1/20W
VDD12_BB
C705
0.1uF
+/-10%
6.3V
C706
1000pF
+/-10%
25V
VDD12_RF_
C707
0.1uF
+/-10%
6.3V
C708
0.1uF
6.3V
+/-10%
{8} PCIE_EP_RST_L
PCIE_REFCLK-
PCIE_REFCLK+
PETN0
PETP0
PERN0
PERP0
AF12
AF18
AG18
AF16
AG16
AF17
AG17
VDD33_AR9344
R588
0
1/8W
+/-5%
C424
6.3V
10uF
+/-10%
R399
1
1/10W
+/-5%
R412
1
1/10W
+/-5%
C127
6.3V
C129
22uF
+/-20%
10V
0.01uF
+/-10%
0.1uF
+/-10%
VDD33_SW REG
VDD12_U
C423
10uF
+/-10%
6.3V
C601
0.01uF
+/-10%
10V
VDD12_AR9344
VDD12_RF
0
0
C747
0.1uF
+/-10%
6.3V
R589
R353
R138
1/8W
VDD12_U
VDD12_PU
0
SWREG_L_PAD
CTRL_DDR_XPNP_PAD
SWREG_L_PAD
VDD2p0
CTRL20
AR9344-W ASP-TEST
SW REG_L
L23
SW REG_B22
2.2uH20%
C753
0.1uF
+/-10%
6.3V
+/-5%
C392
+/-10%
0.1uF
6.3V
AA25
W25
VREG_SWREG_FB
SW REG_B22
C754
0.01uF
+/-10%
10V
VDD_DDR_CTRL_XPNP
U4B
USB_DM
USB_DP
rbias_pad
W27
Y27
AB27
R154
2.37K
USB_DM
USB_DP
{7}
{7}
C130
U4H
PCIE_RST_L_OUT
AF15
R386 0
+/-5% ?
PCIE_RST_L
R173
100K
?
+/-1%
{5,8}
VDD12_INT
B20
AE20
AE23
C25
E25
J25
P25
V25
AE25
B26
D26
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E26
F26
H26
J26
AB26
AC26
AE26
J27
L27
P27
V27
AA27
AC27
U4I
PCIE_EP_REFCLK_N
PCIE_EP_REFCLK_P
PCIE_EP_RX_N
PCIE_EP_RX_P
C
AG12
AF13
AF14
AG15
AG14
AG13
PCIE_REFCLK-_PCIe_EP_CONN
PCIE_REFCLK+_PCIe_EP_CONN
{8}
{8}
SYS_RST_L_OUT
L26
R29
0
SYSRST
SYS_RST_L
{8,9,14}
PERN0_PCIE_EP_CONN
PERP0_PCIE_EP_CONN
PETP0_PCIE_EP_CONN
PETN0_PCIE_EP_CONN
{8}
{8}
U4E
DDR_BA_0
Y1
AA1
A3
G1
P2
AC2
B4
E1
N3
AB3
T1
U1
V1
W1
H1
J1
J2
F1
VDD_DDR_VREF
DDR_BA_0
DDR_BA_1
DDR_DQM_0
DDR_DQM_1
DDR_DQM_2
DDR_DQM_3
DDR_DQS_0
DDR_DQS_1
DDR_DQS_2
DDR_DQS_3
DDR_WE_L
DDR_CAS_L
DDR_RAS_L
DDR_CS_L
DDR_CK_N
DDR_CK_P
DDR_CKE
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
AR9344-WASP-TEST
U4D
DDR_DATA_0
DDR_DATA_1
DDR_DATA_2
DDR_DATA_3
DDR_DATA_4
DDR_DATA_5
DDR_DATA_6
DDR_DATA_7
DDR_DATA_8
DDR_DATA_9
DDR_DATA_10
DDR_DATA_11
DDR_DATA_12
DDR_DATA_13
DDR_DATA_14
DDR_DATA_15
DDR_DATA_16
DDR_DATA_17
DDR_DATA_18
DDR_DATA_19
DDR_DATA_20
DDR_DATA_21
DDR_DATA_22
DDR_DATA_23
DDR_DATA_24
DDR_DATA_25
DDR_DATA_26
DDR_DATA_27
DDR_DATA_28
DDR_DATA_29
DDR_DATA_30
DDR_DATA_31
A8
A7
A6
B7
B6
A5
A4
B5
A2
D1
D2
C1
B2
A1
B3
B1
M3
E2
K3
H3
F3
E3
D3
C3
Y2
AA3
Y3
W3
V3
U3
T3
R3
DDR_DATA_0
DDR_DATA_1
DDR_DATA_2
DDR_DATA_3
DDR_DATA_4
DDR_DATA_5
DDR_DATA_6
DDR_DATA_7
DDR_DATA_8
DDR_DATA_9
DDR_DATA_10
DDR_DATA_11
DDR_DATA_12
DDR_DATA_13
DDR_DATA_14
DDR_DATA_15
DDR_DATA_16
DDR_DATA_17
DDR_DATA_18
DDR_DATA_19
DDR_DATA_20
DDR_DATA_21
DDR_DATA_22
DDR_DATA_23
DDR_DATA_24
DDR_DATA_25
DDR_DATA_26
DDR_DATA_27
DDR_DATA_28
DDR_DATA_29
DDR_DATA_30
DDR_DATA_31
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
{6}
PCIE_EP_TX_P
PCIE_EP_TX_N
{8}
DDR_BA_1
{8}
DDR_DQM_0
ERX_EN
ERX_CLK
ERXD0
ERXD1
ERXD2
ERXD3
ETXEN
ETXCLK
ETXD0
ETXD1
ETXD2
ETXD3
EMDC
EMDIO
AG11
AF11
AG10
AF10
AG9
AF9
AG8
AF8
AG7
AF7
AG6
AF6
AE10
AE11
EMDIO
E_TXEN
E_TXC
E_TXD0
E_TXD1
E_TXD2
E_TXD3
DDR_DQM_1
ERX_EN
ERX_CLK
ERXD0
ERXD1
ERXD2
ERXD3
R151
R144
R150
R143
R149
R142
EMDC
22
22
22
22
{9,14}
R583
R688
{9,14}
{9,14}
U4C
DDR_A_0
DDR_A_1
DDR_A_2
DDR_A_3
DDR_A_4
DDR_A_5
DDR_A_6
DDR_A_7
DDR_A_8
DDR_A_9
DDR_A_10
DDR_A_11
DDR_A_12
AB1
AC1
AD1
K1
R1
R2
P1
N2
M1
M2
AA2
L1
L2
DDR_ADDR_0
DDR_ADDR_1
DDR_ADDR_2
DDR_ADDR_3
DDR_ADDR_4
DDR_ADDR_5
DDR_ADDR_6
DDR_ADDR_7
DDR_ADDR_8
DDR_ADDR_9
DDR_ADDR_10
DDR_ADDR_11
DDR_ADDR_12
{6}
{6}
{6}
{6,7}
{6}
{6}
{6}
{6}
{6,7}
{6,7}
{6}
{6}
{6}
DDR_DQM_2
{9,14}
DDR_DQM_3
{9,14}
DDR_DQS_0
{9,14}
DDR_DQS_1
{9,14}
{9,14}
22
49.9
ETX_CLK
C215
No Load
ETX_EN
ETX_CLK
ETXD0
ETXD1
ETXD2
ETXD3
560
+/-1%
1/16W
1K
+/-5%
1/16W
3.3V
3.3V
{9,14}
{9,14}
{9,14}
{9,14}
{9,14}
{9,14}
DDR_DQS_2
DDR_DQS_3
DDR_WE_L
DDR_CAS_L
DDR_RAS_L
DDR_CS_L
DDR_CK_N
DDR_CK_P
DDR_CKE_L
DDR_VREF
AR9344-WASP-TEST
U4F
B
AR9344-WASP-TEST
AR9344-WASP-TEST
AR9344-WASP-TEST
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
A
AE4
AF4
AE5
AF5
AG5
U26
U27
T27
T26
T25
R27
R26
N27
N26
N25
M27
M26
M25
B16
C15
A16
B15
A15
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
No Load
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
5
TCK
TDI
TDO
TMS
S17_INTn
SPI_CS_L
{7}
{7}
{7}
{7}
{8,9}
{7}
PCIE_REFCLK-
+/-5%
0
PCIE_REFCLK+
+/-5%
0
SILK TEXT: AR9380 PCIe
place close to AR9344
R141
1/16W
R140
1/16W
PE_REFCLK-
PE_REFCLK+
R148
0
R389
0
R147
0
R390
0
PCIE_REFCLK-_AR9380
{5}
PCIE_REFCLK-_PCIe_CONN
PCIE_REFCLK+_AR9380
{5}
{8}
PNP TO GENERATE VDD_DDR
3.3V
VDD_DDR
VDD_DDR_PNP
N1
AF1
C2
G2
U2
W2
AE2
G3
J3
L3
AC3
AE3
AG4
C5
C7
AE7
C9
W9
V9
U9
T9
R9
P9
N9
M9
L9
K9
J9
AE9
W10
V10
U10
T10
R10
P10
N10
M10
L10
K10
J10
W11
V11
U11
T11
R11
P11
N11
M11
L11
K11
J11
W12
V12
U12
T12
R12
P12
N12
M12
L12
K12
J12
AE13
W13
V13
U13
T13
R13
P13
N13
M13
L13
K13
J13
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
W19
V19
U19
T19
R19
P19
N19
M19
L19
K19
J19
B19
AE18
W18
V18
U18
T18
R18
P18
N18
M18
L18
K18
J18
W17
V17
U17
T17
R17
P17
N17
M17
L17
K17
J17
C17
B17
A17
AE16
W16
V16
U16
T16
R16
P16
N16
M16
L16
K16
J16
C16
W15
V15
U15
T15
R15
P15
N15
M15
L15
K15
J15
AE14
W14
V14
U14
T14
R14
P14
N14
M14
L14
K14
J14
B14
C
B
AR9344-W ASP-TEST
SPI_MO_SI
{7,8}
PCIE_REFCLK+_PCIe_CONN
PERN0_AR9380
{8}
C126
0.1uF
10V
+/-10%
R139
No Load
R388
No Load
R387
No Load
R153
0
R393
0
R152
0
R394
0
PERN0_AR9380
{5}
R170
{8}
0
+/-5%
1/8W
{8}
UART_SIN
UART_SOUT
USB_LED
{7}
{7}
{8}
{8}
{8}
PERN0
PERN0_PCIe_Conn
PERP0_AR9380
PERN0_PCIE_CONN
PERP0_AR9380
{5}
PNP TO GENERATE AVDD_2.0V
VDD_DDR_CTRL_XPNP
3.3V
AR9344_2G_WLAN_LED
RDY_STATUS_LED
JUMP_START_LED
JUMP_ST_SW
R607
R608
?
0
?
SW RST
WAKE_EP
INTERNET_LED
LED_LINK_1
LED_LINK_2
LED_LINK_3
WAKE_RC
LED_LINK_4
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
{8}
{8}
{8}
2
2
AR9344_5G_WLAN_LED
PERP0
PERP0_PCIe_Conn
PERP0_PCIE_CONN
MMBT2907A
1
Q3
AVDD20_T
R145
PETN0
C131
0.1uF
+/-10%
10V
0
R392
0
R146
0
R391
0
PETN0_AR9380
PETN0_AR9380
{5}
VDD_DDR_AR9344
VDD_DDR_PNP
MMBT2907A
1
Q2
3
PETP0_AR9380
{4,7,8,14}
{4,7,8,14}
{7,8}
{8}
{7,8}
{7,8}
{7,8}
{7,8}
{8,9}
{8,9}
{7,8}
{7,8}
{7,8}
{8}
{8}
{8}
{8}
{8}
{7,8}
{8}
{7,8}
{7,8}
{7,8}
PETP0_AR9380 {5}
R496
2
R410
0
+/-5%
AVDD20 1/8W
MMBT2907A
2
PETN0_PCIe_Conn
C452
0.1uF
10V
+/-10%
R174
10K
CTRL2P0
PETN0_PCIE_CONN
{8}
3
VDD_DDR_PNP
{8}
0
+/-5%
1/10W
C150
10uF
+/-10%
6.3V
C128
1uF
6.3V
+/-10%
Q5
MMBT2907A
1
Q4
R175
No Load
PETP0
C132
0.1uF
+/-10%
10V
1
PETP0_PCIe_Conn
PETP0_PCIE_CONN
SILK TEXT: mPCIe conn
R411
0
+/-5%
1/8W
3
3
A
GPIO_21
GPIO_22
AR9344-WASP-TEST
GPIO4
GPIO17
No Load
No Load
R669
?
R670
?
?
?
GPIO4_DC
GPIO17_DIO
{14}
{14}
ATHEROS CONFIDENTIAL
PRELIMINARY
Atheros Communications, Inc
1700 Technology Drive
San Jose, CA 95110
Date
3
C453
10uF
+/-10%
6.3V
C454
1uF
6.3V
+/-10%
TO I2S/ SLIC
GPIO7
GPIO6
GPIO6
No Load
No Load
R559
?
R560
?
R577
R578
?
0
0
?
GPIO7_DC
GPIO6_DIO
SPI_CLK
SPI_MI_SO
{14}
{14}
{7,8}
{7,8}
Title
AR9344 Digital Interface
DWG NO
TO CFG STRAPs
4
GPIO8
Saturday, April 30, 2011
2
Size Custom
Rev
?
Sheet
3
of
15
1
245-02042-041
5
4
3
2
1
VDD33_RF
C748
C749
TP8
0.1uF
+/-10%
10V
VDD33_RF
1
TP9
0.1uF
+/-10%
10V
1
C338
10pF
+/-5%
50V
R341
0
+/-5%
1/16W
U4G
TP6
C315
+/-5%
50V
10pF
C95
6.8pF
50V
+/-0.25PF
L21
3.9nH
+/-0.1NH
C316
C98
25V
1.3pF
+/-0.1pF
C100
2G_TX_1
+/-0.1NH
3.9nH L18
2.2nH
+/-0.1NH
2G_TX_1
{13}
R333
0
+/-5%
1/16W
RF2OUTN_0
C63
6.8pF
50V
+/-0.25PF
C60
1.3pF
25V
+/-0.1pF
C57
1.8pF
50V
+/-0.25PF
10pF
50V
+/-5%
R332
0
+/-5%
1/16W
C65
6.8pF
50V
+/-0.25PF
D
1
R687
1/20W
D
510
+/-5%
510
+/-5%
B22
B23
C21
C22
RFIN2GP_0
XPABIAS2_0
RFIN2GN_0
XPABIAS2_1
RFIN5GP_0
XPABIAS5_0
XPABIAS5_1
RFIN2GP_1
RFIN2GN_1
RFIN5GP_1
RFIN5GN_1
RFIN5GN_0
A19
A20
A22
A21
RF5INP_0
RF5INN_0
RF2INP_0
RF2INN_0
C336
10pF
50V
+/-5%
R340
0
+/-5%
1/16W
TP7
1
R686
1/20W
XPABIAS5_0
XPABIAS5_1
RF2OUTP_1
C94
0.3pF
+/-0.1PF
50V
RF2OUTN_1
C96
6.8pF
50V
+/-0.25PF
C97
1.3pF
25V
+/-0.1pF
C99
1.8pF
50V
+/-0.25PF
L9
3.9nH
+/-0.1NH
C61
25V
1.3pF
+/-0.1pF
RF2OUTP_0
C64
0.3pF
+/-0.1PF
50V
C58
+/-0.1NH
3.9nH L8
2G_TX_0
2.2nH
+/-0.1NH
2G_TX_0
{13}
A27
B27
D27
C27
RF5INP_1
RF5INN_1
RF2INP_1
RF2INN_1
C101
1.0pF
50V
+/-0.25PF
{13} AR9344_COM_A
{13} AR9344_COM_B
{13} AR9344_COM_C
{13} AR9344_COM_D
D25
C24
B24
C23
C54
1.0pF
50V
+/-0.25PF
ANTA_PAD
ANTB_PAD RFOUT2GP_0
ANTC_PAD RFOUT2GN_0
ANTD_PAD RFOUT5GP_0
RFOUT5GN_0
A24
A23
A26
A25
RF5OUTP_0
RF5OUTN_0
C35
8.2pF
+/-0.25PF
RF2OUTP_1
RF2OUTN_1
RF5OUTP_1
RF5OUTN_1
L12
No Load
RF2INN_1
C79
No Load
?
?
L51
No Load
RF2OUTP_0
RF2OUTN_0
C51
8.2pF
+/-0.25PF
L52
RF2INN_0
1.0pF
+/-0.25PF
50V
2G_RX_1
2G_RX_1
{13}
L54
1.0pF
+/-0.25PF
50V
2G_RX_0
2G_RX_0
{13}
RFOUT2GP_1
RFOUT2GN_1
{3,7,8,14}
RST_B
F27
E27
H27
G27
RFOUT5GP_1
RFOUT5GN_1
AE1
A18
6.19K
K27
Y1
+/-1%
40MHz-7M40000005
1
3
K26
R64
L6
No Load
C80
No Load
?
?
L53
No Load
RESET_B
BIASREF
XTALO
XTALI
RF2INP_1
C36
8.2pF
+/-0.25PF
C75
C
2.0nH
+/-01nH
C69
No Load
?
?
RF2INP_0
C48
8.2pF
+/-0.25PF
C76
2.0nH
+/-01nH
C46
No Load
?
?
C
25MHz
AR9344-WASP-TEST
VDD33_RF
VDD33_RF
1
Y2
2
C367
8.2pF
50V
+/-0.25PF
C406
8.2pF
50V
+/-0.25PF
C773
10uF
+/-20%
6.3V
C756
0.1uF
+/-10% 6.3V
VDD33_RF
R613
0
R614
0
R615
No Load
R616
0
C757
+/-10%
1000pF
25V
?
17
16
15
14
VPD
VDD33_RF
VCC1
H/Lin
GND
C339
2.2uF
6.3V
C337
2.2pF
50V +/-0.25PF
Traces 1 & 2
1/4 Wavelength
L11
C67
0.6nH
+/-0.1NH
C68
0.2pF
50V
1.5nH
+/-0.1NH
+/-0.1PF
C59
No Load
?
5G_TXOUT_0
?
C341
2.2uF
6.3V
C340
2.2pF
50V +/-0.25PF
XPABIAS5_0
GND
Place on
BOT layer
Place on
BOT layer
Traces 1 & 2
1/4 Wavelength
L20
RF5OUTP_1
C104
1.2nH
+/-0.1NH
0R
C109
0.2pF
50V
+/-0.1PF
+/-5%
1/20W
U13
13
VDD33_RF
C758
0.1uF
+/-10%
6.3V
C760
1000pF
+/-10%
25V
2.2pF
+/-0.25PF
C761
50V
R617
22R
+/-5%
?
C759
10pF
50V
+/-5%
1
2
3
4
VCC2
PAon
GND
HB
GND
GND
12
11
10
9
C821
No Load
?
?
5G_TX_0
5G_TX_0
RF5OUTP_0
2.2pF
C106
5G_TXOUT_0
No Load
?
5G_TXOUT_1
?
R619
No Load
? ?
R618
+/-0.25PF 50V
R345
0
GND
GND
GND
1
2
B
R620
No Load
? ?
GND
R342
0
1
2
TXin
GND
B
R343
RF5OUTN_0
0
L10
No Load
C66
50V
1.2pF
+/-0.25pF
R344
C62
RF5OUTN_1
0
L19
No Load
C103
50V
1.2pF
+/-0.25pF
5
6
7
8
C105
PA-SE5005L
1.8pF
50V
+/-0.25PF
C53
50V
2.2pF
+/-0.25PF
L5
1.8nH
+/-0.1NH
L7
No Load
C50
0.5pF
25V +/-0.25pF
5G_RX_0
C49
0.5pF
25V +/-0.25pF
C47
No Load
?
?
5G_RX_0
{13}
RF5INP_1
1.5pF
25V
+/-.25pF
C90
2.2pF
50V +/-0.25PF
L17
1.8nH
+/-0.1NH
L16
No Load
VDD33_RF
VDD33_RF
C91
0.5pF
25V +/-0.25pF
5G_RX_1
C72
0.5pF
25V +/-0.25pF
C92
No Load
?
?
5G_RX_1
{13}
C774
10uF
+/-20%
6.3V
VDD33_RF
C762
0.1uF
+/-10% 6.3V
R621
0
R622
0
R623
No Load
R624
0
RF5INP_0
RF5INN_1
C70
2.2pF
50V +/-0.25PF
L13 1.8nH
+/-0.1NH
RF5INN_0
C52
2.2pF
50V +/-0.25PF
L4 1.8nH
+/-0.1NH
C763
+/-10%
1000pF
25V
?
C764
0.1uF
+/-10%
6.3V
C765
1000pF
+/-10%
25V
17
16
15
14
VPD
U14
XPABIAS5_1
R625
22R
+/-5%
?
VCC1
H/Lin
GND
GND
13
2.2pF
+/-0.25PF
C767
50V
C766
10pF
50V
+/-5%
1
2
3
4
VCC2
PAon
GND
HB
GND
GND
12
11
10
9
C822
No Load
?
?
5G_TX_1
5G_TX_1
2.2pF
5G_TXOUT_1
A
R626
+/-0.25PF 50V
GND
GND
GND
R627
No Load
? ?
R628
No Load
? ?
5
6
7
8
GND
TXin
GND
A
PA-SE5005L
ATHEROS CONFIDENTIAL
PRELIMINARY
Date
5
4
3
Atheros Communications, Inc
1700 Technology Drive
San Jose, CA 95110
Saturday, April 30, 2011
2
Title
Atheros RF Interface
DWG NO
Size Custom
Rev
?
Sheet
4
of
15
1
245-02042-041
5
4
3
2
1
U9C
U9D
AR9380_5G_WLAN_LED
{8}
Y3
U9A
14
13
XTALO
CLKOBS
BT_CLK_EN
77
64
72
108
107
AR9380_RF5INP_1
R281
6.19K
+/-1%
1/20W
AR9380_RF5INN_1
AR9380_RF5INP_0
AR9380_RF5INN_0
39
40
CMODE0
CMODE1
PCIE_RST_L
R247
No Load
D
EPRM_SDA
EPRM_SCLK
CMODE0
GPIO0
GPIO1
GPIO2
GPIO3
41
42
43
44
45
46
47
48
49
50
56
57
OGPIO11
AR9380_RF5INN_2
R458
No Load
10K
+/-5%
1/20W
VDD33_AR9380
R459
VDD33_AR9380
TP10
TP13
TP14
RF2INP_0
RF2INN_0
RF5INP_0
RF5INN_0
RF2INP_1
XPABIAS2_0
XPABIAS5_0
XPABIAS2_1
XPABIAS5_1
XPABIAS2_2
XPABIAS5_2
71
70
69
68
67
66
9
3
AR9380_RF5OUTN_0
AR9380_XPABIAS5_2
AR9380_XPABIAS5_1
3.3V_A
AR9380_RF5OUTP_0
C234 1.0pF
50V +/-0.25PF
C236
0.3pF
50V
+/-0.1PF
AR9380_XPABIAS5_0
AR9380 Chain-0 5G
L31 2.0nH
+/-01nH
C246
0.3pF
50V
+/-0.1PF
AR9380_5G_TX_0
1
1
1
80
1
73
C226
No Load
?
+/-5%
0R
R252
3
78
XTALI
BIASREF
BT_CLKOUT
AR9380
11
10
26
25
81
58
59
61
62
63
CMODE1
GPIO4
RESET_B
GPIO5
GPIO12
GPIO6
GPIO13
GPIO7
GPIO14
GPIO8
GPIO15
GPIO9
GPIO16
GPIO10
GNDPAD
AR9380
1
1
1
TP11
TP12
TP15
C230
No Load
RF2INN_1
RF5INP_1
RF5INN_1
RF2INP_2
PABIASN_1
RF2INN_2
PABIASP_2
RF5INP_2
PABIASN_2
RF5INN_2
XLNABIAS_0
RF2OUTP_0
XLNABIAS_1
RF2OUTN_0
XLNABIAS_2
RF5OUTP_0
RF5OUTN_0
RF2OUTP_1
RF2OUTN_1
RF5OUTP_1
RF5OUTN_1
RF2OUTP_2
SW COM0
RF2OUTN_2
SW COM1
RF5OUTP_2
SW COM2
RF5OUTN_2
SW COM3
AR9380
105
104
93
92
PABIASP_0
PABIASN_0
PABIASP_1
C255
No Load
103
97
88
82
15
1
94
C547
0.1uF
+/-10%
6.3V
C546
10pF
+/-5%
50V
C579
0.1uF
+/-10%
6.3V
C571
10pF
+/-5%
50V
C563
C549
0.1uF
10pF
+/-10% +/-5%
6.3V
50V
C232
50V
2.2pF
+/-0.25PF
L29
1.8nH
+/-0.1NH
L26
No Load
C241 0.5pF
25V +/-0.25pF
C233 1.0pF
50V +/-0.25PF
C235 0.3pF
50V +/-0.1PF
L32
+/-01nH
2.0nH
C245 0.3pF
50V +/-0.1PF
L33
2.7nH
+/-0.1NH
D
AR9380_RF5INP_2
90
89
8
7
R261
0R
+/-5%
?
109
GPIO11
C248
0.5pF
+/-0.1pF
50V
AR9380_XLNABIAS5_0
AR9380_XLNABIAS5_1
AR9380_XLNABIAS5_2
AR9380_RF5INP_0
AR9380_RF5OUTP_0
R253
No Load
CMODE0
CMODE1
C202
PERP0
6.3V
0.1uF
R254
No Load
AR9380_RF5OUTN_0
5
4
102
101
AR9380_5G_RX_0
C240
0.5pF
25V +/-0.25pF
C242
No Load
?
?
AR9380_RF5INN_0
C231 2.2pF
50V +/-0.25PF
L30 1.8nH
+/-0.1NH
{3} PERP0_AR9380
AR9380_RF5OUTN_1
99
+/-10%
R433
No Load
R432
No Load
AR9380_RF5OUTP_1
98
87
C203
0.1uF
6.3V
+/-10%
{3} PERN0_AR9380
PERN0
U9B
17
18
19
20
86
AR9380_RF5OUTP_2
84
AR9380_RF5OUTN_2
83
AR9380_COM_A
AR9380_COM_B
AR9380 Chain-1 5G
L41 2.0nH
+/-01nH
AR9380_RF5OUTP_1
C266 1.0pF
50V +/-0.25PF
C265
0.2pF
50V
+/-0.1PF
C278
0.2pF
50V
+/-0.1PF
AR9380_5G_TX_1
+/-5%
1/16W
R268
0
CON RF 3PIN
R267
C288
No Load
C
32
31
PCIE_TX_P
PCIE_TX_N
C200
No Load
C
{3} PETP0_AR9380
{3} PETN0_AR9380
PETP0
PETN0
1/20W
0R
0R
1/20W
+/-5%
R249
R251
+/-5%
33
34
PCIE_RX_P
PCIE_RX_N
R250
{3} PCIE_REFCLK+_AR9380
100K
+/-1%
{3} PCIE_REFCLK-_AR9380
?
REFCLK+
REFCLK-
30
29
PCIE_REFCLK_P
PCIE_REFCLK_N
S3
C247
3.3pF
No Load
L34
J11
AR9380_RF5OUTN_1
C268 1.0pF
50V +/-0.25PF
C267
50V
0.2pF
+/-0.1PF
L42
2.0nH
+/-01nH
C279 0.2pF
50V +/-0.1PF
L45
2.7nH
+/-0.1NH
C201
No Load
VDD33_AR9380
23
24
~PCIE_WAKE_L
AR9380_5G_TX_0_OUT
{3,8} PCIE_RST_L
PCIE_RST_L
R248
10K
+/-5%
~PCIE_CLKREQ_L
4
3
1
7
OUT1/TX
OUT2/RX
IN
6
5
2
?
?
L48
1.5nH
C249
3.3pF
+/-0.25PF
50V
C277
0.5pF
+/-0.1pF
50V
36
GND
VCONT1
T-GND VCONT2
uPG2163T5N-TSON
0.5pF
ANT3
~PCI_RST_L
AR9380
AR9380_5G_RX_0_IN
C243
2.2pF
+/-0.25PF
50V
C244
3.3pF
+/-0.25PF
50V
C270 2.2pF
50V +/-0.25PF
AR9380_RF5INP_1
L44
1.8nH
+/-0.1NH
L28
No Load
C274 0.5pF
25V +/-0.25pF
AR9380_5G_RX_1
C273
0.5pF
25V +/-0.25pF
C280
No Load
?
?
1
2
C289
No Load
IN
NC
R262
No Load
R263
No Load
1.2V_A
ANT-5GHz
C562
0.1uF
+/-10%
6.3V
C566
0.01uF
+/-10%
10V
C543
0.01uF
+/-10%
10V
+/-5%
50V
10pF
C542
C553
0.01uF
+/-10%
10V
+/-5%
50V
10pF
C548
+/-5%
50V
10pF
C570
+/-5%
50V
10pF
C561
+/-5%
R265
1/20W
R264
0R
TO 5G STAMPED ANTENNA
AR9380_COM_A
AR9380_RF5INN_1
AR9380_COM_B
0R
C269 2.2pF
50V +/-0.25PF
L43 1.8nH
+/-0.1NH
+/-5%
1/20W
+/-5%
1/16W
R300
0
CON RF 3PIN
R301
C296
No Load
AR9380_RF5OUTP_2
C262 1.0pF
50V +/-0.25PF
ANT4
C261
0.2pF
50V
+/-0.1PF
C275
0.2pF
50V
+/-0.1PF
AR9380_5G_TX_2
J16
1.2V_A
U9E
B
VDD12_AR9380
R457
0R
+/-5%
?
S5
C287
3.3pF
No Load
L47
AR9380 Chain-2 5G
L38 2.0nH
+/-01nH
B
2
12
N17224055
C552
0.01uF
10V
+/-10%
N17379853
3.3V_A
C559
0.01uF
10V
+/-10%
C196
1uF
6.3V
+/-10%
R460
0R
+/-5%
?
AVDD12
AVDD12
AVDD12
AVDD12
AVDD12
AVDD12
AVDD12
AVDD33
AVDD33
AVDD33
DVDD12
DVDD12
DVDD12
DVDD12
DVDD12
DVDD12
DVDD12
VDDP12
VDDP12
DVDD33
16
22
27
37
54
55
65
VDD12_AR9380
AR9380_5G_TX_1_OUT
4
3
C284
OUT1/TX
OUT2/RX
IN
6
5
2
?
?
L50
1.5nH
C283
3.3pF
+/-0.25PF
50V
75
R461
0R
+/-5%
?
1
7
76
91
95
AR9380_5G_RX_1_IN
2.2pF
+/-0.25PF
50V
GND
VCONT1
T-GND VCONT2
uPG2163T5N-TSON
0.5pF
1
2
C297
No Load
R284
No Load
R288
No Load
C285
3.3pF
+/-0.25PF
50V
IN
NC
AR9380_RF5OUTN_2
C257 1.0pF
50V +/-0.25PF
C256 0.2pF
50V +/-0.1PF
L36
C259 0.2pF
2.0nH
50V +/-0.1PF
+/-01nH
L37
2.7nH
+/-0.1NH
C565
106
0.22uF
6.3V
+/-20%
6
ANT-5GHz
28
35
VDD33_AR9380
+/-5%
R287
1/20W
R289
0R
TO 5G STAMPED ANTENNA
AR9380_COM_A
74
79
85
AR9380_COM_B
C514
0.1uF
+/-10%
6.3V
C538
0.1uF
+/-10%
6.3V
0R
+/-5%
1/20W +/-5%
1/16W
R299
0
C258
0.5pF
+/-0.1pF
50V
21
38
51
60
C286
3.3pF
No Load
L46
AVDD33
DVDD33
AVDD33
DVDD33
AVDD33
DVDD33
~SWREG_L
C197
2.2uF
6.3V
C75022uF
+/-20%
6.3V
L24
1.2V_INT_AR9380
VDD33_AR9380
96
100
4.7uH
SWREG_L/
R246
C295
J15
AR9380_RF5INP_2
C264
50V
2.2pF
+/-0.25PF
L40
1.8nH
+/-0.1NH
C272 0.5pF
25V +/-0.25pF
AR9380_5G_RX_2
C271
0.5pF
25V +/-0.25pF
C276
No Load
?
?
53
52
10pF
R298
C293
No Load
CON RF 3PIN
S4
SW REG_VDD33
AR9380
C556
0.1uF
+/-10%
6.3V
C516
0.1uF
+/-10%
6.3V
C515
0.1uF
+/-10%
6.3V
C539
0.1uF
+/-10%
6.3V
AR9380_5G_TX_2_OUT
L27
No Load
0R
C199
2.2uF
+/-20%
6.3V
C198
2.2uF
6.3V
+/-20%
4
3
C281
OUT1/TX
OUT2/RX
IN
6
5
2
?
?
L49
1.5nH
C260
3.3pF
+/-0.25PF
50V
AR9380_RF5INN_2
0.5pF
ANT5
C263 2.2pF
50V +/-0.25PF
1
7
GND
VCONT1
T-GND VCONT2
uPG2163T5N-TSON
AR9380_5G_RX_2_IN
2.2pF
+/-0.25PF
50V
C282
3.3pF
+/-0.25PF
50V
L39 1.8nH
+/-0.1NH
1
2
C294
No Load
IN
NC
A
A
R283
No Load
3.3V_A
R285
No Load
ANT-5GHz
+/-5%
R282
1/20W
+/-5%
50V
10pF
C560
+/-5%
50V
10pF
C573
+/-5%
50V
10pF
C572
+/-5%
50V
10pF
C569
+/-5%
50V
10pF
C550
+/-5%
50V
C545
10pF 0.1uF
C544
+/-10%
6.3V
R286
C551
0.1uF
+/-10%
6.3V
C564
0.1uF
+/-10%
6.3V
C567
0.1uF
+/-10%
6.3V
C568
0.1uF
+/-10%
6.3V
C558
0.1uF
+/-10%
6.3V
0R
TO 5G STAMPED ANTENNA
AR9380_COM_A
AR9380_COM_B
0R
+/-5%
1/20W
ATHEROS CONFIDENTIAL
PRELIMINARY
Title
Atheros Communications, Inc
1700 Technology Drive
San Jose, CA 95110
Date
5
4
3
2
AR9380 Interface
DWG NO
Saturday, April 30, 2011
Size Custom
Rev
?
Sheet
5
of
15
1
245-02042-041
展开预览

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评论

lang518899
开发板 图很完整,在设计中值得参考,谢谢分享,就是要专用软件才能打开
2019-12-03 09:51:08回复
coffee_cn
相信公版设计不会错
2019-05-13 22:41:49回复
zsjlover
开发板 图很完整,在设计中值得参考,谢谢分享。
2018-09-12 09:36:09回复
fgh316316
参考设计不会错
2017-12-12 14:19:42回复
wuhaiyunyiyi
开发板 图很完整,在设计中值得参考,谢谢分享。
2017-09-08 11:11:15回复
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