HIGH POWER, HIGH EFFICIENCY, LOW COST CAPACITOR CHARGER
CONCEPT AND DEMONSTRATION
A. Pokryvailo
ξ
, C. Carp and C. Scapellati
Spellman High Voltage Electronics Corporation, 475 Wireless Boulevard
Hauppauge, NY 11788
Abstract
A 20-kJ/s, 10-kV, 1-kHz repetition-rate technology
demonstrator design and testing are described. The goal of
the development was combining high performance and
versatility
with
low-cost
design
and
good
manufacturability. This goal was met using an energy-
dosing converter topology with smart controls adapting
the switching frequency in such a way as to ensure zero-
current switching for all possible scenarios, keeping
maximum duty cycle for high power. The switching is
accomplished at a frequency of up to 55 kHz employing
relatively slow IGBTs with low conduction losses. High
efficiency allows all-air cooled design that fits into a
19”x10”x24” rack.
Design guidelines are reviewed. Comprehensive PSpice
models accounting for numerous parasitic parameters and
mimicking controls for the frequency variation were
developed, and simulation results are presented. Together
with analytical tools, they predicted a pulse-to-pulse
repeatability (PPR) of
±0.15
%; the measured figures are
±0.4
% and
±0.5
% for short- and long-term operation,
respectively, at peak charging and repetition rate.
Repeatability analysis is briefed upon here, and to larger
extent, in an accompanying paper. Test methods are
described. Typical current and voltage traces and results
of thermal runs are presented.
II. MAIN SPECIFICATIONS
Input Voltage
Output Voltage
Average
Charging Rate
PRR
Efficiency
Power factor
Pulse to Pulse
repeatability
+
10%
400 VAC or
480
VAC
−
14%
, 3Φ
50/60 Hz, frequency
±
2%
0÷10 kV
20 kJ/s
Insulation
Size
Weight
Cooling
Single shot to 1 kHz
>92 % at full charging rate, >85 %
at 30 % of rated power
>0.93 at full charging rate
>0.85 at 30 % of rated power
Better than
±
0.5%
at 1 kHz,
10 kV, full power; long-term
Better than
±
0.4% at 1 kHz, 10 kV,
full power; short-term
Better than
±
1%
at 1 kHz, 2 kV-
10 kV, short-term.
Air, 10 kV and below
10½” (6U)H x 19”W x 24”D
rack mount
90 lb (41 kg)
Air
III.
DESIGN
I. INTRODUCTION
Between numerous capacitor charging applications, a
combination of high voltage, high charging rate (tens of
kJ/s and higher), high pulse repetition rate (PRR),
compactness, high efficiency and good pulse-to-pulse
repeatability (PPR) is a serious technological challenge.
Putting
constraints
of
low-cost
and
good
manufacturability makes the charger development even
more difficult. They restrict use of costly switches, e.g.,
SiC, exotic cooling schemes and materials, leaving
freedom to choose proper circuit topology and control
strategy to increase the switching frequency with the
purpose of shrinking the size and improving PPR. This
paper describes an attempt to satisfy the above
contradicting requirements within the constraints of low-
cost proven technology.
A charger block-diagram is shown in Figure 1. The
charger comprises a 3-phase input rectifier with soft start
and a smoothing filter, a converter module (CM), an HV
divider and control means. Triggered by an external
source, the charger charges capacitor Cs that is discharged
onto a dummy load via a high-power switch DSw.
CM comprises an inverter INV, HV transformer using
popular U100/57/25 ferrites, a rectifier R and control
means. The CM’s heart is a half-bridge quasi-resonant
inverter with energy dosing capacitors (Figure 2) [1]-[3].
Work [2] provides the principle and theory of operation.
The benefits of this topology are tight control of the
energy transfer and inherent limitation of the short circuit
current and voltages across the converter components.
The maximum conversion frequency is 55 kHz at low
rail voltage. The parasitics of the HV transformer together
with capacitors Cdiv form the resonant tank circuit.
ξ
email:
Apokryva@spellmanhv.com
801
9781-4244-4065-8/09/$25.00 ©2009 IEEE
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Standard components and subassemblies field-tested in
thousands of Spellman HVPS were used throughout for
low cost and reliability.
light.
a
b
Figure 1
. Charger block-diagram.
Vrail
Z2
D2
{cdiv }
C2
D4
2
{w1}
2
{w2}
Cs
D5
Vr
Z1
D1
C1
{cdiv }
1
D3
1
Figure 2.
Halfbridge inverter with energy dosing
capacitors.
Figure 3. Charger a – front view; b – HV section.
Comprehensive PSpice models accounting for
numerous parasitic parameters and mimicking controls for
the frequency variation were developed assisting in both
the design and interpretation of the experimental data. A
sample of simulated waveforms is given in Figure 4 for
the cases of low- and high line voltage. In these
simulations, Cs was 200 nF, approximately half of that
used in the experiments. It is seen that at any moment
(except the first pulse) during the charging cycle ZCS is
attained. This was confirmed experimentally.
10KV
SEL>>
0V
V(CS)
400A
0A
-400A
0s
100us
I(L1)
200us
Time
300us 400us
The FPGA-based controls are characterized by their
flexibility ensuing from digital processing capabilities.
The standard features include multiple protections (short
circuit, overheat, overcurrent and overvoltage, etc.) and
means of voltage and current setting. Via firmware, an
algorithm is implemented that adapts the switching
frequency in such a way as to ensure zero-current
switching (ZCS) for all possible scenarios, keeping
maximum duty cycle for high power. Thus, the switching
losses are virtually non-existent, which allows using
relatively slow low-cost switches both on the primary and
secondary side.
A precision feedback divider was designed for high-
fidelity measurements necessary for good PPR. A risetime
of less than 1
μs
and low temperature drift were realized.
The packaging was made in a 19” rack-mounted
chassis, 10½” tall, 24” deep. On the front view (Figure
3a), the front panel borrowed from the ubiquitous SR6
series [4] is seen. The filling factor is low as shown in
Figure 3b, so the unit, weighing in at 41 kg, is relatively
460V
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10KV
5KV
0V
V(CS)
500A
SEL>>
0s
I(L1)
Time
100us
200us
300us
b
590V
Figure 4. PSpice simulation for 460V and 590V DC rail
voltage. Cs=200 nF.
Figure 5. Typical waveforms at highline. PRR=1400 Hz
in burst, charge time is 507
μs.
a – load capacitor voltage
and primary winding current; b – collector current.
a
IV. EXPERIMENTAL
A. Measurement Means
For the measurement of the high-frequency current of
the inverter components, Rogowski probes of PEM make,
model CWT15, were used. The Cs voltage was measured
by a Tektronix P6015A probe. Floating voltage
measurements were performed by a differential Tektronix
probe P5200. Efficiency and power factor were measured
with a Voltech power meter, model PM300.
B. Waveforms
One of the main goals of this work was realizing as
high efficiency as possible by enforcing lossless switching
in all possible scenarios at all charge levels and repetition
rates. The noise immunity of the control circuitry in this
sense is also an important issue. A thorough experimental
investigation side by side with PSpice modeling was
performed. We found that no under circumstances ZCS
was disturbed. Several screens below illustrate the results.
Figure 6a shows V
c
and primary winding current I
1
in
burst operation at a PRR of 1400 Hz for Cs=420 nF
(charge rate of 29.4 kJ/s), with the collector current, I
c
, of
one of the transistors displayed on expanded scale in
Figure 6b.
b
a
Figure 6. Typical waveforms at 10 kV@1000 Hz at low
(a) and nominal (b) line.
At low line (longest charge), Cs=420 nF is charged in
750
μs
(Figure 6a), so continuous operation with such
load is limited to a PRR of 1 kHz, if ample dead time is
desirable between the shots. At higher line voltage, the
charge is accomplished faster (Figure 5a, Figure 6b). As
vividly seen in Figure 5b, the conversion frequency adapts
to keep high duty cycle yet maintaining ZCS; there are no
shoot-through currents. The highest conversion frequency
is 55 kHz at low line, with very large margin guaranteeing
ZCS even at abnormal line sags.
V
c
I
1
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C. Repeatability
PRR is an important parameter in capacitor charging
applications. It influences stability of various physical
processes ranging from lasing to pulsed X-rays to plasma
chemistry applications. PPR,
ℜ,
is defined here
1
as
ℜ=
V
C
max
−
V
C
min
V
Cavg
,
(1)
where
V
Cmax
,
V
Cmin
and
V
Cavg
are maximum, minimum and
average values of the voltage across the storage cap for a
predefined number of pulses. Pulse-to-pulse variability
evolves from several factors:
1. Converter remnant energy,
E
rem
, at the End-of-Charge
(EOC). This energy can be stored in the HV
transformer magnetic system, its parasitic
capacitance, resonant capacitors, buswork, etc.
E
rem
may flow wholly or partially to the storage capacitor,
so the output voltage will be higher than the
programmed value.
2. Error in generating EOC signal. This may be caused
by poor-quality feedback, noise, unstable reference
voltage, etc.
3. Delay, t
d
, between EOC and actual IGBT turn-off. It
comprises digital delays, optocouplers delay, and
IGBT turn-off delay. Even constant t
d
, if
commensurable with half-period, affects PPR.
Depending on the circuitry and the components, t
d
can be fractions of a microsecond, i.e., t
d
is
commensurable with half-period.
We will distinguish here between short-term and long-
term PPR. The former is defined as that derived from N
consecutive
pulses. In our measurements, N=80, sampled
from 121
st
to the 200
th
pulse. Thus, short-term PPR is not
influenced by thermal drifts, aging of components, etc. It
is affected by the rail voltage variations to the extent of
the high-frequency rail voltage ringing, excluding slow
input changes. Long-term PPR is also influenced by the
rail voltage variation in the full defined range, for
instance, from 460 VDC to 590 VDC (corresponding to
+
10%
400
VAC
−
14%
). In this report, the reference to long-term
voltage, Vfdbk (with the same sensitivity and offset), and
primary current were monitored. The shortcoming of
these
direct
measurements is their low resolution, of the
order of several bits of the scope vertical resolution.
Arguably, a better technique is differential measurement,
e.g., monitoring the difference between the feedback
voltage and the programming voltage. In such a way, at
EOC the scope would see virtually zero voltage. In the
differential measurement, the feedback voltage was biased
with a voltage equal to the programming value. After
finding fair matching of the V
c
and differential Vfdbk
data, we continued with direct V
c
measurement only.
The scope was triggered by the EOC event. Note that
the discharge switch DSw is fired on in 20
μs
after EOC.
The first 800 shots were collected with a 500-pnt
resolution on a 4-μs/div scale. The waveforms were saved
as screen captures, and 80 frames, starting from 121
st
frame, were saved in the csv format. An Excel
spreadsheet was designed, in which 79 shots
2
were
processed; they are graphed in Figure 7 for several rail
voltages showing pulse-to-pulse V
c
variation.
-2.04
-2.045
Vc, kV
-2.05
-2.055
-2.06
-2.065
-2.07
1 7 13 19 25 31 37 43 49 55 61 67 73 79
shot#
590VDC rail under load PRR 1kHz, P6015A
-6
-6.01
Vc, kV
-6.02
-6.03
-6.04
-6.05
-6.06
1 6 11 16 21 26 31 36 41 46 51 56 61 66 71 76
shot#
520VDC rail under load, 1kHz PRR,
PPR is made in the light of such variations, other
parameters being not controlled.
PPR measurements were taken using the FastFrame
capability of a DPO7054 scope. Up to four signals were
monitored simultaneously. The load voltage, V
c
, was
measured again by the P6015A probe, but on a 100-mV
scale with a 10-V offset allowing the signal at end-of-
charge (EOC) fit the screen. In addition, the feedback
2
PPR is defined by most vendors as
±xx%,
so 1% in our
measurements corresponds to
±0.5%
in their definition.
1
Values shown are averages of 50 points, starting from
250 pnt of the acquisition (approximately, the middle part
of the screen Figure 8).
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-9.88
-9.9
Vc, kV
-9.92
-9.94
-9.96
-9.98
590VDC rail under load, PRR 1kHz, P6015A
10 kHz with short-term- and long-term repeatability of
1.5 % and 4.6 %, respectively. However, the existing
DSw limits the operation to 1-kHz CW.
a
I
1
V
c
1 6 11 16 21 26 31 36 41 46 51 56 61 66 71 76
shot#
Figure 7. Shot-to-shot variability taken with FastFrame.
Cs=420 nF, 1 kHz reprate, 2 kV, 6 kV and 10 kV settings.
See inset annotations for rail voltage.
Three typical screenshots of the overlays of 80 frames
are shown in Figure 8. They correspond to data Figure 7
and show quite vividly wherefrom the variability, at least
partially, evolves. At EOC, the primary current is chopped
at random. If there is a certain pattern (as seen at 2-kV
and 6-kV settings), PPR is better. When the current is
chopped at an arbitrary time point (10-kV setting), at the
rising and trailing edges, and at zero, PPR deteriorates. It
still remains below
±0.
5% at maximum voltage and PRR,
owing to specifics of the used converter topology and
high conversion frequency.
For 3 rail voltage settings, namely 460 VDC, 520 VDC
and 590 VDC, PPR was calculated by the formula, in
Excel convention,
(min(A2 : C80) - max(A2 : C80))
,
average(A2 : C80) *100
(2)
b
I
1
V
c
c
I
1
V
c
where columns A-C contain each V
c
values for 79
consecutive pulses, for 460, 520 and 590 VDC,
respectively. Alternatively, we varied the line voltage
continuously from the low to high level, looking for the
least stable operation, i.e., for the largest V
c
variation. For
this method, PPR was calculated by (1) using
V
Cmax
,
V
Cmin
values from the whole measurement range.
Short- and long-term PPR are plotted in Figure 9, Figure
10, respectively. The experimental curves shown in
Figure 10 are calculated by (1), (2); they are marked as "
3
rail experimental
" and "
overall experimental cont rails
",
respectively. The variability is larger than predicted by
theory accounting for the Factor 1 only (“analytical”
curve—see accompanying paper). This discrepancy can
be attributed to the measurement errors and propagation
delays (Factors 2, 3).
With much smaller Cs=33nF the charge to 10 kV is
accomplished in 53
μ
s at low line, which allows PRR of
Figure 8. Overlay of 80 frames (V
c
- 100 V/div, I
1
–
100 A/div) for: a) high line, 2 kV@1 kHz; b) nominal
line, 6 kV@1 kHz; c) high line, 10 kV@1 kHz
D. Efficiency and Power Factor
The efficiency is calculated from the values of the input
and load power, the former being measured by a Voltech
PM300 power meter. Measuring the load power is
indirect. It is actually calculated as the energy per shot
delivered to the storage capacitor (E=Cs
⋅
V
c2
/2) multiplied
by PRR. At full power, the efficiency was about 92 %,
and power factor, PF, was 94 % (Figure 11). The
efficiency values are lower by 1-2 % than expected and
what could be deducted from the loss estimation, and
intuitively from the amount of the dissipated heat. We
note that the IGBTs baseplate overheat was less than
805
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