With the possible exceptions of speed, deterministic timing, and low power, few things are asimportant to programmable logic designers as reconfigurability and available I/O. In-SystemProgramming (ISP) has provided a flexible means of reconfigurability, but this feature mandatesthe availability of at least four pins to accommodate ISP and Boundary Scan operations. SomeISP devices provide dual configurations of the JTAG pins, where the ISP pins may beconfigured as general purpose I/O if not required for ISP or Boundary Scan. In most cases,however, the designation of JTAG pins as I/O precludes this device from future ISP operationsunless the part is bulk erased using a VPP mode of erasure. Historically, the use of ISPtechniques exacerbated the issue of insufficient device I/O, especially for smaller devices withlow I/O counts.
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