High-Performance DSC CPU Modified Harvard architecture C compiler optimized instruction set 16-bit wide data path 24-bit wide instructions Linear program memory addressing up to 4M istruction words Linear data memory addressing up to 64 Kbytes 71 base instructions: mostly 1 word/1 cycle Sixteen 16-bit General Purpose Registers Flexible and powerful Indirect Addressing modes Software stack 16 x 16 multiply operations 32/16 and 16/16 divide operations Up to ?6-bit data shifts
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