Intel
®
Core™ i7 Processor Family for
LGA2011-v3 Socket
Datasheet – Volume 1 of 2
Supporting Desktop Intel
®
Core™ i7-5960X Extreme Edition Processor for
the LGA2011-v3 Socket
Supporting Desktop Intel
®
Core™ i7-59xx and i7-58xx Processor Series
for the LGA2011-v3 Socket
August 2014
330839-001
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2
Datasheet
Table of Contents
1
Introduction
.............................................................................................................. 9
1.1
Processor Feature Details ................................................................................... 10
1.2
Supported Technologies ..................................................................................... 11
1.3
Interfaces ........................................................................................................ 11
1.3.1 System Memory Support ......................................................................... 11
1.3.2 PCI Express* ......................................................................................... 12
1.3.3 Direct Media Interface Gen 2 (DMI2)......................................................... 13
1.3.4 Platform Environment Control Interface (PECI) ........................................... 14
1.4
Power Management Support ............................................................................... 14
1.4.1 Processor Package and Core States........................................................... 14
1.4.2 System States Support ........................................................................... 14
1.4.3 Memory Controller.................................................................................. 14
1.4.4 PCI Express* ......................................................................................... 14
1.5
Thermal Management Support ............................................................................ 14
1.6
Package Summary............................................................................................. 15
1.7
Terminology ..................................................................................................... 15
1.8
Related Documents ........................................................................................... 18
Interfaces................................................................................................................
20
2.1
System Memory Interface .................................................................................. 20
2.1.1 System Memory Technology Support ........................................................ 20
2.1.2 System Memory Timing Support............................................................... 20
2.2
PCI Express* Interface....................................................................................... 21
2.2.1 PCI Express* Architecture ....................................................................... 21
2.2.1.1 Transaction Layer ..................................................................... 22
2.2.1.2 Data Link Layer ........................................................................ 22
2.2.1.3 Physical Layer .......................................................................... 22
2.2.2 PCI Express* Configuration Mechanism ..................................................... 22
2.3
Direct Media Interface 2 (DMI2) / PCI Express* Interface ....................................... 23
2.3.1 DMI2 Error Flow ..................................................................................... 23
2.3.2 Processor / PCH Compatibility Assumptions................................................ 23
2.3.3 DMI2 Link Down..................................................................................... 23
2.4
Platform Environment Control Interface (PECI) ...................................................... 23
Technologies
........................................................................................................... 24
3.1
Intel
®
Virtualization Technology (Intel
®
VT) ......................................................... 24
3.1.1 Intel
®
VT-x Objectives ............................................................................ 24
3.1.2 Intel
®
VT-x Features .............................................................................. 25
3.1.3 Intel
®
VT-d Objectives ............................................................................ 25
3.1.3.1 Intel
®
VT-d Features Supported.................................................. 26
3.1.4 Intel
®
Virtualization Technology Processor Extensions ................................. 26
3.2
Security Technologies ........................................................................................ 27
3.2.1 Intel
®
Advanced Encryption Standard New Instructions
(Intel
®
AES-NI) Instructions .................................................................... 27
3.2.2 Execute Disable Bit................................................................................. 27
3.3
Intel
®
Hyper-Threading Technology (Intel
®
HT Technology).................................... 27
3.4
Intel
®
Turbo Boost Technology ........................................................................... 28
3.4.1 Intel
®
Turbo Boost Operating Frequency ................................................... 28
3.5
Enhanced Intel
®
SpeedStep
®
Technology............................................................. 28
3.6
Intel
®
Advanced Vector Extensions (Intel
®
AVX) ................................................... 29
Signal Descriptions
.................................................................................................. 31
4.1
System Memory Interface .................................................................................. 31
4.2
PCI Express* Based Interface Signals................................................................... 32
2
3
4
Datasheet
3
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
5
Direct Media Interface 2 (DMI2) Signals................................................................33
Intel
®
QuickPath Interconnect (Intel
®
QPI) Signals ................................................34
Platform Environment Control Interface (PECI) Signal .............................................34
System Reference Clock Signals ..........................................................................34
JTAG and TAP Signals.........................................................................................34
Serial VID Interface (SVID) Signals ......................................................................35
Processor Asynchronous Sideband and Miscellaneous Signals...................................35
Processor Power and Ground Supplies ..................................................................38
Electrical Specifications
...........................................................................................39
5.1
Integrated Voltage Regulation .............................................................................39
5.2
Processor Signaling ............................................................................................39
5.2.1 System Memory Interface Signal Groups....................................................39
5.2.2 PCI Express* Signals...............................................................................39
5.2.3 Direct Media Interface 2 (DMI2) / PCI Express* Signals ...............................39
5.2.4 Platform Environmental Control Interface (PECI) .........................................40
5.2.4.1 Input Device Hysteresis .............................................................40
5.2.5 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN) .........................40
5.2.6 JTAG and Test Access Port (TAP) Signals....................................................41
5.2.7 Processor Sideband Signals ......................................................................41
5.2.8 Power, Ground and Sense Signals .............................................................41
5.2.8.1 Power and Ground Lands............................................................41
5.2.8.2 Decoupling Guidelines ................................................................42
5.2.8.3 Voltage Identification (VID) ........................................................42
5.2.8.4 SVID Commands .......................................................................42
5.2.8.5 SetVID Fast Command ...............................................................43
5.2.8.6 SetVID Slow .............................................................................43
5.2.8.7 SetVID Decay ...........................................................................43
5.2.8.8 SVID Power State Functions: SetPS .............................................43
5.2.8.9 SVID Voltage Rail Addressing......................................................44
5.2.8.10 Reserved or Unused Signals........................................................46
5.2.9 Reserved or Unused Signals .....................................................................46
5.3
Signal Group Summary.......................................................................................46
5.4
Power-On Configuration (POC) Options .................................................................50
5.5
Absolute Maximum and Minimum Ratings..............................................................51
5.5.1 Storage Conditions Specifications..............................................................51
5.6
DC Specifications ...............................................................................................52
5.6.1 Die Voltage Validation .............................................................................55
5.6.1.1 V
CCIN
Overshoot Specifications ....................................................55
5.6.2 Signal DC Specifications ..........................................................................56
5.6.2.1 DDR4 Signal DC Specifications ....................................................56
5.6.2.2 PECI DC Specifications ...............................................................58
5.6.2.3 System Reference Clock (BCLK{0/1}) DC Specifications .................58
5.6.2.4 SMBus DC Specifications ............................................................60
5.6.2.5 JTAG and TAP Signals DC Specifications .......................................61
5.6.2.6 Serial VID Interface (SVID) DC Specifications................................61
5.6.2.7 Processor Asynchronous Sideband DC Specifications ......................62
5.6.2.8 Miscellaneous Signals DC Specifications........................................62
Processor Land Listing
.............................................................................................63
6
4
Datasheet
Figures
1-1
1-2
2-1
2-2
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
Platform Block Diagram Example ......................................................................... 10
PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) .................. 13
PCI Express* Layering Diagram........................................................................... 21
Packet Flow through the Layers........................................................................... 21
Input Device Hysteresis ..................................................................................... 40
Voltage Regulator (VR) Power State Transitions..................................................... 44
Serial VID Interface (SVID) Signals Clock Timings ................................................. 53
V
CCIN
Static and Transient Tolerance Loadlines ...................................................... 55
V
CCIN
Overshoot Example Waveform .................................................................... 56
BCLK{0/1} Differential Clock Measurement Point for Ringback ................................ 59
BCLK{0/1} Differential Clock Cross Point Specification ........................................... 59
BCLK{0/1} Single-Ended Clock Measurement Points for Absolute Cross Point and
Swing60
BCLK{0/1} Single-Ended Clock Measure Points for Delta Cross Point ........................ 60
Tables
1-1
1-2
1-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
Terminology ..................................................................................................... 15
Related Publications........................................................................................... 18
Public Publications ............................................................................................. 18
Memory Channel DDR0, DDR1, DDR2, DDR3......................................................... 31
Memory Channel Miscellaneous ........................................................................... 32
PCI Express Port 1 Signals.................................................................................. 32
PCI Express* Port 2 Signals ................................................................................ 32
PCI Express* Port 3 Signals ................................................................................ 33
PCI Express* Miscellaneous Signals ..................................................................... 33
Direct Media Interface 2 (DMI2) Signals ............................................................... 33
Intel QPI Port 0 and 1 Signals ............................................................................. 34
Platform Environment Control Interface (PECI) Signal ............................................ 34
System Reference Clock (BCLK{0/1}) Signals ....................................................... 34
JTAG and TAP Signals ........................................................................................ 34
SVID Signals .................................................................................................... 35
Processor Asynchronous Sideband Signals ............................................................ 35
Miscellaneous Signals ........................................................................................ 37
Power and Ground Signals .................................................................................. 38
Power and Ground Lands.................................................................................... 41
SVID Address Usage .......................................................................................... 44
VR12.5 Reference Code Voltage Identification (VID) Table ...................................... 45
Signal Description Buffer Types ........................................................................... 47
Signal Groups ................................................................................................... 47
Signals with On-Die Weak Pull-Up/Pull-Down Resistors ........................................... 50
Power-On Configuration Option Lands .................................................................. 50
Processor Absolute Minimum and Maximum Ratings ............................................... 51
Storage Condition Ratings .................................................................................. 52
Voltage Specification.......................................................................................... 53
Current (I
CCIN_MAX
and I
CCIN_TDC
) Specification ..................................................... 54
V
CCIN
Static and Transient Tolerance Processor...................................................... 54
V
CCIN
Overshoot Specifications ............................................................................ 56
DDR4 Signal DC Specifications ............................................................................ 56
Datasheet
5
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