ZedBoard
(Zynq™
Evaluation
and
Development)
Hardware User’s Guide
Version 2.2
27 January 2014
Table of Contents
1
INTRODUCTION .................................................................................................................................. 2
1.1
2
Z
YNQ
B
ANK
P
IN
A
SSIGNMENTS
...................................................................................................... 4
FUNCTIONAL DESCRIPTION ............................................................................................................ 5
2.1
A
LL
P
ROGRAMMABLE
S
O
C ............................................................................................................. 5
2.2
M
EMORY
......................................................................................................................................... 5
2.2.1
DDR3 ...................................................................................................................................... 5
2.2.2
SPI Flash ................................................................................................................................ 7
2.2.3
SD Card Interface ..................................................................................................................10
2.3
USB ...............................................................................................................................................11
2.3.1
USB OTG ...............................................................................................................................11
2.3.2
USB-to-UART Bridge ............................................................................................................11
2.3.3
USB-JTAG .............................................................................................................................12
2.3.4
USB circuit protection ...........................................................................................................13
2.4
D
ISPLAY AND
A
UDIO
......................................................................................................................13
2.4.1
HDMI Output.........................................................................................................................13
2.4.2
VGA Connector......................................................................................................................16
2.4.3
I2S Audio Codec ....................................................................................................................17
2.4.4
OLED .....................................................................................................................................18
2.5
C
LOCK SOURCES
.............................................................................................................................18
2.6
R
ESET
S
OURCES
.............................................................................................................................18
2.6.1
Power
‐
on Reset (PS_POR_B)................................................................................................18
2.6.2
Program Push Button Switch.................................................................................................19
2.6.3
Processor Subsystem Reset ....................................................................................................19
2.7
U
SER
I/O ........................................................................................................................................19
2.7.1
User Push Buttons .................................................................................................................19
2.7.2
User DIP Switches .................................................................................................................19
2.7.3
User LEDs .............................................................................................................................20
2.8
10/100/1000 E
THERNET
PHY ........................................................................................................20
2.9
E
XPANSION
H
EADERS
....................................................................................................................21
2.9.1
LPC FMC Connector.............................................................................................................21
2.9.2
Digilent Pmod™ Compatible Headers (2x6).........................................................................22
2.9.3
Agile Mixed Signaling (AMS) Connector, J2 .........................................................................23
2.10 C
ONFIGURATION
M
ODES
................................................................................................................26
2.10.1 JTAG ......................................................................................................................................27
2.11 P
OWER
...........................................................................................................................................28
2.11.1 Primary Power Input .............................................................................................................28
2.11.2 On/Off Switch ........................................................................................................................28
2.11.3 Regulators..............................................................................................................................28
2.11.4 Sequencing .............................................................................................................................29
2.11.5 Power Good LED ..................................................................................................................30
2.11.6 Power Estimation ..................................................................................................................30
2.11.7 Testing ...................................................................................................................................31
2.11.8 Probes ....................................................................................................................................31
3
ZYNQ-7000 AP SOC BANKS .............................................................................................................32
3.1
Z
YNQ
-7000 AP S
O
C B
ANK
V
OLTAGES
..........................................................................................33
4
5
6
JUMPER SETTINGS ............................................................................................................................34
MECHANICAL ....................................................................................................................................36
REVISION HISTORY ..........................................................................................................................37
1
27-Jan-2014
1 Introduction
The ZedBoard is an evaluation and development board based on the Xilinx Zynq -7000 All
Programmable SoC (AP SoC). Combining a dual Corex-A9 Processing System (PS) with 85,000
Series-7 Programmable Logic (PL) cells, the Zynq-7000 AP SoC can be targeted for broad use in
many applications. The ZedBoard’s robust mix of on-board peripherals and expansion
capabilities make it an ideal platform for both novice and experienced designers. The features
provided by the ZedBoard consist of:
•
Xilinx® XC7Z020-1CLG484C Zynq-7000 AP SoC
o
Primary configuration = QSPI Flash
o
Auxiliary configuration options
Cascaded JTAG
SD Card
Memory
o
512 MB DDR3 (128M x 32)
o
256 Mb QSPI Flash
Interfaces
o
USB-JTAG Programming using Digilent SMT1-equivalent circuit
Accesses PL JTAG
PS JTAG pins connected through PS Pmod
o
10/100/1G Ethernet
o
USB OTG 2.0
o
SD Card
o
USB 2.0 FS USB-UART bridge
o
Five Digilent Pmod™ compatible headers (2x6) (1 PS, 4 PL)
o
One LPC FMC
o
One AMS Header
o
Two Reset Buttons (1 PS, 1 PL)
o
Seven Push Buttons (2 PS, 5 PL)
o
Eight dip/slide switches (PL)
o
Nine User LEDs (1 PS, 8 PL)
o
DONE LED (PL)
On-board Oscillators
o
33.333 MHz (PS)
o
100 MHz (PL)
Display/Audio
o
HDMI Output
o
VGA (12-bit Color)
o
128x32 OLED Display
o
Audio Line-in, Line-out, headphone, microphone
Power
o
On/Off Switch
o
12V @ 5A AC/DC regulator
Software
o
ISE® WebPACK Design Software
o
License voucher for ChipScope™ Pro locked to XC7Z020
TM
•
•
•
•
•
•
2
27-Jan-2014
7
Flash
QSPI
8
32
QSPI
<User
Select>
PMOD
Pmods
Pmod
14
Multiplexed I/O (MIO)
Gbit
Enet
USB
OTG
PHY
ENET/
MDIO
USBOTG
82
FMC
FMC-LPC
12
PHY
GPIO
21
SD
SD
Programmable Logic (PL)
8
GPIO (8 LEDs,
8 slide switches,
5 pushbuttons)
HdPhn Out
USB
UART
1 LED,
2 buttons
USB
Cont
2
8
USBUART
I2S/ACD
I2S Audio
Codec
Line Out
Line In
MIC In
3
PS_GPIO
27
HDMI
HDMI
transmitter
Type A
HDMI Out
Processing System (PS)
512Mbyte
DDR3 (x32)
71
VGA
10
DDR3
DDR
VGA (12-
bit color)
Display
OLED
5
128x32 OLED
Reset
33Mhz
Clk
1
PS_RST
PS_CLK
DONE
PROG
GPIO/VP/VN
JTAG
1
1
8
DONE LED
PROG
XADC
USB
Cont
Clk
1
4
Primary JTAG
GCLK
1
100Mhz
ZYNQ XC7Z020-CLG484
Figure 1 – ZedBoard Block Diagram
3
27-Jan-2014
1.1
Zynq Bank Pin Assignments
The following figure shows the Zynq bank pin assignments on the ZedBoard followed by a table
that shows the detailed I/O connections.
Figure 2 - Zynq Z7020 CLG484 Bank Assignments
4
27-Jan-2014
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