OMAP-L138 C6-Integra
DSP+ARM Processor
Technical Reference Manual
Literature Number: SPRUH77
August 2011
2
Copyright
©
2011, Texas Instruments Incorporated
SPRUH77
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August 2011
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Contents
Preface
......................................................................................................................................
81
1
Overview
..........................................................................................................................
83
1.1
1.2
1.3
1.4
1.5
Introduction
.................................................................................................................
Block Diagram
.............................................................................................................
DSP Subsystem
...........................................................................................................
ARM Subsystem
...........................................................................................................
DMA Subsystem
...........................................................................................................
Introduction
.................................................................................................................
Operating States/Modes
..................................................................................................
Processor Status Registers
..............................................................................................
Exceptions and Exception Vectors
......................................................................................
The 16-BIS/32-BIS Concept
.............................................................................................
16-BIS/32-BIS Advantages
...............................................................................................
Co-Processor 15 (CP15)
.................................................................................................
2.7.1 Addresses in an ARM926EJ-S System
........................................................................
2.7.2 Memory Management Unit (MMU)
.............................................................................
2.7.3 Caches and Write Buffer
........................................................................................
84
84
84
84
85
88
89
89
90
91
91
92
92
92
93
2
ARM Subsystem
................................................................................................................
87
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3
DSP Subsystem
................................................................................................................
95
3.1
3.2
Introduction
.................................................................................................................
96
TMS320C674x Megamodule
.............................................................................................
97
3.2.1 Internal Memory Controllers
.....................................................................................
97
3.2.2 Internal Peripherals
...............................................................................................
97
Memory Map
..............................................................................................................
102
3.3.1 DSP Internal Memory
...........................................................................................
102
3.3.2 External Memory
................................................................................................
102
Advanced Event Triggering (AET)
.....................................................................................
102
Introduction
...............................................................................................................
104
System Interconnect Block Diagram
..................................................................................
105
Introduction
...............................................................................................................
ARM Memories
...........................................................................................................
DSP Memories
...........................................................................................................
Shared RAM Memory
...................................................................................................
External Memories
.......................................................................................................
Internal Peripherals
......................................................................................................
Peripherals
................................................................................................................
Introduction
...............................................................................................................
6.1.1 Purpose of the MPU
............................................................................................
6.1.2 Features
..........................................................................................................
6.1.3 Block Diagram
...................................................................................................
6.1.4 MPU Default Configuration
....................................................................................
Contents
Copyright
©
2011, Texas Instruments Incorporated
3.3
3.4
4
System Interconnect
........................................................................................................
103
4.1
4.2
5
System Memory
...............................................................................................................
107
5.1
5.2
5.3
5.4
5.5
5.6
5.7
108
108
108
108
108
109
109
112
112
112
112
113
3
6
Memory Protection Unit (MPU)
..........................................................................................
111
6.1
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6.2
6.3
Architecture
...............................................................................................................
6.2.1 Privilege Levels
..................................................................................................
6.2.2 Memory Protection Ranges
....................................................................................
6.2.3 Permission Structures
..........................................................................................
6.2.4 Protection Check
................................................................................................
6.2.5 DSP L1/L2 Cache Controller Accesses
......................................................................
6.2.6 MPU Register Protection
.......................................................................................
6.2.7 Invalid Accesses and Exceptions
.............................................................................
6.2.8 Reset Considerations
...........................................................................................
6.2.9 Interrupt Support
................................................................................................
6.2.10 Emulation Considerations
.....................................................................................
MPU Registers
...........................................................................................................
6.3.1 Revision Identification Register (REVID)
....................................................................
6.3.2 Configuration Register (CONFIG)
............................................................................
6.3.3 Interrupt Raw Status/Set Register (IRAWSTAT)
............................................................
6.3.4 Interrupt Enable Status/Clear Register (IENSTAT)
.........................................................
6.3.5 Interrupt Enable Set Register (IENSET)
.....................................................................
6.3.6 Interrupt Enable Clear Register (IENCLR)
...................................................................
6.3.7 Fixed Range Start Address Register (FXD_MPSAR)
......................................................
6.3.8 Fixed Range End Address Register (FXD_MPEAR)
.......................................................
6.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
..............................
6.3.10 Programmable Range
n
Start Address Registers (PROGn_MPSAR)
..................................
6.3.11 Programmable Range
n
End Address Registers (PROGn_MPEAR)
...................................
6.3.12 Programmable Range
n
Memory Protection Page Attributes Register (PROGn_MPPA)
............
6.3.13 Fault Address Register (FLTADDRR)
.......................................................................
6.3.14 Fault Status Register (FLTSTAT)
............................................................................
6.3.15 Fault Clear Register (FLTCLR)
..............................................................................
Overview
..................................................................................................................
Frequency Flexibility
.....................................................................................................
Peripheral Clocking
......................................................................................................
7.3.1 USB Clocking
....................................................................................................
7.3.2 DDR2/mDDR Memory Controller Clocking
..................................................................
7.3.3 EMIFA Clocking
.................................................................................................
7.3.4 EMAC Clocking
..................................................................................................
7.3.5 uPP Clocking
....................................................................................................
7.3.6 McASP Clocking
................................................................................................
7.3.7 I/O Domains
.....................................................................................................
Introduction
...............................................................................................................
PLL Controllers
...........................................................................................................
8.2.1 Device Clock Generation
.......................................................................................
8.2.2 Steps for Programming the PLLs
.............................................................................
PLLC Registers
...........................................................................................................
8.3.1 PLLC0 Revision Identification Register (REVID)
...........................................................
8.3.2 PLLC1 Revision Identification Register (REVID)
...........................................................
8.3.3 Reset Type Status Register (RSTYPE)
......................................................................
8.3.4 PLLC0 Reset Control Register (RSCTRL)
...................................................................
8.3.5 PLLC0 Control Register (PLLCTL)
...........................................................................
8.3.6 PLLC1 Control Register (PLLCTL)
...........................................................................
8.3.7 PLLC0 OBSCLK Select Register (OCSEL)
..................................................................
8.3.8 PLLC1 OBSCLK Select Register (OCSEL)
..................................................................
8.3.9 PLL Multiplier Control Register (PLLM)
......................................................................
113
113
114
115
116
116
116
117
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117
118
120
120
121
122
123
123
124
124
125
126
127
128
129
130
131
134
136
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148
148
150
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155
156
157
158
159
160
161
7
Device Clocking
...............................................................................................................
133
7.1
7.2
7.3
8
Phase-Locked Loop Controller (PLLC)
...............................................................................
147
8.1
8.2
8.3
4
Contents
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©
2011, Texas Instruments Incorporated
SPRUH77
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August 2011
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8.3.10
8.3.11
8.3.12
8.3.13
8.3.14
8.3.15
8.3.16
8.3.17
8.3.18
8.3.19
8.3.20
8.3.21
8.3.22
8.3.23
8.3.24
8.3.25
8.3.26
8.3.27
8.3.28
8.3.29
8.3.30
8.3.31
8.3.32
8.3.33
8.3.34
8.3.35
8.3.36
8.3.37
PLLC0 Pre-Divider Control Register (PREDIV)
............................................................
PLLC0 Divider 1 Register (PLLDIV1)
.......................................................................
PLLC1 Divider 1 Register (PLLDIV1)
.......................................................................
PLLC0 Divider 2 Register (PLLDIV2)
.......................................................................
PLLC1 Divider 2 Register (PLLDIV2)
.......................................................................
PLLC0 Divider 3 Register (PLLDIV3)
.......................................................................
PLLC1 Divider 3 Register (PLLDIV3)
.......................................................................
PLLC0 Divider 4 Register (PLLDIV4)
.......................................................................
PLLC0 Divider 5 Register (PLLDIV5)
.......................................................................
PLLC0 Divider 6 Register (PLLDIV6)
.......................................................................
PLLC0 Divider 7 Register (PLLDIV7)
.......................................................................
PLLC0 Oscillator Divider 1 Register (OSCDIV)
............................................................
PLLC1 Oscillator Divider 1 Register (OSCDIV)
............................................................
PLL Post-Divider Control Register (POSTDIV)
............................................................
PLL Controller Command Register (PLLCMD)
............................................................
PLL Controller Status Register (PLLSTAT)
................................................................
PLLC0 Clock Align Control Register (ALNCTL)
...........................................................
PLLC1 Clock Align Control Register (ALNCTL)
...........................................................
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE)
............................................
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE)
............................................
PLLC0 Clock Enable Control Register (CKEN)
............................................................
PLLC1 Clock Enable Control Register (CKEN)
............................................................
PLLC0 Clock Status Register (CKSTAT)
...................................................................
PLLC1 Clock Status Register (CKSTAT)
...................................................................
PLLC0 SYSCLK Status Register (SYSTAT)
...............................................................
PLLC1 SYSCLK Status Register (SYSTAT)
...............................................................
Emulation Performance Counter 0 Register (EMUCNT0)
................................................
Emulation Performance Counter 1 Register (EMUCNT1)
................................................
161
162
162
163
163
164
164
165
165
166
166
167
167
168
168
169
170
171
172
173
174
174
175
176
177
178
179
179
182
182
184
185
187
187
187
188
188
188
189
190
191
192
192
193
193
194
194
195
195
196
197
198
5
9
Power and Sleep Controller (PSC)
.....................................................................................
181
9.1
9.2
Introduction
...............................................................................................................
Power Domain and Module Topology
.................................................................................
9.2.1 Power Domain States
..........................................................................................
9.2.2 Module States
...................................................................................................
Executing State Transitions
............................................................................................
9.3.1 Power Domain State Transitions
..............................................................................
9.3.2 Module State Transitions
.......................................................................................
IcePick Emulation Support in the PSC
................................................................................
PSC Interrupts
............................................................................................................
9.5.1 Interrupt Events
.................................................................................................
9.5.2 Interrupt Registers
..............................................................................................
9.5.3 Interrupt Handling
...............................................................................................
PSC Registers
............................................................................................................
9.6.1 Revision Identification Register (REVID)
....................................................................
9.6.2 Interrupt Evaluation Register (INTEVAL)
....................................................................
9.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0)
..................................
9.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0)
..................................
9.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0)
......................................
9.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0)
......................................
9.6.7 Power Error Pending Register (PERRPR)
...................................................................
9.6.8 Power Error Clear Register (PERRCR)
......................................................................
9.6.9 Power Domain Transition Command Register (PTCMD)
..................................................
9.6.10 Power Domain Transition Status Register (PTSTAT)
.....................................................
9.6.11 Power Domain 0 Status Register (PDSTAT0)
.............................................................
Contents
Copyright
©
2011, Texas Instruments Incorporated
9.3
9.4
9.5
9.6
SPRUH77
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August 2011
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