Avago’s ATF-34143 is a high dynamic range, low noise
PHEMT housed in a 4-lead SC-70 (SOT-343) surface mount
plastic package.
Based on its featured performance, ATF-34143 is ideal for
the first stage of base station LNA due to the excellent
combination of low noise figure and high linearity
[1]
. The
device is also suitable for applications in Wireless LAN,
WLL/RLL, MMDS, and other systems requiring super low
noise figure with good intercept in the 450 MHz to 10 GHz
frequency range.
Note:
1. From the same PHEMT FET family, the larger geometry ATF-33143
may also be considered either for the higher linearity performance
or easier circuit design for stability in the lower frequency bands
(800– 900 MHz).
Features
Lead-free Option Available
Low Noise Figure
Excellent Uniformity in Product Specifications
800 micron Gate Width
Low Cost Surface Mount Small Plastic Package
SOT-343 (4 lead SC-70)
Tape-and-Reel Packaging Option Available
Specifications
1.9 GHz; 4V, 60 mA (Typ.)
0.5 dB Noise Figure
17.5 dB Associated Gain
20 dBm Output Power at 1 dB Gain Compression
31.5 dBm Output 3
rd
Order Intercept
Surface Mount Package - SOT-343
Applications
Tower Mounted Amplifier and Low Noise Amplifier
for GSM/TDMA/CDMA Base Stations
LNA for Wireless LAN, WLL/RLL and MMDS
Applications
Pin Connections and Package Marking
DRAIN
SOURCE
General Purpose Discrete PHEMT for other Ultra Low
Noise Applications
SOURCE
GATE
Note:
Top View. Package marking provides
orientation and identification.
“4P” = Device code
“x” = Date code character. A new character
is assigned for each month, year.
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model (Class A)
ESD Human Body Model (Class 0)
Refer to Avago Application Note A004R:
Electrostatic Discharge Damage and Control.
4Px
ATF-34143 Absolute Maximum Ratings
[1]
Symbol
V
DS
V
GS
V
GD
I
D
P
diss
P
in max
T
CH
T
STG
jc
Parameter
Drain - Source Voltage
[2]
Gate - Source Voltage
[2]
Gate Drain Voltage
[2]
Drain Current
[2]
Total Power Dissipation
[4]
RF Input Power
Channel Temperature
Storage Temperature
Thermal Resistance
[5]
Units
V
V
V
mA
mW
dBm
°C
°C
°C/W
Absolute
Maximum
5.5
-5
-5
I
dss [3]
725
17
160
-65 to 160
165
Notes:
1. Operation of this device above any one of
these parameters may cause permanent
damage.
2. Assumes DC quiescent conditions.
3. V
GS
= 0 volts.
4. Source lead temperature is 25°C. Derate
6 mW/°C for T
L
> 40°C.
5. Thermal resistance measured using 150°C
Liquid Crystal Measurement method.
6. Under large signal conditions, V
GS
may
swing positive and the drain current may
exceed I
dss
. These conditions are acceptable
as long as the maximum P
diss
and P
in max
ratings are not exceeded.
Product Consistency Distribution Charts
[7]
250
+0.6 V
120
100
80
200
Cpk = 1.37245
Std = 0.66
9 Wafers
Sample Size = 450
I
DS
(mA)
150
0V
-3 Std
60
40
+3 Std
100
50
–0.6 V
20
0
0
0
2
4
V
DS
(V)
6
8
29
30
31
32
OIP3 (dBm)
33
34
35
Figure 1. Typical/Pulsed I-V Curves
[6]
.
(V
GS
= -0.2 V per step)
120
100
80
Cpk = 2.69167
Std = 0.04
9 Wafers
Sample Size = 450
Figure 2. OIP3 @ 2 GHz, 4†V, 60 mA.
LSL=29.0, Nominal=31.8, USL=35.0
120
100
80
Cpk = 2.99973
Std = 0.15
9 Wafers
Sample Size = 450
-3 Std
60
40
20
0
0
0.2
0.4
NF (dB)
+3 Std
60
40
20
0
0.6
0.8
16
16.5
-3 Std
+3 Std
17
17.5
GAIN (dB)
18
18.5
19
Figure 3. NF @ 2 GHz, 4†V, 60 mA.
LSL=0.1, Nominal=0.47, USL=0.8
Figure 4. Gain @ 2 GHz, 4†V, 60 mA.
LSL=16.0, Nominal=17.5, USL=19.0
Notes:
7. Distribution data sample size is 450 samples taken from 9 different wafers. Future wafers allocated to this product may have nominal values
anywhere within the upper and lower spec limits.
8. Measurements made on production test board. This circuit represents a trade-off between an optimal noise match and a realizeable match based
on production test requirements. Circuit losses have been de-embedded from actual measurements.
2
ATF-34143 Electrical Specifications
T
A
= 25°C, RF parameters measured in a test circuit for a typical device
Symbol
Parameters and Test Conditions
I
dss [1]
V
P [1]
I
d
g
m[1]
I
GDO
I
gss
NF
Saturated Drain Current
Pinchoff Voltage
Quiescent Bias Current
Transconductance
Gate to Drain Leakage Current
Gate Leakage Current
Noise Figure
f = 2 GHz
f = 900 MHz
G
a
Associated Gain
f = 2 GHz
f = 900 MHz
OIP3
Output 3
rd
Order
Intercept Point
[3]
f = 2 GHz
+5 dBm P
out
/Tone
f = 900 MHz
+5 dBm P
out
/Tone
P
1dB
1 dB Compressed
Intercept Point
[3]
f = 2 GHz
f = 900 MHz
Notes:
1. Guaranteed at wafer probe level
2. Typical value determined from a sample size of 450 parts from 9 wafers.
3. Using production test board.
Units
mA
V
mA
mmho
μA
μA
dB
dB
dB
dB
dBm
dBm
dBm
dBm
Min.
90
-0.65
—
180
Typ.
[2]
118
-0.5
60
230
Max.
145
-0.35
—
—
500
V
DS
= 1.5 V, V
GS
= 0 V
V
DS
= 1.5 V, I
DS
= 10% of I
dss
V
GS
= -0.34 V, V
DS
= 4 V
V
DS
= 1.5 V, g
m
= I
dss
/V
P
V
GD
= 5 V
V
GD
= V
GS
= -4 V
V
DS
= 4 V, I
DS
= 60 mA
V
DS
= 4 V, I
DS
= 30 mA
V
DS
= 4 V, I
DS
= 60 mA
V
DS
= 4 V, I
DS
= 60 mA
V
DS
= 4 V, I
DS
= 30 mA
V
DS
= 4 V, I
DS
= 60 mA
V
DS
= 4 V, I
DS
= 60 mA
V
DS
= 4 V, I
DS
= 30 mA
V
DS
= 4 V, I
DS
= 60 mA
V
DS
= 4 V, I
DS
= 60 mA
V
DS
= 4 V, I
DS
= 30 mA
V
DS
= 4 V, I
DS
= 60 mA
—
30
0.5
0.5
0.4
300
0.8
16
17.5
17
21.5
19
29
31.5
30
31
20
19
18.5
Input
50 Ohm
Transmission
Line Including
Gate Bias T
(0.5 dB loss)
Input
Matching Circuit
Γ_mag
= 0.30
Γ_ang
= 56°
(0.4 dB loss)
DUT
50 Ohm
Transmission
Line Including
Drain Bias T
(0.5 dB loss)
Output
Figure 5. Block diagram of 2 GHz production test board used for Noise Figure, Associated Gain, P1dB, and OIP3 measurements. This circuit represents a trade-off
between an optimal noise match and associated impedance matching circuit losses. Circuit losses have been de-embedded from actual measurements.
3
ATF-34143 Typical Performance Curves
35
30
ASSOCIATED GAIN (dB)
NOISE FIGURE (dB)
25
OIP3, P
1dB
(dBm)
20
15
10
5
0
0
20
40
60
80
100
P
1dB
3V
4V
OIP3
20
1
0.8
0.6
0.4
0.2
0
15
10
5
3V
4V
3V
4V
120
140
0
0
20
40
60
CURRENT (mA)
80
100
120
0
20
40
60
CURRENT (mA)
80
100
120
I
DSQ
(mA)
Figure 6. OIP3 and P
1dB
vs. I
DS
and V
DS
Tuned for NF @
4 V, 60 mA at 2 GHz.
[1,2]
35
30
Figure 7. Associated Gain vs. Current (I
d
) and Voltage
(V
D
) at 2 GHz.
[1,2]
25
20
ASSOCIATED GAIN (dB)
15
10
5
0
Figure 8. Noise Figure vs. Current (I
d
) and Voltage
(V
DS
) at 2 GHz.
[1,2]
0.7
0.6
NOISE FIGURE (dB)
0.5
0.4
0.3
0.2
OIP3
25
OIP3, P
1dB
(dBm)
20
15
10
5
0
0
20
40
60
I
DSQ
(mA)
80
3V
4V
P
1dB
3V
4V
0.1
120
0
0
20
40
60
CURRENT (mA)
80
3V
4V
100
120
0
20
40
60
CURRENT (mA)
80
100
100
120
Figure 9. OIP3 and P
1dB
vs. I
DS
and V
DS
Tuned for NF @
4 V, 60 mA at 900 MHz.
[1,2]
Figure 10. Associated Gain vs. Current (I
d
) and Voltage
(V
D
) at 900 MHz.
[1,2]
25
Figure 11. Noise Figure vs. Current (I
d
) and Voltage
(V
DS
) at 900 MHz.
[1,2]
1.2
1.0
20
0.8
Fmin (dB)
0.6
0.4
0.2
0
60 mA
40 mA
20 mA
G
a
(dB)
15
10
60 mA
40 mA
20 mA
0
2.0
4.0
6.0
5
0
1.0
2.0
3.0
4.0
5.0
6.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 12. Fmin vs. Frequency and Current at 4 V.
Notes:
Figure 13. Associated Gain vs. Frequency and Current
at 4 V.
1. Measurements made on a fixed toned production test board that was tuned for optimal gain match with reasonable noise figure at 4V, 60 mA
bias. This circuit represents a trade-off between optimal noise match, maximum gain match, and a realizable match based on production test
board requirements. Circuit losses have been de-embedded from actual measurements.
2. P
1dB
measurements are performed with passive biasing. Quicescent drain current, I
DSQ
, is set with zero RF drive applied. As P
1dB
is approached,
the drain current may increase or decrease depending on frequency and dc bias point. At lower values of I
DSQ
the device is running closer to class
B as power output approaches P
1dB
. This results in higher PAE (power added efficiency) when compared to a device that is driven by a constant
current source as is typically done with active biasing. As an example, at a V
DS
= 4 V and I
DSQ
= 10 mA, I
d
increases to 62 mA as a P
1dB
of +19 dBm
is approached.
4
ATF-34143 Typical Performance Curves, continued
25
85 C
25 C
-40 C
1.5
33
31
GAIN (dB), OP1dB, and OIP3 (dBm)
29
P1dB, OIP3 (dBm)
35
30
25
20
15
10
5
0
2000
4000
FREQUENCY (MHz)
6000
8000
0
0
20
40
60
80
100
120
140
Gain
OP1dB
OIP3
NF
5.0
4.5
4.0
3.0
2.5
2.0
1.5
1.0
0.5
0
NOISE FIGURE (dB)
3.5
20
G
a
(dB)
1.0
NF (dB)
27
25
23
21
19
OIP3
85 C
25 C
-40 C
P
1dB
15
0.5
10
0
2000
4000
FREQUENCY (GHz)
6000
0
8000
17
I
DSQ
(mA)
Figure 14. Fmin and G
a
vs. Frequency and Temperature
at V
DS
= 4 V, I
DS
= 60 mA.
30
27
GAIN (dB), OP1dB, and OIP3 (dBm)
24
21
18
15
12
9
6
3
0
0
20
40
60
I
DSQ
(mA)
80
100
120
Gain
OP1dB
OIP3
NF
Figure 15. P
1dB
, IP3 vs. Frequency and Temperature at V
DS
= 4 V, I
DS
= 60 mA.
[1]
25
20
NOISE FIGURE (dB)
15
P
1dB
(dBm)
10
5
0
-5
3V
4V
Figure 16. NF, Gain, OP1dB and OIP3 vs. I
DS
at 4 V and
3.9 GHz Tuned for Noise Figure.
[1]
25
20
15
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
P
1dB
(dBm)
10
5
0
-5
3V
4V
0
50
I
DS
(mA)
100
150
0
50
I
DS
(mA)
100
150
Figure 17. NF, Gain, OP1dB and OIP3 vs. I
DS
at 4 V and
5.8 GHz Tuned for Noise Figure.
[1]
Figure 18. P
1dB
vs. I
DS
Active Bias Tuned for NF @ 4V, 60
mA at 2 GHz.
Figure 19. P
1dB
vs. I
DS
Active Bias Tuned for min NF @
4V, 60 mA at 900 MHz.
Note:
1. P
1dB
measurements are performed with passive biasing. Quicescent drain current, I
DSQ
, is set with zero RF drive applied. As P
1dB
is approached,
the drain current may increase or decrease depending on frequency and dc bias point. At lower values of I
DSQ
the device is running closer to class
B as power output approaches P
1dB
. This results in higher PAE (power added efficiency) when compared to a device that is driven by a constant
current source as is typically done with active biasing. As an example, at a V
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