Preliminary Technical Data
FEATURES
SNR = 71.7 dBc (72.7dBFS) to 70 MHz @ 150 MSPS
SFDR = 85 dBc to 70 MHz @ 150 MSPS
Low Power: 780 mW
1.8V analog supply operation
1.8V to 3.3V CMOS output supply or 1.8V LVDS supply
Integer 1 to 8 Input Clock Divider
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input: 1 V p-p to 2 V p-p range
Differential analog inputs with 650MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial Port Control
User-configurable built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated Receive Features:
Fast Detect/Threshold Bits
Composite Signal monitor
14-Bit, 80/105/125/150 MSPS, 1.8 V
Dual Analog-to-Digital Converter
AD9640
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers:
GSM, EDGE, PHS, UMTS, WCDMA, CDMA-ONE,
IS95, CDMA2000, IMT-2000, WiMax
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
FUNCTIONAL BLOCK DIAGRAM
Figure 1. AD9640 Functional Block Diagram
Rev. PrD
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AD9640
TABLE OF CONTENTS
General Description ......................................................................... 4
Product Highlights ....................................................................... 4
Specifications..................................................................................... 5
ADC DC Specifications ............................................................... 5
ADC AC Specifications ............................................................... 6
Digital specifications.................................................................... 7
switching specifications ............................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Characteristics .............................................................. 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Equivalent circuits .......................................................................... 13
Typical Performance Characteristics ........................................... 14
Timing Diagrams............................................................................ 15
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
ADC Architecture ...................................................................... 17
Analog Input Considerations.................................................... 17
Voltage Reference ....................................................................... 19
Clock Input Considerations ...................................................... 20
Power Dissipation and Standby Mode..................................... 22
Digital Outputs ........................................................................... 22
Timing.......................................................................................... 23
ADC OVERRANGE and GaIN control ...................................... 24
Fast detect overview ................................................................... 24
ADC Fast Magnitude ................................................................. 24
ADC overrange (OVR).............................................................. 25
Preliminary Technical Data
Gain Switching............................................................................ 25
SIGNAL Monitor............................................................................ 27
Peak Detector Mode (Mode Bits 01) ....................................... 27
RMS/MS Magnitude Mode (Mode Bits 00)............................ 27
Threshold Crossing Mode (Mode Bits 1x).............................. 28
Additional Control Bits ............................................................. 28
DC Correction ............................................................................ 29
Signal monitor SPORT OUTPUT............................................ 29
Built-In Self-Test (BIST) and Output test ................................... 30
Built in self test (BIST)............................................................... 30
output test modes ....................................................................... 30
Channel/Chip Synchronization.................................................... 31
Serial Port Interface (SPI).............................................................. 32
Configuration Using the SPI..................................................... 32
Hardware Interface..................................................................... 32
Configuration WITHOUT the SPI.......................................... 33
Memory Map .............................................................................. 33
SPI Accessible Features.............................................................. 33
External memory MaP................................................................... 35
memory map register description............................................ 38
Applications..................................................................................... 39
Design Guidelines ...................................................................... 39
AD9640 Evaluation Board and Software..................................... 40
Outline Dimensions ....................................................................... 41
Ordering Guide .......................................................................... 41
Rev. PrD | Page 2 of 41
Preliminary Technical Data
REVISION HISTORY
12/06—Revision PrD:
9/06—Revision PrC:
8/06—Revision PrB: Preliminary Version
AD9640
Rev. PrD | Page 3 of 41
AD9640
GENERAL DESCRIPTION
The AD9640 is a dual 14-Bit 150 MSPS ADC. The AD9640 is
designed to support communications applications where low
cost, small size, and versatility are desired.
The dual ADC core features a multistage differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth differential sample-and-hold
analog input amplifiers supporting a variety of user-selectable
input ranges. An integrated voltage reference eases design
considerations. A duty cycle stabilizer is provided to compen-
sate for variations in the ADC clock duty cycle, allowing the
converters to maintain excellent performance.
The AD9640 has several functions which simply the AGC
function in the system receiver. The fast detect feature allows
fast overrange detection by outputting 4 bits of input level
information with very short latency. Additionally, the
programmable threshold detector allows monitoring of the
incoming signal power from the ADC’s 4 fast detect bits with
very low latency. If the input signal level exceeds the
programmable threshold, the decrement gain indicator will go
high. Because this threshold is set from the 4 MSB’s this allows
the user to quickly turn down the system gain to avoid an
overrange condition. The second AGC related function is the
Signal monitor. This block allows the user to monitor the
composite magnitude of the incoming signal which aids in
setting the gain to optimize the dynamic range of the overall
system.
The ADC output data can be routed directly to the two external
Preliminary Technical Data
14-bit output ports. These outputs can be set from 1.8V to
3.3V CMOS. Or 1.8V LVDS.
Flexible power-down options allow significant power savings,
when desired.
PRODUCT HIGHLIGHTS
•
•
•
•
•
Integrated dual 14-Bit 150 MSPS ADC.
Fast Over-range Detect and Signal monitor with Serial
Output
Signal monitor block with dedicate serial output mode.
Proprietary, differential input maintains excellent SNR
performance for input frequencies up to 450 MHz.
The AD9640 operates from a single 1.8 Volt supply and
features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or gray coding), enabling the
clock DCS, power-down, and voltage reference mode.
The AD9640 is pin compatible with the AD9627, allowing
a simple migration from 12 to 14 Bits.
•
•
Rev. PrD | Page 4 of 41
Preliminary Technical Data
SPECIFICATIONS
ADC DC SPECIFICATIONS
AD9640
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, Fast Detect Outputs disabled, Signal Monitor disabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential
Nonlinearity (DNL)
1
Integral Nonlinearity
(INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE
REFERENCE
Output Voltage Error
(1 V Mode)
Load Regulation @ 1.0
mA
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0
V
Input Capacitance
2
VREF INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD, DVDD
DRVDD (CMOS
Mode)
Supply Current
IAVDD
IDVDD
IDRVDD (3.3V)
IDRVDD (1.8V)
PSRR
POWER CONSUMPTION
DC Input
Sine Wave Input
(DRVDD=1.8V)
Sine Wave Input
(DRVDD=3.3V)
Standby Power
3
Powerdown Power
Temp
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
AD9640BCPZ-80
Min
Typ
Max
14
Guaranteed
±0.3
±2.0
AD9640BCPZ-105
Min
Typ
Max
14
Guaranteed
±0.3
±TBD
±2.0
±TBD
±0.4
±TBD
±2
±15
±95
±1.8
±15
±95
±TBD
±2
±15
±95
AD9640BCPZ-125
Min
Typ
Max
14
Guaranteed
±0.3
±TBD
±1.7
±TBD
±0.4
±TBD
±2
±15
±95
AD9640BCPZ-150
Min
Typ
Max
14
Guaranteed
±0.3
±1.7
Unit
Bits
±TBD
±TBD
±TBD
±TBD
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
±0.4
±0.4
±TBD
Full
Full
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mV
mV
25°C
Full
Full
Full
TBD
2
8
6
TBD
2
8
6
TBD
2
8
6
TBD
2
8
6
LSB rms
V p-p
pF
kΩ
Full
Full
1.7
1.7
1.8
3.3
1.9
3.6
1.7
1.7
1.8
3.3
1.9
3.6
1.7
1.7
1.8
3.3
1.9
3.6
1.7
1.7
1.8
3.3
1.9
3.6
V
V
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
219
29
30
TBD
±0.01
TBD
TBD
546
TBD
TBD
292
37
39
TBD
±0.01
TBD
TBD
721
TBD
TBD
363
45
47
TBD
±0.01
TBD
TBD
890
TBD
TBD
384
47.5
53.3
TBD
±0.01
TBD
TBD
953
TBD
TBD
mA
mA
mA
mA
% FSR
mW
mW
mW
mW
mW
1
2
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure x for the equivalent analog input structure.
3
Standby power is measured with a dc input, the CLK pins inactive (set to AVDD or AGND).
Rev. PrD | Page 5 of 41
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