提出一种新的WEP 协议中RC4 算法硬件设计方法，算法的KSA 和PRGA 两个步骤共用同一硬件电路，每生成1 个KSA 状态和每产生1 字节PRGA 数据流都只需要3 个时钟周期。该方法具有设计简单、密匙长度动态可选、在加密/解密相同长度数据下所需的执行时间较少的优点，功能仿真结果表明了设计的正确性。关键字：WEP 协议 RC4 算法 VHDL MAX+plusⅡAbstract:A new hardware design of RC4 algorithm in WEP is developed. In the scheme, the time to generate a KSA stage and the time to generate one byte PRGA data stream both need only three clock period. The scheme shows superior characteristics for its simple design and variable length key input, and it has fewer executing time when encrypting or decrypting equal length data. At last, result of functional simulation is given.Keywords: WEP protocol RC4 algorithm VHDL MAX+plusⅡ
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