PCI
®
Express
Basics
Richard Solomon
LSI Corporation
Copyright © 2009, PCI-SIG, All Rights Reserved
1
Acknowledgements
I would like to acknowledge the contributions of
Ravi Budruk, Mindshare, Inc.
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PCI
®
Express
Introduction
PCI Express architecture is a high performance, IO
interconnect for peripherals in
computing/communication platforms
Evolved from PCI
TM
and PCI-X
TM
architectures
Yet PCI Express architecture is significantly different from its
predecessors PCI and PCI-X
PCI Express is a serial point-to-point interconnect
between two devices
Implements packet based protocol for information
transfer
Scalable performance based on number of signal
Lanes implemented on the PCI Express interconnect
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PCI Express Terminology
PCI Express Device A
Signal
Wire
Link
Lane
PCI Express Device B
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PCI Express Throughput
Link Width
x1
PCIe 1.x BW (GB/s)
PCIe 2.0 BW (GB/s)
0.5
1
x2
1
2
x4
2
4
x8
4
8
x12
6
12
x16
8
16
x32
16
32
Derivation of these numbers:
2.5 GT/s (PCIe 1.x) or 5.0 GT/s (PCIe 2.0) signaling in
each direction
20% overhead due to 8b/10b encoding
Bandwidth described as “aggregate”, implying
simultaneous traffic in both directions
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