www.fairchildsemi.com
AN-6076
Design and Application Guide of Bootstrap Circuit for
High-Voltage Gate-Drive IC
1. Introduction
The purpose of this paper is to demonstrate a systematic
approach to design high-performance bootstrap gate drive
circuits for high-frequency, high-power, and high-efficiency
switching applications using a power MOSFET and IGBT.
It should be of interest to power electronics engineers at all
levels of experience. In the most of switching applications,
efficiency focuses on switching losses that are mainly depen-
dent on switching speed. Therefore, the switching character-
istics are very important in most of the high-power switching
applications presented in this paper. One of the most widely
used methods to supply power to the high-side gate drive cir-
cuitry of the high-voltage gate-drive IC is the bootstrap
power supply. This bootstrap power supply technique has the
advantage of being simple and low cost. However, it has
some limitations, on time of duty-cycle is limited by the
requirement to refresh the charge in the bootstrap capacitor
and serious problems occur when the negative voltage is pre-
sented at the source of the switching device. The most popu-
lar bootstrap circuit solutions are analyzed; including the
effects of parasitic elements, the bootstrap resistor, and
capacitor; on the charge of the floating supply application.
unique level-shift design. To maintain high efficiency and
manageable power dissipation, the level-shifters should not
draw any current during the on-time of the main switch.
A widely used technique for these applications is called
pulsed latch level translators, shown in Figure 1.
V
B
UVLO
PULSE GENERATOR
Shoot-through current
compensated gate driver
IN
NOISE
CANCELLER
R
S
R
Q
HO
V
S
Figure 1. Level-Shifter in High-Side Drive IC
2.2 Bootstrap Drive Circuit Operation
The bootstrap circuit is useful in a high-voltage gate driver
and operates as follows. When the V
S
goes below the IC
supply voltage V
DD
or is pulled down to ground (the low-
side switch is turned on and the high-side switch is turned
off), the bootstrap capacitor, C
BOOT
, charges through the
bootstrap resistor, R
BOOT
, and bootstrap diode, D
BOOT
, from
the V
DD
power supply, as shown in Figure 2. This is pro-
vided by V
BS
when V
S
is pulled to a higher voltage by the
high-side switch, the V
BS
supply floats and the bootstrap
diode reverses bias and blocks the rail voltage (the low-side
switch is turned off and high-side switch is turned on) from
the IC supply voltage, V
DD
.
R
BOOT
D
BOOT
2. High-Speed Gate-Driver Circuitry
2.1 Bootstrap Gate-Drive Technique
The focus of this topic is the bootstrap gate-drive circuit
requirements of the power MOSFET and IGBT in various
switching-mode power-conversion applications. Where
input voltage levels prohibit the use of direct-gate drive cir-
cuits for high-side N-channel power MOSFET or IGBT, the
principle of bootstrap gate-drive technique can be consid-
ered. This method is utilized as a gate drive and accompany-
ing bias circuit, both referenced to the source of the main
switching device. Both the driver and bias circuit swing
between the two input voltage rails together with the source
of the device. However, the driver and its floating bias can
be implemented by low-voltage circuit elements since the
input voltage is never applied across their components. The
driver and the ground referenced control signal are linked by
a level shift circuit that must tolerate the high-voltage differ-
ence and considerable capacitive switching currents between
the floating high-side and ground-referenced low-side cir-
cuits. The high-voltage gate-drive ICs are differentiated by
© 2008 Fairchild Semiconductor Corporation
Rev. 1.4
•
12/18/14
DC SUPPLY
Bootstrap charge current path
Bootstrap discharge current path
V
B
RG1
V
DD
HO
C
BOOT
Q1
I
LOAD
V
DD
V
S
LOAD
RG2
Q2
COM
LO
Figure 2. Bootstrap Power Supply Circuit
www.fairchildsemi.com
AN-6076
APPLICATION NOTE
2.3 Drawback of Bootstrap Circuitry
The bootstrap circuit has the advantage of being simple and
low cost, but has some limitations.
Duty-cycle and on time is limited by the requirement to
refresh the charge in the bootstrap capacitor, C
BOOT
.
The biggest difficulty with this circuit is that the negative
voltage present at the source of the switching device during
turn-off causes load current to suddenly flow in the low-side
freewheeling diode, as shown in Figure 3.
This negative voltage can be trouble for the gate driver’s out-
put stage because it directly affects the source V
S
pin of the
driver or PWM control IC and might pull some of the inter-
nal circuitry significantly below ground, as shown in Figure
4. The other problem caused by the negative voltage tran-
sient is the possibility to develop an over-voltage condition
across the bootstrap capacitor.
The bootstrap capacitor, C
BOOT
, is peak charged by the boot-
strap diode, D
BOOT
, from V
DD
the power source.
Since the V
DD
power source is referenced to ground, the
maximum voltage that can build on the bootstrap capacitor is
the sum of V
DD
and the amplitude of the negative voltage at
the source terminal.
2.4 Cause of Negative Voltage on V
S
Pin
A well-known event that triggers V
S
go below COM
(ground) is the forward biasing of the low-side freewheeling
diode, as shown in Figure 5.
Major issues may appear during commutation, just before
the freewheeling diode starts clamping.
In this case, the inductive parasitic elements, LS1 and LS2,
may push V
S
below COM, more than as described above or
normal steady-state condition.
The amplitude of negative voltage is proportional to the par-
asitic inductances and the turn-off speed, di/dt, of the switch-
ing device; as determined by the gate drive resistor, R
GATE
,
and input capacitance, C
iss
, of switching device.
It is sum of C
gs
and C
gd
, called Miller capacitance.
V
CC
D
BOOT
V
DC
INPUT
IN
V
B
C
BOOT
Q1
B
R
GATE
L
S1
GND
V
S
C
L
S2
R
BOOT
D
BOOT
GND
- V
S
HVIC
V
DD
C
DRV
HO
A
i
LOAD
C
i
Free
DC SUPPLY
C
OUT
V
OUT
D1
VB
RG1
VDD
HIN
LIN
C
IN
HO
C
BOOT
Ls1
Q1
High Side OFF
Figure 5. Step-Down Converter Applications
HIN
LIN
VS
i
Load
Ls2
RG2
i
free
Q2
Freewheeling Path
Figure 6 shows the waveforms of the high-side, N-channel
MOSFET during turn-off.
COM
LO
Figure 3. Half-Bridge Application Circuits
A-Point
V
BS
HIN
B-Point
V
DC
+V
GS,Miller
t
C-Point
V
DC
V
S
-COM
t
-V
S
Freewheeling
Recovery Time
V
GS
=B-C Point
Figure 4. V
S
Waveforms During Turn-off
Figure 6. Waveforms During Turn-off
www.fairchildsemi.com
2
© 2008 Fairchild Semiconductor Corporation
Rev. 1.4 • 12/18/14
AN-6076
APPLICATION NOTE
2.5 Effects in the Undershoot Spike on V
S
Pin
If undershoot exceeds the absolute maximum rating speci-
fied in the datasheet, the gate drive IC suffers damage or the
high-side output is temporarily unresponsive to input transi-
tion as shown in Figure 7 and Figure 8.
Figure 7 shows Latch-up case that the high-side output does
not changed by input signal. In this case, short-circuit condi-
tion occur on external, main, high-side and low-side
switches in half-bridge topology.
2.6 Consideration of Latch-up Problem
The most integrated high-voltage gate-drive ICs have para-
sitic diodes, which, in forward or reverse break-down, may
cause parasitic SCR latch-up. The ultimate outcome of latch-
up often defies prediction and can range from temporary
erratic operation to total device failure. The gate-drive IC
may also be damaged indirectly by a chain of events follow-
ing initial overstress. For example, latch-up could conceiv-
ably result in both output drivers assuming a HIGH state,
causing cross-conduction followed by switch failure and,
finally, catastrophic damage to the gate-drive IC. This failure
mode should be considered a possible root-cause, if power
transistors and/or gate-drive IC are destroyed in the applica-
tion. The following theoretical extremes can be used to help
explain the relationships between excessive V
S
undershoot
and the resulting latch-up mechanism.
In the first case, an "ideal bootstrap circuit" is used in which
V
DD
is driven from a zero-ohm supply with an ideal diode
feed V
B
, as shown in Figure 9. When the high current flow-
ing through freewheeling diode, V
S
voltage is below ground
level by high di/dt. This time, latch-up risk appears since
internal parasitic diode, D
BS
of the gate driver ultimately
enters conduction from V
S
to V
B
, causing the undershoot
voltage to sum with V
DD
, causing the bootstrap capacitor to
overcharge, as shown Figure 10.
For example,
if V
DD
=15 V, then V
S
undershoot in excess of
10V forces the floating supply above 25 V, risking break-
down in diode D
BS
and subsequent latch-up.
INPUT
OUTPUT
Latch-Up Problem
Figure 7. Waveforms in Case of Latch-up
Figure 8 shows Missing case that the high-side output does
not responded to input transition. In this case, the level
shifter of the high-side gate driver suffers form a lack of the
operation voltage headroom. This should be noted, but
proves trivial in most applications, as the high-side in not
usually required to change state immediately following a
switching event.
V
DD
V
B
D
BS
COM
V
S
Gate Driver
INPUT
Figure 9. Case 1: Ideal Bootstrap Circuits
V
B
V
S
OUTPUT
Signal Missing Problem
HIGH V
BS
GND
Figure 8. Waveforms in Case of Signal Missing
Figure 10. V
B
and V
S
Waveforms of Case 1
© 2008 Fairchild Semiconductor Corporation
Rev. 1.4 • 12/18/14
www.fairchildsemi.com
3
AN-6076
APPLICATION NOTE
Suppose that the bootstrap supply is replaced with the ideal
floating supply, as shown in Figure 11, such that V
BS
is fixed
under all circumstances. Note that using a low impedance
auxiliary supply in place of a bootstrap circuit can approach
this situation. This time, latch-up risk appears if V
S
under-
shoot exceeds the V
BS
maximum specified in datasheet,
since parasitic diode D
BCOM
ultimately enters conduction
from COM to V
B
, as shown in Figure 12.
2.7 Effect of Parasitic Inductances
The amplitude of negative voltage is:
V
S
−
COM
= −
(
V
RBOOT
+
V
FDBOOT
)
−
(
L
S
1
+
L
S
2
)
di dt
(1)
To reduce the slope of current flowing in the parasitic induc-
tances to minimize the derivative terms in Equation 1.
For example,
if a 10 A, 25 V gate driver with 100nH para-
sitic inductance switches in 50 ns, the negative voltage spike
between V
S
and ground is 20 V.
V
CC
V
B
V
CC
D
BCOM
3. Design Procedure of Bootstrap
Components
3.1 Select the Bootstrap Capacitor
The bootstrap capacitor (C
BOOT
) is charged every time the
low-side driver is on and the output pin is below the supply
voltage (V
DD
) of the gate driver. The bootstrap capacitor is
discharged only when the high-side switch is turned on. This
bootstrap capacitor is the supply voltage (V
BS
) for the high
circuit section. The first parameter to take into account is the
maximum voltage drop that we have to guarantee when the
high-side switch is in on state. The maximum allowable volt-
age drop (V
BOOT
) depends on the minimum gate drive volt-
age (for the high-side switch) to maintain. If V
GSMIN
is the
minimum gate-source voltage, the capacitor drop must be:
Δ
V
BOOT
=
V
DD
−
V
F
−
V
GSMIN
(2)
COM
V
S
Gate Driver
Figure 11. Case 2: Ideal Floating Supply
V
B
V
S
V
B
Below COM
GND
Figure 12. V
B
and V
S
Waveforms of Case 2
where:
V
DD
= Supply voltage of gate driver [V]; and
V
F
= Bootstrap diode forward voltage drop [V]
The value of bootstrap capacitor is calculated by:
C
BOOT
=
Q
TOTAL
Δ
V
BOOT
A practical circuit is likely to fall somewhere between these
two extremes, resulting in both a small increase of V
BS
and
some V
B
droop below V
DD
, as shown in Figure 13.
V
B
V
S
(3)
where Q
TOTAL
is the total amount of the charge supplied by
the capacitor.
V
B
close to COM
GND
The total charge supplied by the bootstrap capacitor is calcu-
lated by equation 4.:
Q
TOTAL
=
Q
GATE
+
(
I
LKCAP
+
I
LKGS
+
I
QBS
+
I
LK
+
I
LKDIODE
⋅
t
ON
+
Q
LS
(4)
)
Increased V
BS
Figure 13. Typical Response of V
B
and V
S
where:
Q
GATE
= Total gate charge;
I
LKGS
= Switch gate-source leakage current;
I
LKCAP
= Bootstrap capacitor leakage current;
I
QBS
= Bootstrap circuit quiescent current;
I
LK
= Bootstrap circuit leakage current;
Q
LS
= Charge required by the internal level shifter, which is
set to 3 nC for all HV gate drivers;
t
ON
= High-side switch on time; and
www.fairchildsemi.com
4
Exactly which of the two extremes is prevalent can be
checked as follows. If the V
S
pins undershoot spike has a
time length that is on order of tenths of nanoseconds; the
bootstrap capacitor, C
BOOT
, can become overcharged and the
high-side gate-driver circuit has damage by over-voltage
stress because it exceeds an absolute maximum voltage
(V
BSMAX
) specified in datasheet. Design to a bootstrap cir-
cuit, that does not exceed the absolute maximum rating of
high-side gate driver.
© 2008 Fairchild Semiconductor Corporation
Rev. 1.4 • 12/18/14
AN-6076
APPLICATION NOTE
I
LKDIODED
= Bootstrap diode leakage current.
The capacitor leakage current is important only if an electro-
lytic capacitor is used; otherwise, this can be neglected.
For example:
Evaluate the bootstrap capacitor value when
the external bootstrap diode used.
Gate Drive IC = FAN7382 (Fairchild)
Switching Device = FCP20N60 (Fairchild)
Bootstrap Diode = UF4007
V
DD
= 15 V
Q
GATE
= 98 nC (Maximum)
I
LKGS
= 100 nA (Maximum)
I
LKCAP
= 0 (Ceramic Capacitor)
I
QBS
= 120 µA (Maximum)
I
LK
= 50 µA (Maximum)
Q
LS
= 3 nC
T
ON
= 25 µs (Duty=50% at f
s
=20KHz)
I
LKDIODE
= 10 nA
If the maximum allowable voltage drop on the bootstrap
capacitor is 1.0V during the high side switch on state, the
minimum capacitor value is calculated by Equation 3.
Q
Total
=
(98
×
10
−
9
)
+
{(100
×
10
−
9
+
120
×
10
−
6
+
50
×
10
−
6
+
10
×
10
−
9
)
×
(25
×
10
−
6
)}
+
(3
×
10
−
9
)
=
105.2
×
10
−
9
[
C
]
(6)
3.2 Select the Bootstrap Resistor
When the external bootstrap resistor is used, the resistance,
R
BOOT
, introduces an additional voltage drop:
V
RBOOT
=
I
CHARGE
•
R
BOOT
t
CHARGE
(5)
where:
I
CHARGE
= Bootstrap capacitor charging current;
R
BOOT
= Bootstrap resistance; and
t
CHARGE
= Bootstrap capacitor charging time (the low-side
turn-on time).
Do not exceed the ohms (typically 5~10
Ω)
that increase the
V
BS
time constant. This voltage drop of bootstrap diode
must be taken into account when the maximum allowable
voltage drop (V
BOOT
) is calculated. If this drop is too high or
the circuit topology does not allow a sufficient charging
time, a fast recovery or ultra-fast recovery diode can be used.
4. Consideration of Bootstrap
Application Circuits
4.1 Bootstrap Startup Circuit
The bootstrap circuit is useful in high-voltage gate driver, as
shown in Figure 1. However, it has a initial startup and lim-
ited charging a bootstrap capacitor problem when the source
of the main MOSFET (Q1) and the negative bias node of
bootstrap capacitor (C
BOOT
) are sitting at the output voltage.
Bootstrap diode (D
BOOT
) might be reverse biased at startup
and main MOSFET (Q1) has a insufficient turn-off time for
the bootstrap capacitor to maintain a required charge, as
shown in Figure 1.
In certain applications, like in battery chargers, the output
voltage might be present before input power is applied to the
converter. Delivering the initial charge to the bootstrap
capacitor (C
BOOT
) might not be possible, depending on the
potential difference between the supply voltage (V
DD
) and
output voltage (V
OUT
) levels. Assuming there is enough
voltage differential between input voltage (V
DC
) and output
voltage (V
OUT
), a circuit comprised of startup resistor
(R
START
), startup diode (D
START
), and Zener diode (D
Z
) can
solve the problem, as shown in Figure 14. In this startup cir-
cuit, startup diode D
START
serves as a second bootstrap
diode used for charging the bootstrap capacitor (C
BOOT
) at
power up. Bootstrap capacitor (C
BOOT
) is charged to the
Zener diode of D
Z
, which is supposed to be higher than the
driver's supply voltage (V
DD
) during normal operation. The
charge current of the bootstrap capacitor and the Zener cur-
rent are limited by the startup resistor. For best efficiency,
the value of startup resistor should be selected to limit the
current to a low value, since the bootstrap path through the
startup diode is permanently in the circuit.
www.fairchildsemi.com
5
The value of bootstrap capacitor is calculated as follows:
C
BOOT
Q
TOTAL
105.2
×
10
−
9
=
=
≅
105[
nF
]
Δ
V
BOOT
1
(7)
The voltage drop due to the external diode is nearly 0.7V.
Assume the capacitor charging time is equal to the high-side
on-time (duty cycle 50%). According to different bootstrap
capacitor values, the following equation applies:
Q
TOTAL
Δ
V
BOOT
= --------------------
-
C
BOOT
(8)
100nF
Δ
V
BOOT
= 1.05 V
150nF
Δ
V
BOOT
= 0.7 V
220nF
Δ
V
BOOT
= 0.48 V
570nF
Δ
V
BOOT
= 0.18 V
Suggested values are within the range of 100 nF ~ 570 nF,
but the right value must be selected according to the applica-
tion in which the device is used. When the capacitor value is
too large, the bootstrap charging time slows and the low-side
on time might be not long enough to reach the bootstrap volt-
age.
© 2008 Fairchild Semiconductor Corporation
Rev. 1.4 • 12/18/14
京公网安备 11010802033920号
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved
评论