Open NAND Flash Interface Specification
Revision 3.2
06 12 2013
Intel Corporation
Micron Technology, Inc.
Phison Electronics Corp.
SanDisk Corporation
SK Hynix, Inc.
Sony Corporation
Spansion
This 3.2 revision of the Open NAND Flash Interface specification ("Final Specification") is
available for download at www.onfi.org.
SPECIFICATION DISCLAIMER
THIS SPECIFICATION IS PROVIDED TO YOU “AS IS” WITH NO WARRANTIES
WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE. THE AUTHORS OF THIS
SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF
ANY PROPRIETARY RIGHTS, RELATING TO USE OR IMPLEMENTATION OF INFORMATION
IN THIS SPECIFICATION. THE AUTHORS DO NOT WARRANT OR REPRESENT THAT SUCH
USE WILL NOT INFRINGE SUCH RIGHTS. THE PROVISION OF THIS SPECIFICATION TO
YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS.
Copyright 2005-2013, Intel Corporation, Micron Technology, Inc., Phison Electronics Corp.,
SanDisk Corporation, SK Hynix, Inc., Sony Corporation, Spansion. All rights reserved.
For more information about ONFI, refer to the ONFI Workgroup website at www.onfi.org.
All product names are trademarks, registered trademarks, or servicemarks of their respective
owners.
ONFI Workgroup Technical Editor:
mailto:
Terry Grunzke
Micron Technology
8000 S. Federal Way
Boise, ID 83707-0006 USA
Tel:
(208)-368-4960
Email: tmgrunzke@micron.com
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Table of Contents
Introduction ............................................................................................................................... 1
1.1. Goals and Objectives ........................................................................................................ 1
1.2. EZ NAND Overview .......................................................................................................... 1
1.3. References ........................................................................................................................ 1
1.4. Definitions, abbreviations, and conventions ...................................................................... 1
1.4.1.
Definitions and Abbreviations .................................................................................... 1
1.4.2.
Conventions ............................................................................................................... 5
2. Physical Interface ..................................................................................................................... 9
2.1. TSOP-48 and WSOP-48 Pin Assignments ....................................................................... 9
2.2. LGA-52 Pad Assignments ............................................................................................... 12
2.3. BGA-63 Ball Assignments ............................................................................................... 14
2.4. BGA-100 Ball Assignments ............................................................................................. 18
2.5. BGA-152 and BGA-132 Ball Assignments ...................................................................... 21
2.6. BGA-272 and BGA-316 Ball Assignments ...................................................................... 24
2.7. Signal Descriptions ......................................................................................................... 30
2.8. CE_n Signal Requirements ............................................................................................. 48
2.8.1.
Requirements for CLK (NV-DDR) ............................................................................ 48
2.9. Absolute Maximum DC Ratings ...................................................................................... 48
2.10.
Recommended DC Operating Conditions ................................................................... 49
2.10.1.
I/O Power (VccQ) and I/O Ground (VssQ) ........................................................... 49
2.11.
AC Overshoot/Undershoot Requirements ................................................................... 50
2.12.
DC and Operating Characteristics ............................................................................... 51
2.12.1.
Single-Ended Requirements for Differential Signals ............................................ 58
2.12.2.
VREFQ Tolerance ................................................................................................ 58
2.13.
Calculating Pin Capacitance ....................................................................................... 59
2.14.
Staggered Power-up.................................................................................................... 60
2.15.
Power Cycle Requirements ......................................................................................... 60
2.16.
Independent Data Buses ............................................................................................. 60
2.17.
Bus Width Requirements ............................................................................................. 61
2.18.
Ready/Busy (R/B_n) Requirements ............................................................................ 61
2.18.1.
Power-On Requirements ...................................................................................... 61
2.18.2.
R/B_n and SR[6] Relationship ............................................................................. 62
2.19.
Write Protect ................................................................................................................ 62
2.20.
CE_n Pin Reduction Mechanism ................................................................................. 63
2.20.1.
Volume Appointment when CE_n Reduction Not Supported .............................. 66
3. Memory Organization ............................................................................................................. 68
3.1. Addressing ...................................................................................................................... 69
3.1.1.
Multi-plane Addressing ............................................................................................ 70
3.1.2.
Logical Unit Selection .............................................................................................. 71
3.1.3.
Multiple LUN Operation Restrictions ........................................................................ 71
3.2. Volume Addressing ......................................................................................................... 72
3.2.1.
Appointing Volume Address .................................................................................... 72
3.2.2.
Selecting a Volume .................................................................................................. 72
3.2.3.
Multiple Volume Operations Restrictions ................................................................. 72
3.2.4.
Volume Reversion.................................................................................................... 73
3.3. Factory Defect Mapping .................................................................................................. 75
3.3.1.
Device Requirements............................................................................................... 75
3.3.2.
Host Requirements .................................................................................................. 75
3.4. Extended ECC Information Reporting ............................................................................. 76
3.4.1.
Byte 0: Number of bits ECC correctability ............................................................... 76
3.4.2.
Byte 1: Codeword size ............................................................................................. 77
3.4.3.
Byte 2-3: Bad blocks maximum per LUN ................................................................. 77
3.4.4.
Byte 4-5: Block endurance ....................................................................................... 77
3.5. Discovery and Initialization.............................................................................................. 77
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3.5.1.
Discovery without CE_n pin reduction ..................................................................... 77
3.5.2.
Discovery with CE_n pin reduction .......................................................................... 78
3.5.3.
Target Initialization ................................................................................................... 81
4. Data Interface and Timing ...................................................................................................... 82
4.1. Data Interface Type Overview ........................................................................................ 82
4.2. Signal Function Assignment............................................................................................ 82
4.3. Bus State ......................................................................................................................... 83
4.3.1.
SDR.......................................................................................................................... 83
4.3.2.
NV-DDR ................................................................................................................... 84
4.3.3.
NV-DDR2 ................................................................................................................. 85
4.3.4.
Pausing Data Input/Output ...................................................................................... 85
4.4. NV-DDR / NV-DDR2 and Repeat Bytes ......................................................................... 86
4.5. Data Interface / Timing Mode Transitions ....................................................................... 86
4.5.1.
SDR Transition from NV-DDR or NV-DDR2 ............................................................ 86
4.5.2.
NV-DDR2 Recommendations .................................................................................. 87
4.6. Test Conditions ............................................................................................................... 87
4.6.1.
SDR Only ................................................................................................................. 87
4.6.2.
Devices that Support Driver Strength Settings ........................................................ 88
4.7. I/O Drive Strength ........................................................................................................... 88
4.8. Output Slew Rate ............................................................................................................ 89
4.9. Capacitance .................................................................................................................... 93
4.9.1.
Capacitance Requirements (Informative) ................................................................ 95
4.10.
Impedance Values ....................................................................................................... 97
4.10.1.
NV-DDR ............................................................................................................... 98
4.10.2.
NV-DDR2 ........................................................................................................... 100
4.11.
Input Slew Rate Derating .......................................................................................... 100
4.11.1.
NV-DDR ............................................................................................................. 101
4.11.2.
NV-DDR2 ........................................................................................................... 101
4.12.
Differential Signaling (NV-DDR2) .............................................................................. 108
4.13.
Warmup Cycles (NV-DDR2) ...................................................................................... 109
4.14.
On-die Termination (NV-DDR2) ................................................................................ 110
4.14.1.
Self-termination ODT.......................................................................................... 111
4.14.2.
Matrix Termination.............................................................................................. 112
4.15.
Timing Parameters .................................................................................................... 119
4.15.1.
General Parameters ........................................................................................... 120
4.15.2.
SDR .................................................................................................................... 122
4.15.3.
NV-DDR ............................................................................................................. 123
4.15.4.
NV-DDR2 ........................................................................................................... 124
4.16.
Timing Modes ............................................................................................................ 125
4.16.1.
SDR .................................................................................................................... 125
4.16.2.
NV-DDR ............................................................................................................. 127
4.16.3.
NV-DDR2 ........................................................................................................... 130
4.17.
Timing Diagrams ....................................................................................................... 135
4.17.1.
SDR .................................................................................................................... 135
4.17.2.
NV-DDR ............................................................................................................. 143
4.17.3.
NV-DDR2 ........................................................................................................... 154
5. Command Definition ............................................................................................................. 160
5.1. Command Set ............................................................................................................... 160
5.2. Command Descriptions ................................................................................................. 163
5.3. Reset Definition ............................................................................................................. 167
5.4. Synchronous Reset Definition ....................................................................................... 167
5.5. Reset LUN Definition ..................................................................................................... 168
5.6. Read ID Definition ......................................................................................................... 169
5.7. Read Parameter Page Definition .................................................................................. 173
5.7.1.
Parameter Page Data Structure Definition ............................................................ 175
5.7.2.
Extended Parameter Page Data Structure Definition ............................................ 192
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5.8. Read Unique ID Definition............................................................................................. 195
5.9. Block Erase Definition ................................................................................................... 197
5.10.
Read Status Definition ............................................................................................... 197
5.11.
Read Status Enhanced Definition ............................................................................. 202
5.12.
Read Status and Read Status Enhanced required usage ........................................ 202
5.13.
Status Field Definition................................................................................................ 203
5.14.
Read Definition .......................................................................................................... 204
5.15.
Read Cache Definition............................................................................................... 206
5.16.
Page Program Definition ........................................................................................... 210
5.17.
Page Cache Program Definition ................................................................................ 212
5.18.
Copyback Definition................................................................................................... 215
5.19.
Small Data Move ....................................................................................................... 220
5.20.
Change Read Column Definition ............................................................................... 223
5.21.
Change Read Column Enhanced Definition ............................................................. 223
5.22.
Change Write Column Definition ............................................................................... 227
5.23.
Change Row Address Definition ............................................................................... 227
5.24.
Volume Select Definition ........................................................................................... 229
5.25.
ODT Configure Definition .......................................................................................... 230
5.26.
Set Features Definition .............................................................................................. 232
5.27.
Get Features Definition.............................................................................................. 236
5.28.
Feature Parameter Definitions .................................................................................. 237
5.28.1.
Timing Mode ....................................................................................................... 238
5.28.2.
NV-DDR2 Configuration ..................................................................................... 238
5.28.3.
I/O Drive Strength............................................................................................... 240
5.28.4.
External Vpp Configuration ................................................................................ 240
5.28.5.
Volume Configuration ......................................................................................... 241
5.28.6.
EZ NAND control ................................................................................................ 241
6. Multi-plane Operations ......................................................................................................... 243
6.1. Requirements ................................................................................................................ 243
6.2. Status Register Behavior .............................................................................................. 244
6.3. Multi-plane Page Program ............................................................................................ 244
6.4. Multi-plane Copyback Read and Program .................................................................... 247
6.5. Multi-plane Block Erase ................................................................................................ 250
6.6. Multi-plane Read ........................................................................................................... 252
7. Behavioral Flows .................................................................................................................. 258
7.1. Target behavioral flows ................................................................................................. 258
7.1.1.
Variables ................................................................................................................ 258
7.1.2.
Idle states ............................................................................................................... 258
7.1.3.
Idle Read states ..................................................................................................... 260
7.1.4.
Reset command states .......................................................................................... 262
7.1.5.
Read ID command states ...................................................................................... 264
7.1.6.
Read Parameter Page command states................................................................ 265
7.1.7.
Read Unique ID command states .......................................................................... 266
7.1.8.
Page Program and Page Cache Program command states ................................. 267
7.1.9.
Block Erase command states ................................................................................ 270
7.1.10.
Read command states ....................................................................................... 272
7.1.11.
Set Features command states ........................................................................... 274
7.1.12.
Get Features command states ........................................................................... 275
7.1.13.
Read Status command states ............................................................................ 275
7.1.14.
Read Status Enhanced command states ........................................................... 276
7.1.15.
Volume Select command states ......................................................................... 276
7.1.16.
ODT Configure command states ........................................................................ 277
7.2. LUN behavioral flows .................................................................................................... 278
7.2.1.
Variables ................................................................................................................ 278
7.2.2.
Idle command states .............................................................................................. 278
7.2.3.
Idle Read states ..................................................................................................... 280
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