Application Note: Xilinx Families
R
Xilinx In-System Programming Using an
Embedded Microcontroller
Contact: Randal Kuramoto
XAPP058 (v4.1) March 6, 2009
Summary
Xilinx® high-performance CPLD, FPGA, and configuration PROM families provide in-system
programmability, reliable pin locking, and IEEE Std 1149.1 (JTAG) boundary-scan test
capability. This powerful combination of features allows designers to make significant changes
and yet keep the original device pinouts, thus, eliminating the need to re-tool PC boards. By
using an embedded processor to program these CPLDs and FPGAs from an onboard RAM or
EPROM, designers can easily upgrade, modify, and test designs, even in the field.
Xilinx Families
This application note can be used with the following Xilinx device families: Virtex® series,
Spartan® series, CoolRunner® series, XC9500 series, Platform Flash PROM family, and
XC18V00 family.
Introduction
The Xilinx CPLD and FPGA families combine superior performance with an advanced
architecture to create new design opportunities that were previously impossible. The
combination of in-system programmability, reliable pin locking, and JTAG test capability gives
the following important benefits:
•
•
•
•
•
Reduces device handling costs and time to market
Saves the expense of laying out new PC boards
Allows remote maintenance, modification, and testing
Increases the life span and functionality of products
Enables unique, customer-specific features
By using a simple JTAG interface, Xilinx devices are easily programmed and tested without
using expensive hardware. Multiple devices can be daisy-chained, permitting a single four-wire
Test Access Port (TAP) to control any number of Xilinx devices or other JTAG-compatible
devices. The four mandatory signals comprising the JTAG TAP are:
•
•
•
•
Test Clock (TCK)
Test Mode Select (TMS)
Test Data Input (TDI)
Test Data Output (TDO)
The processor and JTAG chain schematic shown in
Figure 1, page 2
can help designers
achieve these unprecedented benefits by providing a simple means for programming Xilinx
CPLDs and FPGAs from design information stored in the embedded processor memory space.
This design can be modified for remote downloading applications and the included reference C
code can be compiled for the designer’s processor of choice.
© 2001–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
XAPP058 (v4.1) March 6, 2009
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Introduction
R
X-Ref Target - Figure 1
Xilinx 14-pin JTAG
Ribbon Cable Header
(1)
1
GND
GND
GND
GND
GND
GND
PGND
(2)
VREF
TMS
TCK
TDO
TDI
N/C
N/C
14
VCC
10 kΩ
(2)
10 kΩ
10 kΩ
10 kΩ
2-1 MUX
(2)
SEL_A/B
A1
A2
A3
TMS
(4)
Q1
B1
(5)
Q2 TCK
B2
TDI
Q3
B3
J1
(3)
Code
Memory
XAPP058
Code
Processor
GPIO_TMS
GPIO_TCK
GPIO_TDI
GPIO_TDO
CPLD
TMS_Test_Point
(6)
TCK_Test_Point
(6)
TDI_Test_Point
(6)
TDO_Test_Point
(6)
TMS
TCK
TDI TDO
PROM
TMS
TCK
TDI TDO
FPGA
TMS
TCK
TDI TDO
Data
Memory
XSVF
File
Other
JTAG
Devices
Device
TMS
TCK
TDI
TDO
X058_01_022309
Figure 1:
Notes:
Microcontroller and JTAG Chain Schematic
1. A JTAG cable header is required for prototype design downloading, production in-system
programming, boundary-scan testing, and design/configuration debugging.
2. The 2-1 MUX is an example implementation from the
Platform Cable USB II
data sheet
[Ref 1]
that multiplexes control between the Xilinx JTAG cable and processor. The pull-up
resistor on the MUX SEL_A/B signal selects the processor as the default controller. PGND
drives Low to select the cable as the JTAG controller. See
[Ref 1]
for details regarding the
pseudo-ground (PGND) pin on the 14-pin ribbon cable connector.
3. Jumper J1 is necessary to provide a method of switching the MUX to external JTAG
controllers, JTAG connectors, or software that does not support the PGND function.
4. The TCK and TMS signals should be buffered and routed to minimize skew between TMS
and TCK.
5. The integrity of the JTAG TCK signal is critical. Apply clock distribution and termination
design practices to the TCK signal.
6. Test points on the JTAG signals enable oscilloscope or logic analyzer access for verification
and debug of the in-system programming implementation.
To create device programming files, Xilinx provides iMPACT tool, included with the ISE®
software. The iMPACT software reads standard JEDEC/BIT/MCS/EXO device programming
files and converts them to a compact binary format XSVF format that can be stored in the
onboard flash or RAM. The XSVF format contains both data and programming instructions for
the CPLDs, FPGAs, and configuration PROMs. JEDEC files contain design information for
CPLDs, BIT files for FPGAs, and MCS/EXO files for configuration PROMs. The processor
reference code interprets the XSVF information and applies the corresponding JTAG signal
sequence to program the Xilinx devices.
Figure 2, page 3
shows the software flow from the
design file to the XSVF programming file that is interpreted in the embedded system to program
the Xilinx devices.
XAPP058 (v4.1) March 6, 2009
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Programming Xilinx CPLDs, FPGAs, and Configuration PROMs
R
X-Ref Target - Figure 2
iM P A C T
S
o ftw a re
(Boundary-Scan [JTAG] Chain)
CPLD
TDI
Jedec
(.jed)
File
PROM
PROM
(.mcs/.exo)
File
FPGA
Bitstream
(.bit)
File
Other
JTAG
Devices
Device
BSDL
(.bsd)
File
TDO
iMPACT generates XSVF file
containing JTAG instructions
for device programming
Embedded
System
Board
XSVF
(.xsvf)
File
Data Memory
XSVF
Interpreter
Processor
JTAG
Device
Chain
On
Board
X058_02_020609
Figure 2:
XSVF File Generation Flow to Embedded System
The files and utilities associated with this application note are available in a package for
downloading from:
https://secure.xilinx.com/webreg/clickthrough.do?cid=113970
Programming
Xilinx CPLDs,
FPGAs, and
Configuration
PROMs
Serial Vector Format (SVF) is a syntax specification for describing high-level IEEE Std 1149.1
(JTAG) bus operations. SVF was developed by Texas Instruments and has been adopted as a
standard for data interchange by JTAG test equipment and software manufacturers such as
Teradyne, Tektronix, and others. Xilinx CPLDs, FPGAs, and configuration PROMs accept
programming and JTAG boundary-scan test instructions in SVF format, via the JTAG test
access port (TAP). The timing for these TAP signals is shown in
Figure 8, page 12.
Since the
SVF format is ASCII and has larger memory requirements, it is inefficient for embedded
applications. Therefore, to minimize the memory requirements, SVF is converted into a more
compact (binary) format called XSVF.
Note:
For a description of the SVF and XSVF commands and file formats, see
[Ref 2].
The iMPACT software tool, included with ISE software, can output the device programming
commands and data to an SVF file or to a compact XSVF file. The XSVF file is appropriate for
use with the reference C code. The SVF is useful as a human-readable reference of the
underlying XSVF contents. In this design, the reference C code interprets the XSVF file and
provides the required JTAG TAP stimulus to the target, performing the programming and
(optional) test operations originally specified in the XSVF file. The combination of iMPACT
software, the XSVF file format encapsulating the programming instructions and design data,
and reference C code, enables a simple software flow for programming Xilinx devices in system
from an embedded processor.
The flow for creating the programming files that are used with this design are shown in
Figure 3,
page 4, Figure 4, page 4,
and
Figure 5, page 5.
XAPP058 (v4.1) March 6, 2009
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Programming Xilinx CPLDs, FPGAs, and Configuration PROMs
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X-Ref Target - Figure 3
Create PROM File (MCS/EXO)
from FPGA Bitstream(s) with
iMPACT or PROMGen.
Convert PROM File to
XSVF File Using
iMPACT
Using ISE
Software Tools
Create Intel
Hex File
Appendix-B c-code can
be used if embedded
processor cannot convert
binary to hex.
Program onboard RAM
or EPROM with Hex File
containing XSVF Code
X058_03_020609
Figure 3:
X-Ref Target - Figure 4
Configuration PROM Programming File Creation and Storage Flow
Create
Design
Using ISE
Software Tools
Sythesize and
Translate Design
Fit Design
Generate a JEDEC
Programming File
Convert JEDEC File
to XSVF File with
iMPACT
Appendix-B c-code can be used
if embedded processor cannot
convert binary to hex.
Create Intel
Hex File
Program onboard RAM or EPROM
with Hex file containing XSVF Code
X058_04_020609
Figure 4:
CPLD Programming File Creation and Storage Flow
XAPP058 (v4.1) March 6, 2009
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Programming Xilinx CPLDs, FPGAs, and Configuration PROMs
R
X-Ref Target - Figure 5
Create
Design
Using ISE
Software Tools
Translate and
Synthesize Design
MAP, Place and
Route Design
Generate Programming File
in Binary Format (bitstream)
with BitGen
Convert Bitstream to XSVF
File Using iMPACT
Create Intel
Hex File
Appendix-B c-code can
be used if embedded processor
cannot convert binary to hex.
Program onboard RAM
or EPROMwith Hex File
containing XSVF Code
X058_05_020609
Figure 5:
FPGA Programming File Creation and Storage Flow
Creating an XSVF File Using iMPACT Software
This procedure describes how to create an XSVF file from a FPGA, CPLD, or PROM
programming file. This flow assumes that the ISE software is being used. This software
package includes the Xilinx CPLD and FPGA implementation tools and the iMPACT
programming and file generation software.
iMPACT is supplied with both a graphical and batch user interface. The graphical tool can be
launched from the Project Manager. The batch tool is available by opening a shell and invoking
impact -batch
on the command line.
Using iMPACT Batch Tool to Create XSVF Files
After generating the programming files as specified in
Figure 3, page 4, Figure 4, page 4,
and
Figure 5, page 5,
the user can use the iMPACT batch tool to generate XSVF files:
1. Invoke the iMPACT batch tool from the command line in a new shell:
impact -batch
The following messages appear:
Release <Release Number> - iMPACT <Version Number>
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
2. Put iMPACT into boundary-scan mode using the following command:
setMode -bs
3. Define the ordered set of devices in the JTAG chain. For each device, add the device to the
JTAG chain using the following command:
addDevice -p # -file "filename.xxx"
where the
#
determines the position in the JTAG chain and
filename.xxx
is the full path
to the file that represents the device being added. Position 1 is the device closest to the
XAPP058 (v4.1) March 6, 2009
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