The DS90CR218A receiver deserializes three input LVDSdata streams into 21 bits of CMOS/TTL output data. Whenoperating at the maximum input clock rate of 85 Mhz, theLVDS data is received at 595 Mbps per data channel for atotal data throughput of 1.785 Gbit/sec (233 Mbytes/sec).The narrow bus and LVDS signalling of the DS90CR218A isan ideal means to solve EMI and cable size problems associatedwith wide, high-speed TTL interfaces.
猜您喜欢
推荐内容
开源项目推荐 更多
热门活动
热门器件
用户搜过
随便看看
热门下载
热门文章
热门标签
评论