The AD5382 contains a 14-bit data bus, DB13–DB0. Depend-ing on the value of REG1 and REG0 (see Table 11), this data is loaded into the addressed DAC input registers (x1), offset (c) registers, or gain (m) registers. The format data, offset (c), and gain (m) register contents are shown in Table 12 to Table 14.
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