如何用HDL中设计高效率的比较器COLUMNCreating the Most Efficient Comparatorsby Roberta Fulton, Technical Marketing Engineer, Xilinx, roberta.fulton@xilinx.comHDL ADVISORTHE XILINXComparators are best modeled with word-wise compares within a PROCESS or an ALWAYS block that contains the IF statement and an ELSE clause, and no ELSE-IF clauses. Conditional signal assignments in VHDL or conditional continuous assignments in Verilog could be used, but at a high cost in simulation time. Without the sensitivity list in VHDL or the event list in Verilog the simulators would constantly be checking the statements even when the inputsComparator A - Bit by Bit Comparelibrary IEEE; use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all; entity COMPARATOR_A is port (AIN1, AIN2: in unsigned(7 downto 0); AEQ: out std_logic); en……
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