This document provides practical, common guidelines for incorporating PCI Express interconnectlayouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10-layer or more server baseboard designs. Guidelines and constraints in this document are intendedfor use on both baseboard and add-in card PCB designs. This includes interconnects between PCIExpress devices located on the same baseboard (chip-to-chip routing) and interconnects betweena PCI Express device located “down” on the baseboard and a device located “up” on an add-incard attached through a connector.This document is intended to cover all major components of the physical interconnect includingdesign guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in cardedge-finger and connector considerations. The intent of the guidelines and examples is to helpensure that good high-speed signal design practices are used and that the timing/jitter andloss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect.However, while general physical guidelines and suggestions are given, they may not necessarilyguarantee adequate performance of the interconnect for all layouts and implementations.Therefore, designers should consider modeling and simulation of the interconnect in order toensure compliance to all applicable specifications.The document is composed of two main sections. The first section provides an overview ofgeneral topology and interconnect guidelines. The second section concentrates on physical layoutconstraints where bulleted items at the beginning of a topic highlight important constraints, whilethe narrative that follows offers additional insight.
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