Application Note Spartan6 Virtex6 7 Series and Zynq7000 Devices Parameterizable CORDICBased FloatingPoint Library Operations Authors Nikhil Dhume and Ramakrishnan Srinivasakannan XAPP552 v10 June 1 2012 Summary Introduction This application note presents a design methodology using the Xilinx System Generator for DSP tool to create a parameterizable floatingpoint library computation method for trigonometric power and logarithmic operations based on the coordinate rotational digital computer C......
Application Note: Spartan-6, Virtex-6, 7 Series, and Zynq-7000 Devices
Parameterizable CORDIC-Based
Floating-Point Library Operations
XAPP552 (v1.0) June 1, 2012
Authors: Nikhil Dhume and Ramakrishnan Srinivasakannan
Summary
This application note presents a design methodology using the Xilinx System Generator for
DSP tool to create a parameterizable floating-point library computation method for
trigonometric, power, and logarithmic operations based on the coordinate rotational digital
computer (CORDIC) algorithm
[Ref 1].
The design methodology leverages the fixed-point
CORDIC LogiCORE™ IP v5.0 block, along with floating-point building blocks such as adders,
multipliers, comparators, ROM, and FIFOs to create a set of floating-point CORDIC functions
that can be used as building blocks in applications. These functions are an essential requisite
in a wide range of engineering applications such as image processing, manipulator kinematics,
radar signal processing, robotics, and optimization processes in which a large number of
trigonometric or power operations must be computed in an efficient manner. The library has
been designed using System Generator for DSP, version 13.4, and supports single- and
double-precision input as defined by the IEEE 754 floating-point standard
[Ref 2].
Introduction
The arithmetic unit is one of the important components of CPU design. For computation of
complex arithmetic functions on hardware, the CORDIC algorithm is an attractive fixed-point
algorithm that uses a sequence of simple “shift and add” operations to compute a wide variety
of arithmetic functions. However, many applications are required to work not only with high
precision but also a large dynamic range. Floating-point arithmetic is a feasible solution for such
high-performance systems providing a dynamic range for representing real numbers and
capabilities to retain resolution and accuracy.
Floating-Point Solution for Xilinx FPGAs
Xilinx FPGAs have long been used to implement fixed-point DSP and video algorithms in
hardware. The flexibility of programmable logic allows fixed-point arithmetic to use custom bit
widths that are not bound to the 8-, 16-, or 32-bit boundaries of a fixed-point processor.
Fixed-point bit widths can grow as needed to accommodate applications that require large
dynamic range. However, as the dynamic range needs to grow, a fixed-point implementation
becomes increasingly expensive. Although floating-point solutions on FPGAs are inherently
slower than contemporary processors, the inherent massive parallelism allows these solutions
to be competitive to the software equivalent. For this reason, FPGAs are increasingly being
used as floating-point accelerators. To benefit from the parallelism, there is a requirement to
use hardware-efficient algorithms for FPGAs. More complex floating-point systems on FPGAs
require good implementations of elementary functions such as logarithmic, power, and
trigonometric. The System Generator for DSP tool meets this demand by supporting design
and implementation of floating-point algorithms from within the Simulink modeling environment.
System Generator for DSP also has the flexibility of optimizing an implementation that is bit-
and cycle-accurate to the original model. This library has been designed as an extension for
customers familiar with the flow of the System Generator for DSP tool.
States and other countries. AMBA and ARM are registered trademarks of ARM in the EU and other countries. All other trademarks are the property of their respective owners.
XAPP552 (v1.0) June 1, 2012
www.xilinx.com
1
Fixed-Point CORDIC Algorithm
Fixed-Point CORDIC Algorithm
CORDIC algorithms are a class of iterative solutions for trigonometric and other transcendental
functions that use only shifts and adds to perform. The trigonometric functions are
implemented based on vector rotation. Incremental functions such as logarithm and power are
performed with a simple extension to the hardware architecture and, while not CORDIC in the
strictest sense, are often included because of close similarity. A detailed study of the algorithm
is given in
Fixed-Point CORDIC Algorithm.
Design Approach
A floating-point library for CORDIC trigonometric functions has been developed using the
fixed-point CORDIC block and other basic blocks. The approach chosen has been to use
underlying trigonometric relations to extend the range of the fixed-point CORDIC algorithm.
The input floating-point number is passed through a range reduction step and then processed
with a fixed-point CORDIC block. The range reduction step reduces the input range to the one
allowed by the fixed-point CORDIC algorithm. A post-processing step performs the inverse of
the range reduction step after fixed-point computation. This approach is detailed in
Figure 1.
The library has been made parameterizable to ensure maximum flexibility. The floating-point
CORDIC library presented in this application note has been implemented using the Xilinx IP
portfolio. System Generator for DSP, version 13.4, was used to implement the flow.
X-Ref Target - Figure 1
Input Floating-
Point Number
Range
Reduction
Fixed-Point
Algorithm
Range
Extension
Output Floating-
Point Number
Exception
Handling
X552_01_042612
Figure 1:
Approach Chosen for Floating-Point CORDIC Library
Fixed-Point
CORDIC
Algorithm
The CORDIC algorithm was initially designed to perform vector rotation, where the vector (X,Y)
is rotated through an angle
θ
yielding a new vector (X',Y'). The vector rotation equations are:
X′
=
(
cos
( θ ) ×
X
–
sin
( θ ) ×
Y
)
Y′
=
(
cos
( θ ) ×
Y
+
sin
( θ ) ×
X
)
θ′
=
0
Equation 1
Equation 2
Equation 3
The CORDIC algorithm performs a vector rotation as a sequence of successively smaller
rotations, each of angle atan(2
-i
), known as micro rotations.
Equation 4
through
Equation 6
show the expression for the
i
th
iteration, where
i
is the iteration index from 0 to
n.
The
expression for the
i
th
micro rotation is:
X
i
+
1
=
x
i
–
α
i
×
y
i
×
2
y
i
+
1
=
y
i
+
α
i
×
x
i
×
2
–
i
Equation 4
Equation 5
Equation 6
–
i
–
i
θ
i
+
1
=
θ
i
–
α
i
×
atanh
(
2
)
Where
α
i
is the direction of rotation and can have a value of ±1.
A detailed description of the CORDIC algorithm is given in
Floating-Point Algorithms
and
Library Interface Specifications, page 10.
XAPP552 (v1.0) June 1, 2012
www.xilinx.com
2
Floating-Point Algorithms
Floating-Point
Algorithms
Floating-Point CORDIC sin-cos
The rotational mode of fixed-point CORDIC can be used to simultaneously compute the sine
(sin) and cosine (cos) of the input angle. Setting the
y
component of the input vector to zero
reduces the rotation mode to:
X
n
=
A
n
×
x
0
×
cos
( θ )
Y
n
=
A
n
×
x
0
×
sin
( θ )
Where
A
n
is a gain factor corresponding to the
i
th
micro rotation.
Equation 7
Equation 8
Range Enhancement
The range reduction step for the fixed-point CORDIC algorithm can be achieved by performing
an angle rotation on the input. The input is rotated to a value between –π and +π, which can
then be fed to the fixed-point CORDIC as input. This step is required because the fixed-point
CORDIC only converges for the range between –π and +π. The rotation of the angle can be
given by:
Rotated angle(x)
=
remainder(x, 2
× π )
–
π
Equation 9
Because
n
is subtracted from the remainder, there is an inherent reflection in this step which
needs to be adjusted for post-processing.
Algorithm
The steps in the algorithm are:
1. Range reduction: The input is rotated between –π and +π.
2. The fixed-point CORDIC block is used for computation of the sine and cosine of the
number, as detailed above.
3. Post-processing: A reflection operation is performed on the output of the fixed-point
CORDIC block.
Floating-Point CORDIC sinh-cosh
The close relationship between trigonometric and hyperbolic functions suggests that the same
architecture can be used to compute hyperbolic functions. The CORDIC equations for
hyperbolic rotations are derived by setting the
α
i
factor in
Equation 4, Equation 5,
and
Equation 6
by the amount shown in
Equation 10.
α
i
=
–1 if
i
<
0, +1 otherwise
\
Equation 10
This reduces the CORDIC output in rotation mode to
Equation 11
and
Equation 12.
x
n
=
A
n
× [
x
0
×
cosh
( θ
0
)
+
y
0
×
sinh
( θ
0
) ]
y
n
=
A
n
× [
x
0
×
cosh
( θ
0
)
+
y
0
×
sinh
( θ
0
) ]
A
n
=
Π
1
–
2
–
2i
Equation 11
Equation 12
Equation 13
≅
0.80
The value of hyperbolic sine (sinh) and hyperbolic cosine (cosh) can be found by setting y
0
to 0.
Range Enhancement
The range reduction for the hyperbolic functions can be found by splitting the input into
fractional and integer portions. The integer portion can be processed by means of a stored
look-up table (LUT). The fractional portion can be processed separately using a stored LUT.
Algorithm
The steps in the algorithm are:
XAPP552 (v1.0) June 1, 2012
www.xilinx.com
3
Floating-Point Algorithms
1. Range reduction: The input is reduced in range by first finding the absolute value of the
number and then splitting the number into integer (int) and fractional (frac) portions.
2. The
int
portion is processed by means of a stored LUT while the
frac
portion is processed
by means of a fixed-point CORDIC algorithm.
3. Post-processing: The outputs from the
int
and
frac
portions are combined using
Equation 14
and
Equation 15.
cosh
(
int
+
frac
)
=
cosh
(
int
) ×
cosh
(
frac
)
+
sinh
(
int
) ×
sinh
(
frac
)
sinh
(
int
+
frac
)
=
cosh
(
int
) ×
sinh
(
frac
)
+
cosh
(
frac
) ×
sinh
(
int
)
4. Final stage: A reflection operation is performed when the input is negative.
Equation 14
Equation 15
Floating-Point CORDIC Power
The algorithm for exponential (e
x
) is computed by using the sinh and cosh computed from
Floating-Point CORDIC sinh-cosh.
In addition to exponential, powers of 10 and 2 are supported
in the library.
Algorithm
1. The exponential value of a number can be calculated from the sinh and cosh from
Equation 16.
x
e
=
sinh
(
x
)
+
cosh
(
x
)
Equation 16
2. The power value of 10 and 2 is computed by the core from
Equation 17
and
Equation 18.
10
=
e
2
=
e
x
x
(
x
⋅
ln(10)
)
Equation 17
Equation 18
(
x
⋅
ln(2)
)
Floating-Point CORDIC atan
The floating-point CORDIC computes arctangent (atan (y/x)) directly using the vectoring mode
of the CORDIC rotator if the angle is initialized with 0. The argument must be presented as a
ratio of x/y. The angle accumulator output is given by
Equation 19.
–
1
x
0
θ
n
=
θ
0
+
tan
-----
y
0
Equation 19
Range Enhancement
The range reduction step is performed by removing the sign portion of the input numbers and
adjusting the input so that the imaginary part is always greater in magnitude than the real part.
This adjustment is done to ensure that the output angle is always present in the first quadrant.
Algorithm
The steps in the algorithm are:
1. The absolute value of the input is found, and real and imaginary portions are adjusted so
that the real portion is greater than the imaginary portion.
2. The fixed-point CORDIC atan is used to compute the output.
3. The output is rotated to the correct quadrant based on the input sign and whether the real
portion of the number is greater than the imaginary portion.
Floating-Point CORDIC log
The CORDIC logarithm (ln) is implemented using the hyperbolic vectoring mode of CORDIC.
The hyperbolic arctangent (atanh) can be used to compute log by using
Equation 20.
Logarithms to the base 10 and 2 are also supported.
XAPP552 (v1.0) June 1, 2012
www.xilinx.com
4
System Generator Implementation
w
–
1
ln
(
w
)
=
2
×
atanh
-------------
-
w
+
1
Equation 20
Range Enhancement
There is an inherent range reduction involved in the previous step. Using w–1 and w+1 ensures
that the real portion is always less than the imaginary portion and that the real portion is never
equal to the imaginary portion. If the real portion equals the imaginary portion, the output of
atanh goes to infinity (which cannot be represented by the fixed-point CORDIC block). The
other range reduction algorithm used is separation of input into the mantissa and exponent
portion, which are processed separately. The mantissa is processed by means of the
fixed-point CORDIC, and the exponent is processed by means of a multiplier.
Algorithm
The steps in the algorithm are:
1. Split the input into the exponent and mantissa portion. The exponent portion can be added
back to the processed mantissa at the end.
2. Process the mantissa by using the fixed-point CORDIC algorithm as mentioned above.
3. The log
10
and log
2
is found in the CORDIC core using
Equation 21.
log
(
w
)
log
b
(
w
)
=
----------------
-
log
(
b
)
Equation 21
System
Generator
Implementation
Setting Up the Library
For usage of the library in the System Generator for DSP tool, a patch has been created in the
TAR file contained in the reference design (see
Reference Design, page 16).
After the overlay
is installed, the library should appear similar to
Figure 2.
The patch works with the System
Generator for DSP tool, version 13.4 for nt, nt64, lin, and lin64 builds.
To set up the library:
1. Clear the MATLAB and System Generator for DSP tool caches using the using
xlCache ('clear all')
command.
2. Extract the patch on top of the IDS build using WinZip or the
tar –xvf
command.
3. Open the System Generator for DSP tool to the corresponding IDS build.
4. The floating-point blocks are now visible as a part of the reference blockset as a “Floating
Point” library.
5. These blocks are present as part of the library: Absolute, Conditional Negate, Floor-ceil,
京公网安备 11010802033920号
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved
评论