In the implementation of high-performance CMOS over-sampling A/D converters, high-speed comparators are indispensable. This paper discusses the design and analy-sis of a low-power regenerative latched CMOS compara-tor, based on an analytical approach which gives a deeper insight into the associated trade-offs. Calculation details and simulation results for a 20 MHz clocked comparator in a 0.5μm technology are presented.
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