Enhanced Equalization and Forward Correction Coding Technologies for 25+Gb/s Serial Link System
In this paper, signal integrity challenges for high speed serial links at 25 Gb/s, such as lossy channel, noisy environment, and high speed circuit design will be discussed. Potential solution spaces to address those challenges are investigated. Advanced equalization schemes like floating tap decision feedback equalizer (DFE) and infinite impulse response (IIR) DFE are studied. Meanwhile, different forward error correction (FEC) coding options are also explored to further improve system performance margin. The joint optimization between equalization and FEC in terms of overall system performance is studied. The paper demonstrates that enhanced signal processing enables 25+ Gb/s link performance for new 100 Gigabit Backplane Ethernet interfaces.
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